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1.5 Sketch a transistor-level schematic for a CMOS 4-input NOR gate

the truth table for a 4-input NOR gate.

W X Y Z OUT
0 0 0 0 1
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0

Figure 1: Truth table for 4-input NOR gate.

Observe from the truth table that the output is high when all of the input are low and that
the output is low when at least one of the inputs is high. This means that in the transistor
schematic, the PMOS transistors must be in series and the NMOS transistors must be in

Observe from the schematic that when all of the inputs are low the 4 NMOS transistors are
turned off so there is connection between the output and ground. The 4 PMOS transistors
on the other hand will all be on so the output will get pulled up to . If one of the inputs is

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high then the output cannot get pulled up to ; instead one of the NMOS transistors will
be turned on and the output will be pulled down to ground. Therefore this schematic acts
exactly like a 4 input NOR gate.

1.7 Use a combination of CMOS gates (represented by their symbols) to generate the following
functions from A, B, and C.
a) Y = A (buffer)
b) Y = A𝑩 + 𝑨B (XOR)
c) Y = 𝑨 𝑩+ AB (XNOR)
d) Y = AB + BC + AC (majority)

(a)

For the buffer we can just have two invertors in series so the following gate level
schematic accomplishes the buffer.

(b)

For the given logic function, we

have A and the inverse of B ANDed and this is ORed with the AND of A inverse and B.
Therefore the following gate level schematic accomplishes this logic function.

(c)

For the given logic function, we have A inverse and B inverse ANDed and this is ORed
with the AND of A and B. Therefore the following gate level schematic accomplishes this
logic function.

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(d)

For the given logic function we have each combination of the three inputs ANDed and then
those outputs are ORed together. Therefore the following gate level schematic
accomplishes this logic function.

Note that using DeMorgan’s law it can be shown that an AND gates followed by an OR
gate is the same as having NAND gates followed by one NAND gate. This means that for
the last three schematics the AND and OR gates can be replaced by NAND gates. If the
number of transistors is a concern than using NAND gates is the preferred choice since
less transistors would be needed.

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1.10 Sketch a stick diagram for a CMOS 4-input NOR gate from Exercise 1.5.

Observe that the PMOS transistors are all in series, so there needs to be no rectangle
drawn for the shared source and drain connections in the layout since the sources and
drains can be combined. The NMOS transistors are all in parallel and will require some
rectangles to connect all 4 drains and sources together. Therefore the stick diagram is
shown in Figure 2.

This book uses patterns, layout designers use dry-erase markers or colored pencils for
drawing stick diagrams.

In the stick diagram shown in Figure 2, there are indeed 4 PMOS transistors and 4 NMOS
transistors. The PMOS that A goes into has its source connected to VDD and the other 3
pmos are arranged in series with it. We also have the output Y connected to the drain of
the PMOS that D goes into. Also observe that the NMOS transistors are arranged in
parallel where all of their sources are connected to ground and the drains are connected to
the output. Therefore, the stick diagram does indeed match the schematic.

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1.11 Estimate the area of your 4-input NOR gate from Exercise 1.10.

From the stick diagram, observe that vertically and horizontally we need at least 5 metal
wires. Now if each wire is wide and needs a spacing of then the track pitch is
and there are 5 tracks both horizontally and vertically. Therefore the area would be
about times which is .

1.13 Figure 1.74 shows a stick diagram of a 2-input NAND gate. Sketch a side view (cross-
section) of the gate from X to Xe.

Refer the stick diagram of a 2-input NAND gate shown in Figure

1.74 in textbook. We have an nMOS transistor connected to
ground and that is in series with another NMOS transistor whose
drain is connected to the output. There is also PMOS transistors
whose drains are connected to the output and sources are
connected to .

Sketch, the side view sketch, taking into account that the pMOS
transistor needs an n-well is shown in Figure 1.

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1.16 Consider the design of a CMOS compound OR-AND-INVERT (OAI21) gate computing
F = (𝑨 + 𝑩) · 𝑪.
a) sketch a transistor-level schematic
b) sketch a stick diagram
c) estimate the area from the stick diagram
d) layout your gate with a CAD tool using unit-sized transistors e) compare the layout size to the
estimated area.

(a)

Consider the OR-AND-INVERT gate function,

Observe that A and B are ORed together which means that in the pull down network their
nMOS transistors will be in parallel. Now since C is ANDed with the OR of A and B its
nMOS will be in series with the two that are in parallel. The pull up network will have the
exact opposite arrangement with the pMOS transistors and since the entire expression has
an invert bar there will be no need for an extra inverter.

The transistor level schematic diagram is shown in Figure 1:

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(b)

The stick diagram for the circuit is shown in Figure 1 is shown in Figure 2:

Figure 2

(c)

For the stick diagram in Figure 2 observe that horizontally it has 4 metal rectangles in a
row. Now if each rectangle is wide and the spacing between them is then the
minimum width is .

Vertically the diagram has 6 metal rectangles so if each rectangle is tall and the
spacing between them is then the minimum height is . The width and height of the
stick diagram get an estimate of the area of the layout.

(d)

The layout diagram of the circuit in CAA tool is shown in Figure 3:

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Figure 3

(e)

Now measure the area of layout and compare it to the area estimate from the stick
diagram. Recall that is just half of the minimum width of a transistor in the process. The
actual layout area and its estimate should match or at least be very close. The layout
shown in Figure 3 has an area that matches the estimate.

1.17 Consider the design of a CMOS compound OR-OR-AND-INVERT (OAI22) gate computing
F = (𝑨 + 𝑩) · (𝑪 + 𝑫).
a) sketch a transistor-level schematic
b) sketch a stick diagram
c) estimate the area from the stick diagram
d) layout your gate with a CAD tool using unit-sized transistors
e) compare the layout size to the estimated area

(a)

Consider the following logical expression.

The transistors level schematic is shown in Figure 1:

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Figure 1

(b)

The stick diagram is shown in Figure 2:

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(c)

From Figure 2, observe that horizontally it has 5 metal rectangles in a row. Now if each
rectangle is wide and the spacing between them is then the minimum width is .

Vertically the diagram has 6 metal rectangles so if each rectangle is tall and the
spacing between them is then the minimum height is .

Calculate the area of the stick diagram:

(d)

The layout diagram using CAD tool is shown in Figure 3:

Figure 3

(e)

Now measure the area of layout and compare it to the area estimate from the stick
diagram. Recall that is just half of the minimum width of a transistor in the process. The
actual layout area and its estimate should match or at least be very close. The layout
shown in Figure 3 has an area that matches the estimate.

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1.18 A 3-input majority gate returns a true output if at least two of the inputs are true. A minority
gate is its complement. Design a 3-input CMOS minority gate using a single stage of logic.
a) sketch a transistor-level schematic
b) sketch a stick diagram
c) estimate the area from the stick diagram

(a)

Consider that a 3-input majority gate has three inputs and the output is true when at least
two of the inputs are true.

Consider the three inputs as A, B and C and the output as Y.

Write the truth table for the required condition.

Use the truth table in Table 1 to obtain the logic expression for the output Y.

Use the Boolean theorems and simplify the logic expression Y.

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Simplify the expression further.

Thus, the Boolean expression for the 3-input majority gate is,

Consider that the minority gate is the complement of majority gate. Therefore, the Boolean
expression of for the 3-input minority gate is,

Sketch a transistor-level schematic diagram for the logic expression of 3-input minority
gate.

Note that the combination of two NMOS transistors connected in series and two PMOS
transistors connected in parallel are connected in series to implement a NAND gate.

Note that the combination of two NMOS transistors connected in parallel and two PMOS
transistors connected in series are connected in series to implement a NOR gate.

It is clear from the equation that one set of the transistors with inputs B and C in the pull
down network are connected in parallel and a transistor with input A is connected in series
with the two that are in parallel to implement the expression . The other set of
transistors with inputs B and C are connected in series in the pull down network to
implement the expression BC which is in parallel with the rest of the pull down network.
The pull up network has the exact opposite arrangement since the entire expression is
inverted. There is no need for an extra inverter at the end.

The transistor-level schematic diagram for the logic expression of the 3-input minority gate
is,

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(b)

Use the transistor-level schematic diagram in Figure 1 to draw the stick diagram.

(c)

It is clear from the stick diagram that the vertical tracks are 7 and the horizontal tracks are
6 and each wire is of wide and needs a spacing of then the track pitch is of total
.

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The total horizontal track occupies a width of , that is and the total vertical track
occupies a length of , that is .

Calculate the area from the stick diagram.

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