1

FAST TWO-OPERAND ADDITION

A. Conventional number system.

Carry-propagate adders (CPA)
• Switched carry-ripple adder
• Carry-skip adder
• Carry-lookahead adder
• Prefix adder
• Carry-select adder and conditional-sum adder
• Variable-time adder
B. Redundant number system.
Totally-parallel adders (TPA); adders with limited carry propagation
• Carry-save adder
• Signed-digit adder

Digital Arithmetic - Ercegovac/Lang 2003 2 – Fast Two-Operand Adders

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n-BIT ADDITION

x + y + cin = 2ncout + s
The solution:
s = (x + y + cin) mod 2n

1 if (x + y + cin) ≥ 2n



cout = 


0 otherwise

= b(x + y + cin)/2nc

Digital Arithmetic - Ercegovac/Lang 2003 2 – Fast Two-Operand Adders

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X xi yi
Y
n n
cout cin ci+1 ci
ADDER FA

n
si
S
(a) (b)

Figure 2.1: (a) An n-bit adder. (b) 1-bit adder (full adder module).

Digital Arithmetic - Ercegovac/Lang 2003 2 – Fast Two-Operand Adders

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1-BIT ADDITION

• Primitive module full adder (FA)

xi + yi + ci = 2ci+1 + si
with solution
si = (xi + yi + ci) mod 2
ci+1 = b(xi + yi + ci)/2c

Digital Arithmetic - Ercegovac/Lang 2003 2 – Fast Two-Operand Adders

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ADDITION: TWO-STEP PROCESS

1. Obtain carries (carry at i depends on j ≤ i)

– non-trivial to do fast
2. Compute sum bits (local function)

X Y
n n

c 0 = cin

cout = c n Step 1:
Obtain carries

c n-1 ci c1 c0
yn-1 yi y1 y0
xn-1 xi x1 x0

Step 2:
Compute sum bits

sn-1 si s1 s0

Figure 2.2: Steps in addition.

Digital Arithmetic - Ercegovac/Lang 2003 2 – Fast Two-Operand Adders

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CARRY-OUT CASES

Case xi yi xi + yi ci+1 Comment

1 0 0 0 0 kill (stop) carry-in
2 0 1 1 ci propagate carry-in
1 0 1 ci propagate carry-in
3 1 1 2 1 generate carry-out

Case 1 (Kill): ki = x0iyi0 = (xi yi)0

Case 2 (Propagate): pi = xi ⊕ yi
Case 3 (Generate): gi = xiyi
Then
ci+1 = gi pici = xiyi (xi ⊕ yi)ci
Alternative (simpler) expression:
ci+1 = gi aici
Since ai = ki0 we call it ”alive”

Digital Arithmetic - Ercegovac/Lang 2003 2 – Fast Two-Operand Adders

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CARRY CHAINS

Two types:

1-carry chain consisting of carry=1

0-carry chain consisting of carry=0

i 9 8 7 6 5 4 3 2 1 0
xi 1 0 1 0 1 1 1 1 0 0
yi 0 0 0 1 0 1 0 0 1 0
p k p p p g p p p k
a a a a a a a a
ci+1 0 ← 0 1 ← 1 ← 1 ← 1 0 ← 0 ← 0 ← 0

Digital Arithmetic - Ercegovac/Lang 2003 2 – Fast Two-Operand Adders

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Generalization to group of bits

cj+1 = g(j,i) p(j,i)ci = g(j,i) a(j,i)ci

or, for i = 0
cj+1 = g(j,0) p(j,0)c0 = g(j,0) a(j,0)c0
Recursive combining of subranges of variables:
g(f,d) = g(f,e) p(f,e)g(e−1,d) = g(f,e) a(f,e)g(e−1,d)
a(f,d) = a(f,e)a(e−1,d)
p(f,d) = p(f,e)p(e−1,d)

Digital Arithmetic - Ercegovac/Lang 2003 2 – Fast Two-Operand Adders

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Generalization (cont.)

f e e-1 d

gL aL gR aR

g(f,e) a(f,e) g(e-1,d) a(e-1,d)

GA GA

g(f,d) a(f,d) gout aout

(a) (b)

Figure 2.3: Computing (g(f,d) , a(f,d) ).

Digital Arithmetic - Ercegovac/Lang 2003 2 – Fast Two-Operand Adders

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BASIC CARRY-RIPPLE ADDER (CRA)

y n-1 x n-1 yi xi y0 x0

c c i+1 ci
out =cn FA FA
c1
FA c 0 = c in

s n-1 si s0

Figure 2.4: Carry-ripple adder.

TCRA = (n − 1)tc + max (tc, ts)

Digital Arithmetic - Ercegovac/Lang 2003 2 – Fast Two-Operand Adders

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Implementations of full-adder

xi x’i
yi y’i
xi xi
y’i
c’i yi
x’i xi
yi ci+1
c’i ci
si yi
x’i c’i+1
y’i ci
ci
xi
yi
ci (a)

Half Adder (HA)

HA
xi pi
yi si
gi
ci+1
ci
(b)

xi pi
yi si
g’i
ci+1
ci

(c)

Figure 2.5: Implementation of full-adder. (a) Two-level network. (b) Multilevel network with xor, and and or gates; (c) Multilevel
implementation with xor and nand gates.

Digital Arithmetic - Ercegovac/Lang 2003 2 – Fast Two-Operand Adders

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SWITCHED CARRY-RIPPLE (Manchester) ADDER

yi xi

CC
(Chain Control) GKP
"0"
ki pi

(a) "1"
gi

ci+1 ci

y n-1 x n-1 y n-2 x n-2 yi xi y1 x1 y0 x0

CC CC CC CC CC

cin
ci
cout c n-1 ci+1 c2 c1

(b)

Figure 2.6: Switch carry-ripple network (Manchester circuit)

Digital Arithmetic - Ercegovac/Lang 2003 2 – Fast Two-Operand Adders

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CARRY-SKIP ADDER

(j) (j)
x y

CSK-m adder m m

(j+1) P (j) (j)

cin m-bit Carry-Ripple Adder cin
(j)
cout
(group j)
0
MUX

1
m
(j)
s
(a)

Module (n/m - 1) Module j Module 0

m m m m m m
CSK-m CSK-m CSK-m
ADDER ADDER ADDER
m m m

(b)

Figure 2.7: Carry-skip adder: (a) A group with carry bypass. (b) n-bit CSK adder.

Digital Arithmetic - Ercegovac/Lang 2003 2 – Fast Two-Operand Adders

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CARRY CHAINS IN CARRY-SKIP ADDER

group 3 group 2 group 1 group 0

X 0 1 1 0 1 1 0 0 1 0 0 0 1 1 0 1
Y 0 0 0 1 0 0 1 1 0 0 1 1 0 1 1 1
15 12 8 4 0
position
c16 c7 c3 c1
c8 c4 c2 2
c12 c9 c5
c13 c10 c 6 4
c14 c11
c15 6 carry-skip path
carry-ripple path
group size m = 4
t
Figure 2.8: Carry chains in carry-skip adder: A case with several carry chains.

Digital Arithmetic - Ercegovac/Lang 2003 2 – Fast Two-Operand Adders

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m-bit Carry-Ripple Adder

cn c0

MUX
MUX

MUX
sn-1 (a)

group 3 group 2 group 1 group 0

X 1 1 1 01 1 0 01 0 0 01 0 0 1
Y 0 0 0 10 0 1 10 1 1 10 1 1 1

15 12 8 4 0
position

c1
c2 2
c3
c4 4
c8 c5
c12 c9 c6 6
c16 c13 c10 c7
c14 c11 8
carry-skip path
c15 carry-ripple path
t group size m = 4

(b)

Figure 2.9: (a) Critical path in carry-skip adder. (b) The worst-case situation for n = 16.

Digital Arithmetic - Ercegovac/Lang 2003 2 – Fast Two-Operand Adders

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WORST-CASE DELAY

n
TCSK = mtc + tmux + ( − 2)tmux + (m − 1)tc + ts
m
n
= (2m − 1)tc + ( − 1)tmux + ts
m

Digital Arithmetic - Ercegovac/Lang 2003 2 – Fast Two-Operand Adders

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PROBLEM WITH CLEARING OF CARRIES

(j)
(j+1) cout (j)
cin cin
m-bit Carry-Ripple Adder
(group j)

(j)
P

Figure 2.10: Carry-skip adder using AND-OR for bypass

Digital Arithmetic - Ercegovac/Lang 2003 2 – Fast Two-Operand Adders

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GROUP SIZE IN CARRY-SKIP ADDERS

Fixed-size:
mopt = ( tmux
2tc n) 1/2
(minimum delay)
Topt ≈ (8tmuxtcn)1/2
Variable-size:
Group size
mi

Group i
M-1 0
M - number of groups
Figure 2.11: Optimal distribution of group sizes in carry-skip adder.

Digital Arithmetic - Ercegovac/Lang 2003 2 – Fast Two-Operand Adders

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CARRY-LOOKAHEAD ADDER(CLA)

x(k-1) y(k-1) x(j) y(j) x(1) y(1) x(0) y(0)

m m m m m m m m

cn CLA c2m cm c0
CLA CLA CLA
k-1 j 1 0
m m m m
k=n/m

s (k-1) s (j) s (1) s (0)

Figure 2.12: One-level carry-lookahead adder

Digital Arithmetic - Ercegovac/Lang 2003 2 – Fast Two-Operand Adders

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CARRY-LOOKAHEAD MODULE

y3 x3 y2 x2 y1 x1 y0 x0
CLA-4

gap gap gap gap

g3 a p3 g2 a2 p2 g1 a1 p 1 g0 a0 p 0
3
c4
CARRY LOOKAHEAD GENERATOR c0
G
(CLG-4)
A
c3 c2 c1
p3 p2 p1 p0

s3 s2 s1 s0

Figure 2.13: Carry-lookahead adder module (m = 4).

Digital Arithmetic - Ercegovac/Lang 2003 2 – Fast Two-Operand Adders

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CARRY-LOOKAHEAD GENERATOR

g3 a3 g2 a g1 a1 g0 a0
2

CLG-4

A
c
0
G

c c c c
4 3 2 1

Figure 2.14: 4-bit carry-lookahead generator CLG-4.

Digital Arithmetic - Ercegovac/Lang 2003 2 – Fast Two-Operand Adders

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TWO-LEVEL CARRY-LOOKAHEAD ADDER

carries from CLG-4 modules

(7) (6) (5) (4) (3) (2) (1)
c =c28 c =c24 c =c20 c =c16 c =c12 c =c8 c =c4

x7 y7 x6 y6 x5 y5 x4 y4 x3 y3 x2 y2 x1 y1 x0 y0
4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4

* * * * * * * * c
CLA-4 CLA-4 CLA-4 CLA-4 CLA-4 CLA-4 CLA-4 CLA-4 0
2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4

s7 s6 s5 s4 s3 s2 s1 s0

G A G A G A G A G A G A G A G A
7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0

CLG-4 CLG-4
(8)
c =c32
c (7)=c28 c (6)=c24 c (5)=c20 c (4)=c16 c (3)=c12 c (2)=c8 c (1)=c4

critical path

* Carry-out is not used carries to CLA-4 modules

Figure 2.15: Two-level carry-lookahead adder (n = 32)

Digital Arithmetic - Ercegovac/Lang 2003 2 – Fast Two-Operand Adders

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carries from CLG-2 modules
(3) (2) (1)
c =c6 c =c4 c =c2

x3 y3 x2 y2 x1 y1 x0 y0
2 2 2 2 2 2 2 2

* * * * c
CLA-2 CLA-2 CLA-2 CLA-2 0
2 2 2 2 2 2 2 2

s3 s2 s1 s0
(1) (1) (1) (1) c4 (1) (1) (1) (1)
G A3 G2 A 2 G1 A 1 G0 A 0
3

CLG-2 CLG-2

(3) (1)
(1)
G1 A 1
(1)
c =c6 G0 A 0
(2) (2) c =c2

c8
CLG-2

* Carry-out is not used

c4

Figure 2.16: Three-level carry-lookahead adder (n = 8, m = 2).

Digital Arithmetic - Ercegovac/Lang 2003 2 – Fast Two-Operand Adders

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Prefix adders

left2 right2 left1 right1 gL aL gR aR

g(left2,left1)
a(left2,left1)
g(right2,right1)
a(right2,right1)
2 2

GA GA

g(left2,right1) 2
a(left2,right1)
gout aout

(a) (b)

Figure 2.17: Composition of spans in computing (g, a) signals.

Digital Arithmetic - Ercegovac/Lang 2003 2 – Fast Two-Operand Adders

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( gL , aL ) ( gR, aR ) ( gL , aL ) gR
2 2 2

2 g out = g L + a L g R g out = g L + a L g R
( g out , a out ) a out = a L a R

(g7,a7 ) (g6,a6 ) (g5,a5 ) (g4,a4 ) (g3,a3 ) (g2,a2 ) (g1,a1 ) (g0,a0 )

c0
from position
2 g(2,1) g(0,-1) (-1)
g(6,5) g(4,3)
a(6,5) a(4,3) a(2,1)

g(6,3) g(5,3) g(2,-1) g(1,-1)

a(6,3) a(5,3)

g(6,-1) =c7 c6 c5 c4 c3 c2 c1 c0

p7 p p5 p4 p3 p2 p1 p0
6
XOR XOR XOR XOR XOR XOR XOR XOR

c8 s7 s6 s5 s4 s3 s2 s1 s0

Figure 2.18: 8-bit prefix adder. (Modules to obtain pi , gi , and ai signals not shown.)

Digital Arithmetic - Ercegovac/Lang 2003 2 – Fast Two-Operand Adders

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( gL , aL ) ( gR, aR ) ( gL , aL ) gR
2 2 2

2 g out = g L + a L g R g out = g L + a L g R
( g out , a out ) a out = a L a R

(g7,a7 ) (g6,a6 ) (g5,a5 ) (g4,a4 ) (g3,a3 ) (g2,a2 ) (g1,a1 ) (g0,a0 )

c
0

a(6,5) g(6,5) a(4,3) g(4,3) a(2,1) g(2,1) g(0,-1)

g(2,-1) g(1,-1)

g(4,-1) g(3,-1)

g(6,-1) =c7 g(5,-1)

c6 c c4 c3 c2 c1 c0
p7 p6 5 p p p p2 p1 p0
5 4 3
XOR XOR XOR XOR XOR XOR XOR XOR

c8 s7 s s s s s s s
6 5 4 3 2 1 0

Figure 2.19: 8-bit prefix adder with maximum fanout of three and five levels. (Modules to obtain p i , gi , and ai signals not shown.)

Digital Arithmetic - Ercegovac/Lang 2003 2 – Fast Two-Operand Adders

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( gL , aL ) ( gR, aR ) ( gL , aL ) gR
2 2 2

2 g out = g L + a L g R g out = g L + a L g R
( g out , a out ) a out = a L a R

(g7,a7 ) (g1,a1 ) (g0,a0 )

c0
buffer
g(7,6) g(6,5) g(5,4) g(4,3) g(3,2) g(2,1) g(1,0) g(0,-1)
a(7,6) a(6,5) a(5,4) a(4,3) a(3,2) a (2,1) a(1,0)

g(7,4) g(6,3) g(5,2) g(4,1) g(3,0) g(2,-1) g(1,-1)

*

g(7,0)
* c7 c c c4 c c c1
6 5 3 2
p p6 p p p p2 p1 p0
7 5 4 3
XOR XOR XOR XOR XOR XOR XOR XOR
g(7,-1)

c8 s7 s6 s s s s2 s1 s0
5 4 3

* a(j,k) not labeled

Figure 2.20: 8-bit prefix adder with minimum number of levels and fanout of two.(Modules to obtain p i , gi , and ai signals not shown.)
Digital Arithmetic - Ercegovac/Lang 2003 2 – Fast Two-Operand Adders
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CONDITIONAL ADDER (COND ADDER)

x y
m m COND ADDER y
x
m m
m-BIT 1 m-BIT 0 COND
ADDER ADDER ADDER
m+1 m+1 m+1 m+1

(c1m , S1) (c0m , S0)

(c1m , S1) (c0m , S0)

Two adders use shared circuits (b)

(a)

Figure 2.21: (a) Obtaining conditional outputs. (b) Combined conditi onal adder.

Digital Arithmetic - Ercegovac/Lang 2003 2 – Fast Two-Operand Adders

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CARRY-SELECT ADDER

(k-1) (k-1) (i) (i) (1) (1) (0) (0)

x y x y x y x y
k=n/m
m m m m m m m m
COND- COND- COND- m-BIT
ADDER ADDER ADDER ADDER c0
m+1 m+1 m+1 m+1 m+1 m+1 m

MUX MUX MUX

m+1 m+1 m+1

cn

(k-1) (i) (1) (0)

s s s s
Figure 2.22: Carry-select adder.

Digital Arithmetic - Ercegovac/Lang 2003 2 – Fast Two-Operand Adders

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CONDITIONAL-SUM ADDER

XL YL XR YR

n/2 n/2 n/2 n/2

COND-ADDER COND-ADDER

n/2+1 n/2+1 n/2 n/2

(c 1, S 1 ) (c 0, S 0 )
L L L L c1 S1 c0 S0
R R R R

MUX MUX
n/2+1
n/2+1
n/2 n/2
n+1 n+1

(c 1, S 1 ) (c 0, S 0 )

Figure 2.23: Doubling the number of bits of the conditional sum.

Digital Arithmetic - Ercegovac/Lang 2003 2 – Fast Two-Operand Adders

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16-bit CONDITIONAL-SUM ADDER

Y Y 11-8 Y Y 3-0
15-12 7-4
X 15-12 X 11-8 X 7-4 X 3-0

COND- COND- COND-

c
ADDER ADDER ADDER ADDER 0
5 5 5 5 5 5 5

MUX MUX MUX

c
4

c
8
MUX

9 4 4
c
16

s 15-8 s 7-4 s 3-0

Figure 2.24: 16-bit conditional-sum adder (m = 4).

Digital Arithmetic - Ercegovac/Lang 2003 2 – Fast Two-Operand Adders

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TEMPLATE

s03 s02 s01 s00

c04 c02
Step 2
s13 s12 s11 s10
c14 c12
s03 s02 s01 s00
c04
Step 3
s13 s12 s11 s10
c14
Figure 2.25: Conditional-sum addition for eight bits with m = 1: (a) Template. (b) E xample.

Digital Arithmetic - Ercegovac/Lang 2003 2 – Fast Two-Operand Adders

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7 6 5 4 3 2 1 0
x 0 1 0 1 1 0 1 1 c0 = 0
y 0 1 0 1 0 1 0 1
s0 0 0 0 0 1 1 1 0
c0 0 1 0 1 0 0 0 1
Step 1
s1 1 1 1 1 0 0 0
c1 0 1 0 1 1 1 1
s0 1 0 1 0 1 1 0 0
c0 0 0 0 1
Step 2
s1 1 1 1 1 0 0
c1 0 0 1
s0 1 0 1 0 0 0 0 0
c0 0 1
Step 3
s1 1 0 1 1
c1 0
s 1 0 1 1 0 0 0 0

Digital Arithmetic - Ercegovac/Lang 2003 2 – Fast Two-Operand Adders

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PIPELINED ADDERS

Increase throughput
y3 x3 y2 x2 y1 x1 y0 x0

c FA FA FA FA c0
4

- latch

s s s s
3 2 1 0

Figure 2.26: Pipelined carry-ripple adder (for group size of 1 and n = 4)

Digital Arithmetic - Ercegovac/Lang 2003 2 – Fast Two-Operand Adders

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VARIABLE-TIME ADDER: Type 1

1 1 1 1 1
cn cn-1 ci c1 c0
STFA STFA STFA STFA
0 0 0 0 0
cn cn-1 ci c1 c0

STFA - full-adder module

with self-timed carry circuit
F

Figure 2.27: Variable-time adder: Type 1.

Two carry signals:

c0i zero carry c1i one carry
with coding:
c0i c1i ci
0 0 not determined (yet)
0 1 1
1 0 0
1 1 does not occur

Digital Arithmetic - Ercegovac/Lang 2003 2 – Fast Two-Operand Adders

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VARIABLE-TIME ADDER: Type 1 cont.

STFA module expressions:

c0i+1 = ki(c0i c1i ) pic0i = kic1i + (pi ki)c0i
c1i+1 = gi(c0i c1i ) pic1i = gic0i (pi gi)c1i
si = pi ⊕ c1i

ki = x0iyi0 , g i = x i yi , pi = xi ⊕ yi
Addition time: based on actual delays, not worst-case
n−1
Tvar−1 = tc,i
X

i=0

Digital Arithmetic - Ercegovac/Lang 2003 2 – Fast Two-Operand Adders

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VARIABLE-TIME ADDER: Type 2

1 1 1 1 1
cn cn-1 ci c1 c0

CSFA CSFA CSFA c0 CSFA

1
c0 c0 c0 c0
n n-1 i 0

CSFA - full-adder module with

carry completion sensing

Figure 2.28: Variable-time adder: Type 2.

Carry chains initiated simultaneously

CSFA module expressions:
c0i+1 = ki pic0i , c1i+1 = gi pic1i

Digital Arithmetic - Ercegovac/Lang 2003 2 – Fast Two-Operand Adders

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Example

X 0 1 1 0 0 0 1 1 1 0 0 1 1 0 1 0
Y 1 0 1 0 1 1 0 0 1 1 1 0 0 1 1 0
+ a a a b c c c c c d d d d d d e Prop.chains

Completion signal:
n−1
F = (c0i c1i )
Y

i=0

Addition time: proportional to log2(n)

Digital Arithmetic - Ercegovac/Lang 2003 2 – Fast Two-Operand Adders

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2’s COMPLEMENT AND 1s’ COMPLEMENT ADDERS

(g7,a7 ) (g6,a6 ) (g5,a5 ) (g4,a4 ) (g3,a3 ) (g2,a2 ) (g1,a1 ) (g0,a0 )

Prefix Network
(Notes: no cin input;
last level consists
of "circle" modules)

g(7,0) g(6,0) g(5,0) g(4,0) g(3,0) g(2,0) g(1,0)

a(6,0) a(5,0) a(4,0) a(3,0) a(2,0) a(1,0)

end-around
carry
c c c c c c c c
7 6 5 4 3 2 1 0

p p6 p p p p2 p p
7 5 4 3 1 0
XOR XOR XOR XOR XOR XOR XOR XOR

s s s s s s s s
7 6 5 4 3 2 1 0

Figure 2.29: Implementing ones’ complement adder with prefix network. (Modules to obtain pi , gi , and ai signals not shown.)

Digital Arithmetic - Ercegovac/Lang 2003 2 – Fast Two-Operand Adders

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ADDERS WITH REDUNDANT DIGIT-SET

X[i] S[i] X[i] S[i]

CPA Redundant Adder

S[i+1] S[i+1]

redundant

cycle time cycle time does not

depends on precision depend on precision

(a) (b)

Figure 2.30: Accumulation with (a) non-redundant, and (b) redundant representation of sum.

Digital Arithmetic - Ercegovac/Lang 2003 2 – Fast Two-Operand Adders

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CARRY-SAVE ADDER

xn-1 yn-1 z n-1 xi+1 yi+1 z i+1 xi yi zi x0 y0 z0

FA FA FA FA cin

vsn-1 vsi+1 vsi vs0

vci+2 vci+1 vc1 vc
vcn= cout 0
(a)
X Y Z
n n n

(b) cout CSA cin

n n

VC VS
(vc0 = cin)

Figure 2.31: Carry-save adder: (a) Bit level. (b) Bit-vector level.

Digital Arithmetic - Ercegovac/Lang 2003 2 – Fast Two-Operand Adders

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EXAMPLE OF CARRY-SAVE OPERATION

X 0 1 1 1 0 1 0 0
Y 0 0 1 1 1 0 1 1
Z 1 0 1 0 1 0 1 0
VS 1 1 1 0 0 1 0 1
(cout, V C) 0 0 1 1 1 0 1 0 1
digit value 0 1 2 2 1 0 2 0 2

Digital Arithmetic - Ercegovac/Lang 2003 2 – Fast Two-Operand Adders

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[4:2] ADDER

xi yi wi zi

FA FA

FA FA FA

vsi+1 vc i+1 vsi vci

Figure 2.32: [4:2] adder.

Digital Arithmetic - Ercegovac/Lang 2003 2 – Fast Two-Operand Adders

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HIGH RADIX CARRY-SAVE REPRESENTATION

XS 1 0 1 1 0 1 1 0 0
XC 1 1 0
Y 0 1 0 0 0 1 1 1 1
VS 0 0 0 1 1 1 0 1 1
(cout,VC) 1 0 1 0

XS:
XC:
Y:

3-bit adder 3-bit adder

VS:

VC:

Figure 2.33: Radix-8 carry-save adder.

Digital Arithmetic - Ercegovac/Lang 2003 2 – Fast Two-Operand Adders

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SIGNED-DIGIT ADDITION

• Uses signed-digit representation (redundant)

n−1
x= xi r i
X

0
with digit set
D = {−a, . . . , −1, 0, 1, . . . , a}
• Limits carry propagation to next position
• Addition algorithm:
Step 1: x + y = w + t
xi + yi = wi + rti+1

Step 2: s = w + t
si = w i + t i
• No carry produced in Step 2

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SD ADDER

X Y
n n

(a)
tn
SDA t0

xn-1 yn-1 xi yi xi-1 yi-1 x0 y0

TW TW TW TW Step 1
tn wn-1 tn-1 ti+1 wi ti wi-1 ti-1 t1 w0 t0

ADD ADD ADD ADD Step 2

sn sn-1 si si-1 s0
(b)

Figure 2.34: Signed-digit addition.

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CASES CONSIDERED

Case A : two SD operands; result SD

Step 1:


(0, xi + yi)






if −a + 1 ≤ xi + yi ≤ a − 1
(ti+1, wi) =  (1, xi + yi − r) if xi + yi ≥ a


 (−1, x + y + r) if xi + yi ≤ −a


i i


- algorithm modified for r = 2

Case B : two conventional operands; result SD
Case C : one conventional, one SD; result SD

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SIGNED-BINARY ADDITION: METHOD 1 (DOUBLE RECODING)

RECODING 1:

xi + yi = 2hi+1 + zi ∈ {−2, −1, 0, 1, 2}

hi ∈ {0, 1}, zi ∈ {−2, −1, 0}
qi = zi + hi ∈ {−2, −1, 0, 1}
RECODING 2:

qi = zi + hi = 2ti+1 + wi ∈ {−2, −1, 0, 1}

ti ∈ {−1, 0}, wi ∈ {0, 1}

THE RESULT: si = wi + ti ∈ {−1, 0, 1}

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METHOD 1 SD ADDER

xi y x i-1 y i-1 x i-2 y i-2

i

HZ HZ HZ
Recoding 1 h z hi z i-1 h
i+1 i i-1

ADD ADD

q q
i i-1

TW TW
Recoding 2
t w ti wi-1 t
i+1 i i-1

ADD ADD

s s
i i-1

Figure 2.35: Double recoding method for signed-bit addition

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SIGNED BINARY ADDITION: METHOD 2 (Using Previous Digit)


0 if (xi, yi) both nonnegative






Pi =  (which implies ti+1 ≥ 0)


 1 otherwise (t
i+1 ≤ 0)




xi + y i Pi−1 ti+1 wi
2 - 1 0
1 0(ti ≥ 0) 1 -1
1 1(ti ≤ 0) 0 1
0 - 0 0
-1 0(ti ≥ 0) 0 -1
-1 1(ti ≤ 0) -1 1
-2 - -1 0

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METHOD 2 SD ADDER

x y x i-1 y i-1 x i-2 y i-2

i i P Pi-2
i-1
P P

TW TW TW

t w ti wi-1 t
i+1 i i-1

ADD ADD

s s
i i-1

Figure 2.36: Signed-bit addition using the information from previous digit

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Example

X 011111011
Y 011010101

P 000010010

W 000101110
T 0110110010

S 110011100

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BIT-LEVEL IMPLEMENTATION OF RADIX-2 ALGORITHMS

• Case C: xi ∈ {0, 1}, yi, si ∈ {−1, 0, 1}

• Code: borrow-save yi = yi+ − yi−, yi+, yi− ∈ {0, 1}, sim. for si
• xi + yi ∈ {−1, 0, 1, 2}: recode to (ti+1, wi), ti+1 ∈ {0, 1}, wi ∈ {−1, 0}

xi + yi+ − yi− = 2ti+1 + wi

xi + yi -1 0 1 2
wi -1 0 -1 0
ti+1 0 0 1 1

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SWITCHING FUNCTIONS FOR ti+1 AND wi

xi yi+ yi− xi + yi ti+1 −wi

0 0 0 0 0 0
0 0 1 -1 0 1
0 1 0 1 1 1
0 1 1 0 0 0
1 0 0 1 1 1
1 0 1 0 0 0
1 1 0 2 1 0
1 1 1 1 1 1

wi = (xi ⊕ yi+ ⊕ (yi−)0)0

ti+1 = xiyi+ xi(yi−)0 yi+(yi−)0

=⇒ implemented using a full-adder and inverters (for variables subtracted)

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xi y+
i
y-
i
xi-1 y+ y-
i-1 i-1

FA FA
t i+1 wi ti wi-1
t i-1

s+ s-i s+
i-1 s-i-1
i
Figure 2.37: Redundant adder: one operand conventional, one operand redundant, result redundant.

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BOTH OPERANDS REDUNDANT

• Apply double recoding

x+
i
x-i y+
i
y-i x+ x- y+ y-
i-1 i-1 i-1 i-1

FA FA
{-2,-1,0}
hi+1 hi hi-1
{0,1}
zi z i-1 {0,1}
vi v i-1

FA FA
t i+1 wi ti wi-1 t i-1
{0,1} {-1,0}

s+
i
s-i s+ s-
i-1 i-1

Figure 2.38: Redundant adder: operands and result redundant

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SUMMARY

Scheme Delay Area

proportional to proportional to
Linear structures:
Carry ripple n n
Carry lookahead (one level) n/m (kmm)(n/m) = kmn
Carry select (one level) n/m
√ (kmm)(n/m) = kmn
Carry skip (one level) n n
Logarithmic structures:
Carry lookahead (max. levels) 2 log m n (kmm)(n/m) = kmn
Prefix logm n ((kmm) logm n)n
Conditional sum log2(n/m) (km + log2(n/m))n
Completion signal (avg. delay) (log 2 n)/m kmm(n/m) = kmn
Redundant const. n

Digital Arithmetic - Ercegovac/Lang 2003 2 – Fast Two-Operand Adders