University of Skikda Electrical engineering department

PS VHDL - FPGA

Practical session 03: Multiplexer in VHDL

- . .Adoui
. . . . . .Hana
..................................
Student - . . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . .. . . . .
names
-..........................................

1. Practical session objectives:

At the end of this session, you will be able to: use the ModelSim interface, write a
VHDL description of a multiplexer, compile and simulate a VHDL description.

2. The multiplexer:

A multiplexer is a circuit that can receive multiple input signals and synthesize a
single output signal by selecting one of the inputs. It will therefore have: a single
output, and a control bus (address) to choose which input will be selected. The
number of inputs N is equal to 2 to the power of the number of the control bus bits.
The logic diagram of a multiplexer is given by the following figure (left 2:1, right 4:1):

A A
Z B Z
B C
D
S0
S1 S0

The truth table of a 2:1 multiplexer is given by:

A B S0 Z
0 0 0 0
0 0 1 0
S0 Z 0 1 0 0
0 A or 0 1 1 1
1 B 1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 1
3. Methodology:

Consider the following VHDL description:

library ieee;
use ieee.std_logic_1164.all;

Dr. A. Ganouche
 use ieee.numeric_std.all;
entity circuit4 is
port( entree : in std_logic_vector (3 downto 0);
adresse : in std_logic_vector (1 downto 0);
s : out std_logic);
end;
architecture rapide of circuit4 is
begin
s <= entree(to_integer(unsigned(adresse)));
end ;

3.1. Give the number of inputs and outputs of the circuit made by the previous
description.

● inputs:
. . . .entree
. . . . . .(A,B,C,D)
. . . . . . . . and
. . . . select
. . . . . . bit
. . .(S0,S1)
. . . . . . .we
. . .have
. . . . .6. inputs(4
. . . . . . . . inputs
. . . . . . and
. . . .2. .select
.. bit)
● outputs: s (1 output). .
3.2. Compile and simulate this program on ModelSim with different inputs.
3.3. Give the truth table.
S1 S0 S
0 0 A

0 1 B
1 0 C
1 1 D

3.4. Give the logic equation produced by the previous program.

. . . S=
. . . S0S1A
. . . . . . .+S0S1B
. . . . . . . +S0S1C
. . . . . . . .+S0SD
........................................

3.5. Delete the line that declares the ‘numeric_std’ library then compile. Explain.

If we delete
. . . . . .‘’numeric_std’’
. . . . . . . . . . . . . .the
. . . program
. . . . . . . . .didn’t
. . . . . work,
. . . . . . because
. . . . . . . . in
. . .the
. . . program
. . . . . . . . .we
. . declar
the type of the adresse ‘’insigned’’ in the output s
3.6. Modify the program to make a 32 to 1 multiplexer.

port ( entree: in std_logic_vector (31 down to 0) ;

....................................................................

3.7. Modify the program to add an active low ‘enable’ input.

Dr. A. Ganouche