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labtask2

The document outlines a laboratory exercise focused on translating C language branching and conditional statements into RISC-V assembly language. It details the types of conditional branching instructions available in RISC-V and explains the implementation of if, if-else, and switch-case statements. Additionally, it provides specific tasks for students to complete, including coding examples and simulating results using RISC-V assembly instructions.

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omarashraf13456
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2 views

labtask2

The document outlines a laboratory exercise focused on translating C language branching and conditional statements into RISC-V assembly language. It details the types of conditional branching instructions available in RISC-V and explains the implementation of if, if-else, and switch-case statements. Additionally, it provides specific tasks for students to complete, including coding examples and simulating results using RISC-V assembly instructions.

Uploaded by

omarashraf13456
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Department of Computer Science

Institute of Business Administration, Karachi

Lab #2: Branching & Conditional


Statements:
From C to RISC-V Assembly

Computer Architecture & Assembly Language


January 23, 2024

Course Instructor ..........................................................Salman Zaffar Lab Instructor


............................................................Mehwish Zafar
Week Performed ................................................................: Week 1 Room
.............................................................................MTL4

1 Introduction
There are two goals for this laboratory work. These are compilation and simulation of the
following C language’s statements into RISC-V assembly

1. Branching

2. Conditional Statements

2 Branching
2.1 Conditional Branching
The RISC-V instruction set has six conditional branch instructions, each of which take two
source registers and a label indicating where to go. beq (branch if equal) branches when the
values in the two source registers are equal. bne (branch if not equal) branches when they are
unequal. blt (branch if less than) branches when the value in the first source register is less
than the value in the second, and bge (branch if greater than or equal to) branches when the

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first is greater than or equal to the second. blt and bge treat the operands as signed numbers,
while bltu and bgeu treat the operands as unsigned.

Figure 1: Conditional Branching using beq

Figure 2: Conditional Branching using bne

2.2 Jump
A program can jump—that is, unconditionally branch using one of three instructions: jump (j),
jump and link (jal), or jump register (jr). j jumps directly to the instruction at the specified
label.

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Figure 3: Unconditional Branching using jump

3 Conditional Statement
If, if/else, and switch/case statements are conditional statements commonly used in highlevel
languages. They each conditionally execute a block of code consisting of one or more
statements.

3.1 If Statement
An if statement executes a block of code, the if block, only when a condition is met.

Figure 4: If Statement

3.2 If-Else Statement


If-else statements execute one of two blocks of code, depending on a condition. When the
condition in the if statement is met, the if block is executed. Otherwise, the else block is
executed.

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Figure 5: If-Else Statement

3.3 Switch-Case Statements


Switch-Case statements also called simple case statements, execute one of several blocks of
code, depending on the conditions. If no conditions are met, the default block is executed. A
case statement is equivalent to a series of nested If-Else statements.

Figure 6: Switch-Case Statements

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4 Laboratory Tasks
Note: Submit your lab tasks in hard copy that inlcudes (Pg-5 to Pg-10) 1. Implement

codes in examples 6.15 and 6.16 with beq instruction in place of bne.

(a) Implement 6.15 instruction using beq instruction.

Simulate the results after RUN:


Registers Value

s0 (x8) 0x00000007

s1 (x9) 0x0000000a

s2 (x18) 0x0000000b

s3 (x19) 0x00000008

s4 (x20) 0x00000003

(b) Implement 6.16 instruction using beq instruction.

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Simulate the results after RUN:
Registers Value

s0 (x8) 0x0000000a

s1 (x9) 0x00000012

s2 (x18) 0x00000002

s3 (x19) 0x00000008

s4 (x20) 0x00000003

2. Implement the High-Level Code in example 6.17 using If-Else statement and write its
corresponding RISC-V Assembly Code using following instructions

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###################### 6.17
(Sample Code)
######################

.data
button: .word 1 amt: .word

.text
lw s0, button # Load value at memory location ’button’ into s0 lw s1, amt # Load value at
memory location ’amt’ into s1

case1:
addi t0, zero, 1 bne s0, t0,
case2 addi s1, zero, 20 j
done

case2:
addi t0, zero, 2 bne s0, t0,
case3 addi s1, zero, 50 j
done

case3:
addi t0, zero, 3 bne s0, t0,
default addi s1, zero, 100 j
done

default: add s1, zero, zero

done:
(a) High-Level Code

intbutton=1;
intamt;

(b) RISC-V Assembly Code


• beq (branch if equal)

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Simulate the results after RUN:
Registers Value

t0 (x5) 0x00000001

t1 (x6) 0x00000001

t2 (x7) 0x00000000

t3 (x28) 0x00000000

t4 (x29) 0x00000014

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t5 (x30) 0x00000000

• bne (branch if not equal)

Simulate the results after RUN:


Registers Value

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t0 (x5) 0x00000002

t1 (x6) 0x00000001

t2 (x7) 0x00000002

t3 (x28) 0x00000000

t4 (x29) 0x00000032

t5 (x30) 0x00000000

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Figure 7: RISC-V Base ISA

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Figure 8: Complete Single-Cycle RISC-V Microarchitecture

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