FPGA-Supported HDL Approach to Implement

2023 11th International Conference on Internet of Everything, Microwave Engineering, Communication and Networks (IEMECON) | 978-1-6654-7512-9/23/$31.00 ©2023 IEEE | DOI: 10.1109/IEMECON56962.2023.10092307

Reversible Logic Gate-Based ALU

Piyali Saha Souvik Saha
Soumya Sen
Dept. of Electronics & Communication Dept. of Electronics & Communication
Dept. of Electronics & Communication
Engineering Engineering
Engineering
Maulana Abul Kalam Azad University University of Engineering &
Dr. B. R. Ambedkar National Institute
of Technology Management
ofTechnology
West Bengal, India Jaipur, India
Jalandhar, India
[email protected] [email protected]
[email protected]

Abstract— This manuscript banks on the design of produces three different outputs: smaller, more robust, and
reversible gates and implementation of an Arithmetic comparable to devices used in analog-based applications.
Logic Unit – 16 bit (ALU) utilizing Verilog with Xilinx
Although there might be uses for reversible computing in
ISE 14.7, Spartan 6 FPGA kit. The same functionality is transaction processing and computer security, its primary
compared with a basic logic gate-based ALU. Reversible long-term advantages will be realized in fields that desire
gates can produce a distinct output vector from each input high levels of energy effectiveness and significant
vector, and the opposite is also possible. Circuits with performance with speed [3,4].
irreversible gates suffer from data erosion. Power loss
results from a circuit's loss of data. In conclusion, gates
II. GATES WITH REVERSIBLE LOGIC OVER
with reversible logic are preferable over irreversible
IRREVERSIBLE COUNTERPARTS
counterparts. A library of reversible gates, comprising of
AND, OR, NAND, NOR, and XOR, using Verification Researchers have recently looked into several reversible
Logic Hardware Description Language (HDL) is logic gates and all solutions. Process enhancements
developed, which in turn contributes to the designing of ultimately come to an end. Energy use will grow
arithmetic and combinational logic like full adder, decoder unaffordable. Problems with heat dispersion will worsen. A
(2:4), decoder (3:8), multiplier, full subtractor, and traditional computer uses a lot of electricity—electron
comparator. processes in bulk. To perform a single logical process,
several electrons were employed.
Keywords—Verilog, Xilinx ISE, Toffoli Gates, FPGA
Spartan 6. III. METHODOLOGICAL ANALYSIS
With FPGA Spartan 6 and XILINX ISE version 14.7,
I. INTRODUCTION applications like complete adders and multiplexers are
implemented. A piece of software developed by Xilinx for
Modern computers squander a lot of power and storage the synthesis and evaluation of HDL designs is called Xilinx
space. Every instant, they discard millions of bits. These are ISE. The developer can use this tool to synthesize their
built on irreversible logic units, which have been designs, run time analyses, look at RTL diagrams, design
acknowledged for a significant period to be essentially responses to various stimuli, and work with the coder to
wasteful energy-wise. The optimum solutions are hence establish the intended device. A hardware kit called Spartan
reversible gates. Losses are kept to a minimum in circuits 6 FGPA is utilized to put developer designs into practice.
with reversible gates. The number of inputs and outputs in Utilizing VHDL and Verilog HDL, this kit is simple to use
these circuits will be identical, and the vectors of inputs and and can implement any complicated circuit [5].
outputs will be mapped one to one [1]. Examples of such
gates are Fredkin, Toffoli, Interaction, and Switch. Steps to follow in descending order:-
A full adder is a digital arithmetic logic circuitry that
1) A folder is created in a particular drive, and then the
accumulates n input bits along with a carry. Adder circuits
are included in a wide range of processing devices, not same is located as we enter the XILINX suite.
simply ALU-related tasks, to calculate various increment or 2) The new project will have a Spartan 6 with XC6SLX4
decrement calculations, addresses, and others. A device and TQG144 as the device and package and the language
designated as a multiplexer has numerous inputs but just one selected as Verilog.
output. After selecting one from the many analog and digital 3) The appropriate HDL code is written and simulated as
inputs, the detected inputs are then forwarded a single line behavioral in the new module.
[2]. A combinational logic circuit such as a binary decoder 4) Synthesis is done by forcing the inputs, henceforth
translates binary data from n number of inputs to a maximum generating the program file.
of 2n distinct outputs. In analogue decoders, the decoders are 5) The latter is configured, and the outputs are checked
utilized in the analog-to-digital transformation process. on the FPGA kit.
A full subtractor deducts n input bits while taking borrow
into account. They are employed in digital electronics IV. HDL SIMULATED REVERSIBLE LOGIC GATES
applications and calculations involving mathematical
operations. A combinational circuit identified as The reversible Toffoli logic generates the library, which
"Comparator-Comparator" analyzes n input bits and includes the Toffoli-based basic and universal gates.

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 According to elementary physics, each time a bit of data is
obliterated, energy should therefore be lost in a proportion
equal to kT ln 2 per bit purged, where k is the Boltzmann
constant and T is the absolute temperature (in Kelvin).
Because data erasure causes inevitable energy losses,
although all other energy loss techniques were removed from
any NAND-based circuit, the circuit would still lose energy
when it was in operation. The energy expenditures caused by (a)
logical irreversibility in NAND-based logic circuits
nowadays are eclipsed by other loss sources. The energy
losses caused only by information wiping, resulting from
employing irreversible logic gates, will eventually become
the main contributor as these other loss causes are subdued.
The difficulties of extracting this undesirable surplus heat
from deep inside the irreversible circuitry will now prevent
further downsizing of technology nodes if nothing is
(b)
considered today.
Execution of Libraries for the different logics: Toffoli-
based Basic (AND, OR), Universal Gates (NAND, NOR ),
and CNOT. The inputs are considered as A, B, and C for
every case [6-8]. Considering the library for all the gates
implemented by the Toffoli gates, also known as the
Controlled Controlled NOT gate (CCNOT), which is both
reversible and universal, as shown in Fig. 1(a). Reversibility
leads to no data loss, which finally contributes to no loss of (c)
power. Here the TRUE values of A and B will lead to the
flipping of C. Since A and B are still present and can be used
to reassemble C, this gate is reversible. Furthermore, since
we can convert this gate into a NAND gate, it is universal, as
depicted in Fig. 1(b). In building every plausible circuit, one
NAND is sufficient. But even with just one Toffoli gate, we
can effectively construct NOT, AND, and XOR. The NOT
specific case of NAND should be
acknowledged.Fig.1(c),(d),(e) shows the Toffoli NOT,
(d)
Toffoli AND, and Toffoli XOR, and Fig. 2(a), (b), (c), (d),
(e), and (f) displays the waveform simulated in Xilinx ISE
14.7 and further synthesized in FPGA Spartan 6.

(e)

(a) (b)

(f)
(c) (d) Fig.2. Simulated Waveforms for (a) Toffoli AND; (b)
CNOT; (c) Toffoli OR; (d) Toffoli NAND; (e) Toffoli
NOR; (f) Toffoli XOR

Contributions in the Digital circuits, both arithmetic and

(e) combinational, have been illustrated in the simulated
Fig. 1.(a) Toffoli Gate; (b) Toffoli NAND; (c) Toffoli NOT;
XILINX ISE 14.7 waveforms in Fig. 3.
(d) Toffoli AND; (e) Toffoli XOR.

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 Therefore, the study of graphs and GNR used as connections
could be a further study of this research.

V. REVESIBLE GATE BASED 16-BIT ALU

A highly engineered arithmetic circuitry with the fewest

clock cycles feasible that can execute basic arithmetic tasks
as well as the square, square root, and inverse. In this
research, the ALU was designed with superior productivity
(a)
and trial ability in mind. For the development of an elevated
arithmetic unit, layouts with a significant level of
concurrency were investigated. Operational entities were
created with an 8-bit capability for convenience. Increased
operand capacity might necessitate hardware duplication in
parallel with current circuitry owing to architectural
symmetry. The ALU features an isolated gear that can
compute square, square root, and inverted in addition to
executing fundamental integer arithmetic tasks. Using logic
(b) cells from the integrated cell catalog, an 8-bit logic unit was
constructed, and it was discovered that it operated at a peak
frequency of almost 1GHz. A unified ADD or SUB unit was
used to build for addition and subtraction operations. A
number's 2's complement is created by erasing the operand
and then incrementing by 1. If the Control (CTRL) signal is
"Strong," the XOR gate flips the second input. Cin receives
the control command to execute the necessary adjustment for
the two's complement computation.

(c)

(d)

Fig.4. Architecture for Arithmetic Logical Unit, based on Irreversible gates

(e)
Fig.4. shows the logic diagram for a regular
Fig.3. Simulated Waveforms for (a) 2:4 Decoder; (b) 3:8 Decoder; (c) irreversible gate-based ALU capable of performing about
Full Adder; (d) Multiplexer; (e) Full Subtractor 16 instructions, such as the comparison as well as the basic
gate-related operations, i.e.:- AND, OR, NOT, and the
Scientists have recently looked into various reversible
universal gate based such as the NAND, NOR. We
nature logic gates and associated equivalents. Our solution
utilize 3*3 Toffoli gates in a 3×3 matrix. NOT
has the benefits of being deployed at the gate level and
gates cascade the reversible and function generator
having basic, straightforward logic that is simple to build.
and controlled unit to create the bidirectional Arithmetic
The circuits are created with the fewest possible gates. While
Logical Unit with the lowest possible expense, depicted in
we implemented using 2-3 (least) no of gates, such as 1 TR
Fig.5.. Additionally, cascading can be employed to
gate, 1 Feynman, and 1 BJN gate, the current comparator
construct the ALU units that can reverse any number of
designs utilize more no. of gates, including 8 to 9 TR gates in
bits, as shown in Fig.5. The ALU, in reversible mode
comparison. As indicated in the reference, full subtractors
undertake activities in the range of A7 to A0 and B7 to B0
and adders are created using nine gates, making the design
for A and B respectively.
challenging for simulation and coding. Three gates have
been simplified and integrated into our unique ways.

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 the same is "High." "Cin" and "Cout" denote the carry-in and
borrow-out, respectively, for the proposed circuit

Fig.7. Waveform for ALU based on the reversible gate.

Fig.5. Reversible gate based ALU of 16 bits

Table 1: Power and Delay contrast
The consequence of the first and the second inputs of the
control unit of reversible type, DXOR(0-7) are equal to the Method for Power (ns) Delay (mW)
value of the function generator, FUNC(0 -7) outcome Xi and ALU Design
Yi. The value of the third input control, Ci of reversible
controlled unit DXOR(0-7) has some connection with the Using 2.301 0.320
control signal, namely M. Irreversible
Gates
A. ALU using irreversible gates
Using 1.801 0.247
Considering 0 and 1 as inputs for M and Cin , the value is Reversible
obtained in the output as F and Cout, and figure 6 shows the Gates
output waveform for basic logic gate-based irreversible
ALU.
VI. RESULT AND DISCUSSION

Among the low-power techniques, Toffoli logic gates are

utilized to lower the power consumption compared to logic
gates of irreversible nature. The implementation of an ALU
relying on reversible circuitry minimizes the power
utilization during computations to around 7.3%, as indicated
in Table 1. At the same time, an ALU developed employing
non-reversible logic gates consumes additional power of
about 0.320 mW.

VII. CONCLUSION

In this research, we suggest adopting reversible logic

gates rather than conventional gates to design and
synthesize a 16-bit reversible ALU. Reversibility
Fig.6. Waveform for ALU based on the irreversible gate
significantly lowers data bit usage and degradation,
resulting in optimal power consumption. With the help of
Xilinx ISE 14.7, diverse modules' efficiency is examined.
B. ALU using irreversible gates Reversible logic-based circuit designs displayed decreased
power and latency. The topic of study has been logical
The output waveform layout of a 16-bit irreversible adder reversibility, or the ability of inputs and outputs to be
and subtractor is illustrated in Fig. 7. The inputs as A and B separately retrieved from one another.
for the module and M as a control indicator in the 16-bit
data. The addition process is carried out whenever the
control input is "Low" and the subtraction operation when

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