Unit 1 MCQ
Unit 1 MCQ
interfaces?
A. Microcontroller
B. Microprocessor
C. Embedded system
D. Memory system
ANSWER: A
Which of the following offers external chips for memory and peripheral interface
circuits?
A. Microcontroller
B. Microprocessor
C. Embedded system
D. Peripheral system
ANSWER: B
How embedded systems communicate with the outside world?
A. Peripherals
B. Memory
C. Input
D. Output
ANSWER: A
The initial routine is often referred to as
A. Initial program
B. Bootstrap program
C. Final program
D. Initial Embedded Program
ANSWER: B
How the input terminals are associated with external environments?
A. Actuators
B. Sensors
C. Inputs
D. Outputs
ANSWER: B
Which interrupts are generated by the on-chip peripherals?
A. Internal
B. External
C. Software
D. Hardware
ANSWER: A
Which of the following is the common method for connecting the peripheral to the
processor?
A. Internal Interrupts
B. External Interrupts
C. Software
D. Exception
ANSWER: B
ARM stands for __________
A. Advanced Rate Machines
B. Advanced RISC Machines
C. Artificial Running Machines
D. Aviary Running Machines
ANSWER: B
The main importance of ARM micro-processors is providing operation with ______
A. Low cost and low power consumption
B. Higher degree of multi-tasking
C. Lower error or glitches
D. Efficient memory management
ANSWER: A
The ARM processors don�t support Byte addressability.
A. True
B. False
ANSWER: B
The address system supported by ARM systems is/are ___________
A. Little Endian
B. Big Endian
C. X- Little Endian
D. Both A & B
ANSWER: D
In the ARM, PC is implemented using __________
A. Caches
B. Heaps
C. General purpose register
D. Stack
ANSWER: C
Each instruction in ARM machines is encoded into __________ Word.
A. 2 Byte
B. 3 Byte
C. 4 Byte
D. 8 Byte
ANSWER: C
Which can activate the ISR?
A. Interrupt
B. Function
C. Procedure
D. Structure
ANSWER: A
Which factor depends on the number of times of polling the port while executing the
task?
A. Data
B. Data Transfer rate
C. Data Size
D. Number of bits
ANSWER: B
The time taken to respond to an interrupt is known as
A. Interrupt delay
B. Interrupt Time
C. Interrupt Latency
D. Interrupt Function
ANSWER: C
The Instruction, LDM R10!, {R0,R1,R6,R7} ______
A. Loads the contents of R10 into R1, R0, R6 and R7
B. Creates a copy of the contents of R10 in the other registers except for the
above mentioned ones
C. Loads the contents of the registers R1, R0, R6 and R7 to R10
D. Writes the contents of R10 into the above mentioned registers and clears R10
ANSWER: A
The instruction, MLA R0,R1,R2,R3 performs ________
A. R0<-[R1]+[R2]+[R3]
B. R3<-[R0]+[R1]+[R2]
C. R0<-[R1]*[R2]+[R3]
D. R3<-[R0]*[R1]+[R2]
ANSWER: D
Opcode indicates the operations to be performed.
A. True
B. False
ANSWER: A
Which of the following is not a visible register?
A. General Purpose Register
B. Status Register
C. Address Register
D. Memory Address Register
ANSWER: D
Which of the following is a data transfer instruction?
A. STA 16-bit address
B. ADD A, B
C. MUL C, D
D. RET
ANSWER: A
What kind of a flag is the sign flag?
A. General Purpose
B. Status
C. Address
D. Instruction
ANSWER: B
In memory-mapped I/O _________
A. The I/O devices and the memory share the same address space
B. The I/O devices have a separate address space
C. The memory and I/O devices have an associated address space
D.A part of the memory is specifically set aside for the I/O operation
ANSWER: A
The advantage of I/O mapped devices to memory mapped is ___________
A. The former offers faster transfer of data
B. The devices connected using I/O mapping has a bigger buffer space
C. The devices have to deal with fewer address lines
D. No advantage as such
ANSWER: C
The process wherein the processor constantly checks the status flags is called as
___________
A. Polling
B. Inspection
C. Reviewing
D. Echoing
ANSWER: A
The method which offers higher speeds of I/O transfers is _________
A. Interrupts
B. Memory Mapping
C. Program Controlled I/O
D. DMA
ANSWER: D