COA Lecture

10
Pipelining Design Techniques
 Introduction
• There are two basic techniques to increase the
instruction execution rate of a processor.
– increase the clock rate, thus decreasing the
instruction execution time
– increase the number of instructions that can be
executed simultaneously
• Pipelining is an example of the latter
technique.
• Pipelining owes its origin to car assembly lines.
• The idea is to have more than one instruction
being processed by the processor at the same
time.
• Similar a car assembly line, the success of a
pipeline depends upon dividing the execution of
an instruction among a number of subunits
(stages), each performing part of the required
operations.
• A possible division is to consider instruction
fetch (F), instruction decode (D), operand
fetch (F), instruction execution (E), and store
of results (S) as the subtasks needed for the
execution of an instruction.
• Pipelining refers to the technique in which a given
task is divided into a number of subtasks that
need to be performed in sequence.
• Each subtask is performed by a given functional
unit. The units are connected in a serial fashion
and all of them operate simultaneously.
• The use of pipelining improves the performance
compared to the traditional sequential execution
of tasks.
Pipelining versus sequential processing
Pipelining vs. sequential processing
• It is clear from the figure that the total time
required to process three instructions (I1, I2, I3)
is only six time units if four-stage pipelining is
used as compared to 12 time units if
sequential processing is used.
• A possible saving of up to 50% in the
execution time of these three instructions is
obtained.
 Performance Benefits
• Speed-up of instruction execution
• Throughput increase
• Efficiency
 Pipeline Hazards
• A pipeline hazard occurs when the pipeline,
or some portion of the pipeline, must stall
because conditions do not permit continued
execution.
• Such a pipeline stall is also referred to as a
pipeline bubble.
• There are three types of hazards: resource,
data, and control.
 Resource Hazards
• A resource hazard occurs when two (or more)
instructions that are already in the pipeline
need the same resource.
• The result is that the instructions must be
executed in serial rather than parallel for a
portion of the pipeline.
• A resource hazard is sometime referred to as a
structural hazard.
• Let us consider a simple example of a resource
hazard.
• Assume a simplified five stage pipeline, in
which each stage takes one clock cycle.
Example of Resource Hazard
• The figure above shows the ideal case, in which a new
instruction enters the pipeline each clock cycle. Now
assume that main memory has a single port and that all
instruction fetches and data reads and writes must be
performed one at a time.
• Further, ignore the cache. In this case, an operand read to
or write from memory cannot be performed in parallel with
an instruction fetch.
• This is illustrated in the second diagram, which assumes
that the source operand for instruction I1 is in memory,
rather than a register. Therefore, the fetch instruction stage
of the pipeline must idle for one cycle before beginning the
instruction fetch for instruction I3.
• The figure assumes that all other operands are
in registers. Another example of a resource
conflict is a situation in which multiple
instructions are ready to enter the execute
instruction phase and there is a single ALU.
• One solutions to such resource hazards is to
increase available resources, such as having
multiple ports into main memory and multiple
ALU units.
 Data Hazards
• A data hazard occurs when there is a conflict in the access
of an operand location. In general terms, we can state the
hazard in this form:
• Two instructions in a program are to be executed in
sequence and both access a particular memory or register
operand. If the two instructions are executed in strict
sequence, no problem occurs.
• However, if the instructions are executed in a pipeline, then
it is possible for the operand value to be updated in such a
way as to produce a different result than would occur with
strict sequential execution.
• In other words, the program produces an incorrect result
because of the use of pipelining.
• As an example, consider the following x86 machine instruction sequence:
ADD EAX, EBX /* EAX = EAX + EBX
SUB ECX, EAX /* ECX = ECX – EAX

• The first instruction adds the contents of the 32-bit registers EAX and EBX
and stores the result in EAX. The second instruction subtracts the contents
of EAX from ECX and stores the result in ECX. Figure 12.16 shows the
pipeline behaviour.
• The ADD instruction does not update register EAX until the end of stage 5,
which occurs at clock cycle 5. But the SUB instruction needs that value at
the beginning of its stage 2, which occurs at clock cycle 4.
• To maintain correct operation, the pipeline must stall for two clocks cycles.
Thus, in the absence of special hardware and specific avoidance
algorithms, such a data hazard results in inefficient pipeline usage.
Example of Data Hazard
• Find out the solution for data hazards
 Control Hazards
• A control hazard, also known as a branch
hazard, occurs when the pipeline makes the
wrong decision on a branch prediction and
therefore brings instructions into the pipeline
that must subsequently be discarded.
 Dealing with Branches

• One of the major problems in designing an instruction