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Jatin CourseProject Report

The project involves designing a cascode amplifier and cascode current mirror using LT Spice and Magic tools for both 180 nm and 22 nm technology nodes. The results indicate that the desired gain was achieved in both technologies, with specific bias voltages and output voltage swings reported. The layout was successfully designed and extracted for simulation purposes.

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jatingoyal9814851164
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3 views13 pages

Jatin CourseProject Report

The project involves designing a cascode amplifier and cascode current mirror using LT Spice and Magic tools for both 180 nm and 22 nm technology nodes. The results indicate that the desired gain was achieved in both technologies, with specific bias voltages and output voltage swings reported. The layout was successfully designed and extracted for simulation purposes.

Uploaded by

jatingoyal9814851164
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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EE 301 - ANALOG CIRCUITS

Course Project
Submitted By - Jatin Goyal
2021EEB1180

OBJECTIVE
Design of cascode amplifier and cascode current mirror in schematic and layout using LT Spice and
Magic tools in 180 nm (supply 1.8 V) technology and only schematic
of cascode amplifier, beta multiplier and cascode current mirror in 22 nm (supply 0.8 V) technology
node to see the effect of lowering the technology node.

180nm Technology

Beta Multiplier for 180 nm technology

Cascode Amplifier Implementation biased through current mirror

1
CRCUT foR CASCODE AMPUFIER FoR l&o nM 1ECHNOLbGY
Gfven Vpp |.8V
Ven for NMOs 0.366 V
tor PMOS -0.2406 V

Vbjal
Shold
the
onpifer
Saturafon regio
135V
Vbia Vop hond be Aivided nto
|6 4v Moufete
Vbia3 loneeted Series.

Vin Vetage eaeh


Vop

Condi tforn
for Mesfet to openate
Sat uatfon rogion
Vos (Mos)
(PMos)
For Mi, CNMOS)
Vbg Vgs - UH
Vgs - . 346

Vivn -o - 0-3L

for H,(NNos)
D.9 - b.4s 7
(Vbias3 -b.46) - b.3GG

1.266
For Hg CPMOS)

7/ - o.3906
for Me (PMO),

l8 -|.3s) (l3- VSas ) - o.39ob


0.9594 V

|·8 Vaul > o.3966


|t094 V

Stnce Power Dissiption (Po) < 5mW


RESULTS
Bias Voltages:

Vbias1 = 1.025 V (0.9594 < 1.025 < 1.4094 => Satisfies)


Vbias2 = 541.8 mV (0.5094 < 0.5418 < 0.9594 => Satisfies)
Vbias3 = 853.5 mV (0.816 < 0.8535 < 1.266 => Satisfies)
Vin (DC Bias) = 0.6005 V (0.366 < 0.6005 < 0.816 => Satisfies)

Voltage Swing:

2
Output Voltage Swing (326mv - 248mV) = 78mV

Frequency Response:

Gain (at t = 0) = 26.066 dB

3
22nm Technology

Beta Multiplier for 22 nm technology

Cascode Amplifier Implementation biased through current mirror

4
CiRcUr PoR CAS ChDE AMPufER FoR 22nm ECHNDL06Y
qiven:
for MOS
for Pmos - b.46b V

Satunattn region
siiar to
Vbias2 diuided equaly hen as
well So Poteutal

HH 4
26.2V

Lot Vin

Vin > D.502o8

Vin .703uR
For

o,503o&

Vbas

0.4-02 Vsay9 -0.2) o.503b


Vhins - 0.1o3
Vbiay

70308 V Vbias3 e o.9036V


For iN3 (PMos)

6.4666

b.6- Vhia

D(39 4
For Mt lRMOg)

(os -.6) (o.8- Vhiaa)- 0.4bob


Vbiosl 0.|394 V

Vbiasl) 0.460b

Vhiasl - 0.33q 4

< o.3394

0-1394

Pouoer Dfsipatfon
RESULTS
Bias Voltages:

Vbias1 = 282.88 mV (0.1394 < 0.28288 < 0.3394 => Satisfies)


Vbias2 = 75.654 mV (-0.0606< 0.075654 < 0.1394 => Satisfies)
Vbias3 = 708.86 mV (0.70308 < 0.70886 < 0.90308 => Satisfies)
Vin (DC Bias) = 0.6 V (0.50308 < 0.6 < 0.70308 => Satisfies)

Voltage Swing:

5
Output Voltage Swing (650mv - 159mV) = 491mV

Frequency Response:

Gain (at t = 0) = 26.024 dB

6
MAGIC LAYOUT OF CASCODE AMPLIFIER

CONCLUSION
We can conclude from the project that the desired gain was obtained for both 180nm and 22 nm
technology files under the provided constraints for cascaded amplifier biased through current
mirror, simulated in LT Spice. The layout for cascode amplifier was designed in the Magic
according to the design rules and was extracted to .ext file and later as spice file.

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