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P18is35 - Z2

This document outlines the examination structure for the Computer Organization and Architecture course at P.E.S. College of Engineering for the third semester. It includes course outcomes, a breakdown of exam parts, and specific questions categorized by units, covering topics such as program execution, memory systems, and arithmetic operations. The exam consists of compulsory and optional questions, totaling 100 marks.

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7 views2 pages

P18is35 - Z2

This document outlines the examination structure for the Computer Organization and Architecture course at P.E.S. College of Engineering for the third semester. It includes course outcomes, a breakdown of exam parts, and specific questions categorized by units, covering topics such as program execution, memory systems, and arithmetic operations. The exam consists of compulsory and optional questions, totaling 100 marks.

Uploaded by

mp4248728
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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P18IS35 Page No...

1
U.S.N

P.E.S. College of Engineering, Mandya - 571 401


(An Autonomous Institution affiliated to VTU, Belagavi)
Third Semester, B.E. - Information Science and Engineering
Semester End Examination; March / April - 2022
Computer Organization and Architecture
Time: 3 hrs Max. Marks: 100
Course Outcomes
The Students will be able to:
CO1: Analyze program execution.
CO2: Explain the basic input/output operations.
CO3: Develop the control sequence for a given instruction.
CO4: Design the memory system using various techniques.
CO5: Analyze different algorithms for performing arithmetic operations and understand need for multithread.
Note: I) PART - A is compulsory. Two marks for each question.
II) PART - B: Answer any Two sub questions (from a, b, c) for Maximum of 18 marks from each unit.
Q. No. Questions Marks BLs COs
I : PART - A 10
I a. Write basic performance equation and explain each term. 2 L2 CO1
b. List operations performed by call and branch instructions. 2 L1 CO2
c. Write actions required to perform read operation for the instruction,
2 L2 CO3
MOV (R1), R2
d. Differentiate SRAM and DRAM. 2 L2 CO4
e. Write Amdahl’s law equation. 2 L2 CO5
II : PART - B 90
UNIT - I 18
1 a. Explain connection between processor and memory which is established
9 L2 CO1
during instruction execution.
b. With an example, list and explain basic instruction types. 9 L2 CO1
c. Explain different types of addressing modes. 9 L2 CO1
UNIT - II 18
2 a. Explain Basic push, pop operation, push and pop using auto increment
and auto decrement, Routine used for safe push and safe pop operation 9 L2 CO2
with respect to stack.
b. What are interrupts? Discuss different approaches used by the processor
9 L2 CO2
to handle simultaneous requests.
c. Discuss input and output operation of asynchronous bus. 9 L2 CO2
UNIT - III 18
3 a. Explain Multi bus organization of a processor. 9 L2 CO3
b. Write a control sequence for ADD (R3), R1 and unconditional branch
9 L3 CO3
instruction.
c. Discuss concept of fetching a word from a memory. 9 L2 CO3
Contd... 2
P18IS35 Page No... 2
UNIT - IV 18
4 a. Explain direct and associative cache mapping. 9 L2 CO4
b. Explain static RAM cell and CMOS memory cell. 9 L2 CO4
c. Explain with neat representation the memory hierarchy based on speed,
9 L2 CO4
size and cost.
UNIT - V 18
5 a. Perform sequential multiplication of M = 1101 and Q = 1011 and also
9 L3 CO5
write circuit for binary multiplier.
b. Explain Flynn’s taxonomy. 9 L2 CO5
c. Discuss multi threading on single-core versus multi-core platform. 9 L2 CO5

***

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