Instruction Codes

Instruction Codes

Program
set of instructions to specify the operations, operands and
the sequence by which processing has to occur.

Computer Instruction
• A binary code specifies a sequence of micro-operations for the
computer.
• Computer reads each instruction from memory and places it in a
control register.
• Then the control interprets the binary code of the instruction and
proceeds to execute it by issuing a sequence of micro-operations.
 Instruction Codes

Instruction Code
• Group of bits that instruct the computer to perform a specific operation.
• Example Unique Binary code
is assigned to every
ADD 457 OpCode

Operation Code (Opcode)

• Group of bits that define operations: add, sub, mul, shift, and complement.
• Number of bits required for the opcode depends on the total number of
operations available in the computer.
• Opcode must have at least n bits for a given 2n distinct operations.
 Stored Program Organization

▪ Computer : 1 processor register (AC) & an instruction code format with

two parts.
Part 1 : Operation (opcode) Part 2 :specifies an address (operand).

▪ Memory address tells the control where to find an operand in

memory.
▪ Operand is read from memory & used as the data to be operated on
together with the data stored in the processor register.

▪ Instructions are stored in a section of the memory and data in another.

▪ Memory unit with 4096 words => 12 bits to specify the address[212]
Stored Program Organization
Memory
4096 x 16

15 12 11 0
Opcode Address
Instructions
(program)
Instruction Format

15 0 Operand
Binary Operand (data)

Processor Register
(accumulator or AC)
 Stored Program Organization Contd..

▪ Each instruction code is stored in one 16-bit memory word,

4 bits for opcode to specify one out of 16 [24] possible operations,
12 bits to specify the address of an operand.

▪ The control reads a 16-bit instruction from the program portion of

memory.
▪ It uses the 12-bit address part of the instruction
to read a 16-bit operand from the data portion of memory.

▪ It then executes the operation specified by the operation code.

Instruction format of basic computer

Instruction Format

15 14 12 11 0
I Opcode Address

0 0 0 1 0 1 0 0 0 1 0 1 0 1 1 1

ADD 4 5 7
 Direct & Indirect Addressing of Memory

▪ Immediate: Second part of an instruction specifies the

operand

▪ Direct: Second part of an instruction specifies the

address of an operand

▪ Indirect address: Second part of the instruction

designate an address of a memory word in which the
address of the operand is found.
Direct & Indirect Addressing of Memory

Memory Memory
22 0 ADD 457 35 1 ADD 300

300 1350

457 Operand
1350 Operand

+ +

AC AC
Computer Registers
11 0
Program Counter(12)
PC Holds address of instruction
11 0
Address Register(12)
AR Holds address for memory
15 0
Instruction Register(16)
IR Holds instruction code
15 0
Temporary Register(16)
TR Holds temporary data
15 0
Data Register(16)
DR Holds memory operand
Computer Registers
15 0
Accumulator(16)
AC Processor Register
7 0
Output Register(8)
OUTR Holds output character
7 0
Input Register(8)
INPR Holds input character

Memory
4096 words
16 bits per word
 S2
S1 Bus

Common Memory S0
4096 x 16 7
Address
Bus Write
AR
Read
1

System of
LD INR CLR
PC 2
LD INR CLR
Basic DR 3
LD INR CLR

Computer Adder
& Logic
E
AC 4
LD INR CLR

INPR

IR 5
LD
TR 6
LD INR CLR
OUTR
Clock
LD
Basic Computer Instruction Formats

19I302 Computer Architecture

Types of Computer Instructions
1. Memory Reference Instruction
15 14 12 11 0
I Opcode Address

01 01 01 01 Address

0xxx 8xxx AND AND the content of memory to AC

1xxx 9xxx ADD Add the content of memory to AC
2xxx Axxx LDA Load memory word to AC
3xxx Bxxx STA Store content of AC in memory
4xxx Cxxx BUN Branch unconditionally
5xxx Dxxx BSA Branch and save return address
6xxx Exxx ISZ Increment and skip if zero
Types of Computer Instructions
2. Register Reference Instruction
15 14 13 12 11 0
0 1 1 1 Register Operation

0 1 1 1 1
0 10 1
0 10 01 10 01 0 0 0 0 0

7800 CLA Clear AC

7400 CLE Clear E
7200 CMA Complement AC
7100 CME Complement E
7080 CIR Circulate right AC and E
7040 CIL Circulate left AC and E
7020 INC Increment AC
Types of Computer Instructions
3. Input – Output Instruction
15 14 13 12 11 0
1 1 1 1 I/O Operation

1 1 1 1 10 01 10 01 1
0 01 0 0 0 0 0 0

F800 INP Input character to AC

F400 OUT Output character from AC
F200 SKI Skip on input flag
F100 SKO Skip on output flag
F080 ION Interrupt on
F040 IOF Interrupt off
Basic Computer Instructions
Instruction Set Completeness
Instruction set is said to be complete if it includes
sufficient number of instructions in each of the
following categories:
1. Arithmetic, logical and shift instructions
2. Instructions for moving information to and from
memory and processor registers
3. Program control instructions together with
instructions that check status conditions
4. Input and output instructions
Timing & Control
 Control Organization
Hardwired Control
• The control logic is implemented with gates, flips-flops,
decoders and other digital circuits.
• It can be optimized to produce a fast mode of operation.
• It requires changes in the wiring among the various components
if the design has to be modified or changed.
Microprogrammed Control
• The control information is stored in a control memory.
• The control memory is programmed to initiate the required
sequence of microoperations.
• Any required changes or modifications can be done by updating
the microprogram in control memory.
19I302 Computer Architecture
Control Unit of Basic Computer
0 0 0 Instruction
1 0 Register
1 0 0 0 1 0 1 0 1 1 1
Other inputs
15 14 13 12 11 - 0
0 0 0 1
3x8
Decoder
7 6 5 4 3 2 1 0 Control
D0 Control O/p
I D1 D7 Logic
Gates
T15
T0
15 14 ... 2 1 0
4 x 16
Decoder

4-bit sequence Increment (INR)

Clear (CLR)
counter (SC) Clock
Control Unit

Components of Control unit :

2 - Decoders
•

A sequence counter
•

Control logic gates

•

▪ Instruction read from memory is placed in the Instruction Register

IR has 3 parts
Op-code in bits 12-14 are decoded with a 3 x 8 decoder.
Bit-15 of the instruction is transferred to a flip-flop designated by
the symbol ‘I’.
 Control Unit
▪ 8 outputs of the decoder => Designated by D0 through D7.
▪ Bits 0 through 11 are applied to the control logic gates.
▪ 4‐bit sequence counter can count in binary from 0 through 15. The
outputs of counter are decoded into 16 timing signals T0 through
T15.
▪ Sequence counter SC can be incremented or cleared
synchronously.
▪ Counter is incremented to provide the sequence of timing signals
out of 4 X 16 decoder.
▪ Counter is cleared to 0, causing the next timing signal to be T0.
 Control Unit Example

Consider a case where SC is incremented to provide timing

signals T0, T1, T2, T3 and T4 in sequence. At time T4, SC is
cleared to 0 , if decoder output D3 is active. This is expressed
symbolically by the statement
D3T4: SC ← 0

Initially, the CLR input of SC is active.

The first positive transition of the clock clears SC to 0, which
activates the timing T0 out of the decoder.
T0 is active during one clock cycle.
Control Unit

The positive clock transition labeled T0 in the diagram

will trigger only those registers whose control inputs
are connected to timing signal T0.
SC is incremented with every positive clock transition,
unless its CLR input is active.
This procedures the sequence of timing signals T0, T1,
T2, T3 and T4, and so on. If SC is not cleared, the timing
signals will continue with T5, T6, up to T15 and back to
T0.
Timing Cycle for D3T4: SC ← 0

Clock

CLR
SC
 Control Unit

• The last 3 waveforms shows how SC is cleared when D3T4 = 1.

• Output D3 from the operation decoder becomes active at the end of T2.
• When T4 becomes active, the output of the AND gate that implements the
control function D3T4 becomes active.
• This signal is applied to the CLR input of SC.
• On the next positive clock transition the counter is cleared to 0.
• This causes the T0 to become active instead of T5 that would have been active if
SC were incremented instead of cleared.
Instruction Cycle

A program residing in the memory unit of the computer consists of a sequence of

instructions. In the basic computer each instruction has the following phases:
1. Fetch an instruction from memory.
2. Decode the instruction.
3. Read the effective address from memory if the instruction has an indirect
address.
4. Execute the instruction.
After step 4, the control goes back to step 1 to fetch, decode and execute the next
instruction.
This process continues unless a HALT instruction is encountered.
 Instruction Cycle

Fetch & Decode

• PC is loaded with the address of the first instruction in the program.
• The micro-operations for fetch and decode phases are as follows:
Register Transfer Fetch Phase
 Start
SC ← 0

AR ← PC

IR ← M[AR], PC ← PC + 1

Decode operation code in IR(12-14)

AR ← IR(0-11), I ← IR(15)

(Register or I/O) = 1 = 0 (Memory-reference)

D7
(I/O) = 1 = 0 (register) (indirect) = 1 = 0 (direct)
I I

Execute
Execute
register- AR ← M[AR] Nothing
input-output
reference
instruction
instruction
SC ← 0
SC ← 0
Execute
memory-reference
instruction
SC ← 0
Interrupt Cycle
Instruction cycle = 0 = 1 Interrupt cycle
R

Fetch & Decode Store return address

instruction in location 0
M[0] ← PC
Execute =0
IEN
instruction
=1 Branch to location 1
PC ← 1
=1 FGI
=0
IEN ← 0
=1 FGO R←0
=0
R←1
Register transfer statements for Interrupt cycle
• Fetch and decode phases of the instruction cycle
must be modified & Replace T0, T1, T2 with R'T0,
R'T1, R'T2
• So the interrupt cycle statements are :
RT0 : AR ← 0, TR ← PC
RT1 : M[AR] ← TR, PC ← 0
RT2 : PC ← PC + 1, IEN ← 0, R ← 0, SC ← 0
 Demonstration of Interrupt Cycle
0 0 256
1 0 BUN 1120 PC = 1 0 BUN 1120

255 255
PC = 256 256
Main Program Main Program

1120 1120
I/O program I/O program

1 BUN 0 1 BUN 0

Before Interrupt After Interrupt

Basic Computer - Components
 Start
SC ← 0, IEN ← 0, R ← 0

(Instruction cycle) = 0 =1 (Interrupt cycle)

R

Design of AR ← PC AR ← 0, TR ← PC

Basic IR ← M[AR], PC ← PC + 1 M[AR] ← TR, PC ← 0

Computer Decode operation code in IR(12-14)

AR ← IR(0-11), I ← IR(15)
PC ← PC + 1, IEN ← 0,
R ← 0, SC ← 0

(Register or I/O) = 1 = 0 (Memory-reference)

D7
(I/O) = 1 = 0 (register) (indirect) = 1 = 0 (direct)
I I

Execute input- Execute AR ← M[AR] Nothing

output register-reference
instruction instruction
SC ← 0 SC ← 0
Execute
memory-reference
instruction
SC ← 0
Instruction Formats
&
Addressing Modes
 Instruction format
Combination of an operation code and someway of
specifying an operand, most commonly by its location
or address in memory
 Instruction Formats
Instruction sets are differentiated by the following:
Number of bits per instruction
Stack-based or register-based
Number of explicit operands per instruction
Operand location
Types of operations
Type and size of operands
ISA are measured by :

Main memory space occupied by a program

Instruction complexity
Instruction length (in bits)
Total number of instruction in the instruction set
 ISA design
Instruction set, consideration is given to:

Instruction length - short, long, or variable

Number of operands
Number of addressable registers
Memory organization – byte / word addressable
Addressing modes - direct, indirect or indexed
 Cont..
• Byte ordering, or endianness, is another major
architectural consideration.
• If we have a two-byte integer, the integer may be stored
so that the least significant byte is followed by the most
significant byte or vice versa.
– In little endian machines, the least significant byte
is followed by the most significant byte.
– Big endian machines store the most significant
byte first (at the lower address).
 Cont..

• As an example, suppose we have the hexadecimal

number 12345678.
• The big endian and small endian arrangements of the
bytes are shown below.

Note: This is the internal storage format, usually invisible to the user
 Cont..
• Big endian:
– Is more natural.
– The sign of the number can be determined by
looking at the byte at address offset 0.
– Strings and integers are stored in the same order.
• Little endian:
– Makes it easier to place values on non-word
boundaries, e.g. odd or even addresses
– Conversion from a 32-bit integer to a 16-bit integer
does not require any arithmetic.
 Standard…What Standard?
• Intel (80x86), VAX are little-endian
• IBM 370, Motorola 680x0 (Mac), and most RISC systems are big-
endian
• Makes it problematic to translate data back and forth between
say a Mac/PC
• Internet is big-endian
– Why? Useful control bits in the Most Significant Byte can be
processed as the data streams in to avoid processing the rest
of the data
– Makes writing Internet programs on PC more awkward!
– Must convert back and forth
 What is an instruction set?
• The complete collection of instructions that are
understood by a CPU
The physical hardware that is controlled by the
instructions is referred to as the Instruction Set
Architecture (ISA)
• The instruction set is ultimately represented in binary
machine code also referred to as object code
–Usually represented by assembly codes to human
programmer
 Elements of an Instruction
• Op code : Do this
• Source Operand reference(s) : To this
• Result Operand reference(s) : Put the answer here
• Next Instruction : do this instruction next
 Where are the operands?

• Main memory
• CPU register
• I/O device
• In an instruction itself

• To specify which register, which memory

location, or which I/O device, we’ll need some
addressing scheme for each
 Stack Organization
Stack - A storage device that stores information in such a
manner that the item stored in last is the first item
retrieved (LIFO).
Register that holds the address for the stack is called a
stack pointer (SP)

2 types of Stack organization

Register Stack – Built using registers
Memory Stack – Logical part of memory allocated as stack
Register Stack
Register Stack
Memory Stack
Memory Stack
Reverse Polish Notation
Cont..
Instruction Formats
 Instruction Set Design
One important design factor is the number of operands contained in
each instruction
– Has impact on the word size and complexity of the CPU
– E.g. lots of operands generally implies longer word size needed for
an instruction

How many operands required for an ADD instruction?

– Contents are two memory locations ; to handle at least two
memory addresses
– Where does the result of the add go? We need a third operand to
specify the destination
– What instruction should be executed next?
• Usually next instruction, sometimes to jump / branch
• To specify the next instruction to execute we need a fourth
operand

• If all of these operands are memory addresses, we need a really long

instruction!
 Instruction Formats
Instructions are categorized into different formats with
respect to the operand field in the instructions.
Three Address Instructions
Two Address Instructions
One Address Instructions
Zero Address Instructions
 Number of Operands
• In practice, we won’t really see a four-address instruction.
– Too much additional complexity in the CPU
– Long instruction word
– All operands won’t be used very frequently

• Most instructions have one, two, or three operand addresses

– The next instruction is obtained by incrementing the program counter,
with the exception of branch instructions

• Let’s describe a hypothetical set of instructions to carry out

the computation for:
Y = (A-B) / (C + (D * E))
 Three operand instruction
In 3 operand instruction, 2 source operands and 1 destination to
store the result either a process register or memory operand

Y = (A-B) / (C + (D * E))

SUB R1, A, B ; Register R1 🡨 A-B

MUL R2, D, E ; Register R2 🡨 D * E
ADD R2, R2, C ; Register R2 🡨 R2 + C
DIV R1, R1, R2 ; Register R1 🡨 R1 / R2
• Convenient, flexibility to dictate where the result of computations
should go.
• After this calculation is done, we haven’t changed the contents of
any of our original locations A,B,C,D, or E.
 Two operand instruction
How to reduce the number of operands? to make the
instruction shorter

Typical method is to assign a default destination operand to

hold the results of the computation

Result always goes into this operand

Overwrites and old data in that location

Let’s say that the default destination is the first operand in the
instruction
First operand might be a register, memory, etc.
 Two Operand Instructions
Y = (A-B) / (C + (D * E))

SUB A, B ; Register A 🡨 A-B

MUL D, E ; Register D 🡨 D*E
ADD D, C ; Register D 🡨 D+C
DIV A, D ; Register A 🡨 A / D

Result obtained as before, but changed the contents of A and D

If we want to use the original contents of those registers, make a copy

of them before performing the computation
–MOV R1, A ; Copy A to register R1
–MOV R2, D ; Copy D to register R2
–SUB R1, B ; Register R1 🡨 R1-B
–MUL R2, E ; Register R2 🡨 R2*E
–ADD R2, C ; Register R2 🡨 R2+C
–DIV R1, R2 ; Register R1 🡨 R1 / R2
A-E remain the same as before, but at the cost of some extra
instructions to save the results.
 One Operand Instructions
• Same idea used to get rid of the second operand, leaving only one
operand

• Second operand is left implicit; e.g. could assume that the second
operand will always be in a register such as the Accumulator:

Y = (A-B) / (C + (D * E))
LDA D ; Load ACC with D
MUL E ; Acc 🡨 Acc * E
ADD C ; Acc 🡨 Acc + C
STO R1 ; Store Acc to R1
LDA A ; Acc 🡨 A
SUB B ; Acc 🡨 A-B
DIV R1 ; Acc 🡨 Acc / R1

• Early computers relied on one-address based instructions, as it

makes the CPU much simpler to design.
 Zero Operand Instructions
• we can also have zero operand instructions

• Uses the Stack

Section of memory where we can add and remove items in LIFO

order
Eg: stack of trays in a cafeteria; the last tray placed on the stack is
the first one someone takes out

Computer stack behaves similarly , but with data values

PUSH A ; Places A on top of stack

POP A ; Removes value on top of stack and puts result in A
ADD ; Pops top two values off stack, pushes result back on
 Stack-Based Instructions
Y = (A-B) / (C + (D * E))

Instruction Stack Contents (top to left)

PUSH B ;B
PUSH A ; B, A
SUB ; (A-B)
PUSH E ; (A-B), E
PUSH D ; (A-B), E, D
MUL ; (A-B), (E*D)
PUSH C ; (A-B), (E*D), C
ADD ; (A-B), (E*D+C)
DIV ; (A-B) / (E*D+C)
 How many operands is best?
• More operands
– More complex (powerful?) instructions
– Fewer instructions per program
• More registers
– Inter-register operations are quicker
• Fewer operands
– Less complex (powerful?) instructions
– More instructions per program
– Faster fetch/execution of instructions
 Design Tradeoff Decisions
Operation repertoire
– How many ops?
– What can they do?
– How complex are they?
Data types
– What types of data should ops perform on?
Registers
– Number of registers, what ops on what registers?
Addressing
– Mode by which an address is specified
 Instruction Formats
• We have seen how instruction length is affected by
the number of operands supported by the ISA.
• In any instruction set, not all instructions require the
same number of operands.
• Operations that require no operands, such as HALT,
necessarily waste some space when fixed-length
instructions are used.
• One way to recover some of this space is to use
expanding opcodes.
 Instruction types
Instructions fall into several broad categories that you should
be familiar with:
• Data movement
• Arithmetic
• Boolean
• Bit manipulation
• I/O
• Control transfer
• Special purpose
 Addressing
• Addressing modes specify where an operand is located.
• Every instruction includes operands; the operands can
be a constant, memory location, a processor register or
an I/O device.
• Effective Address (EA) is the address of the exact
memory location where the value of the operand is
present.
• Certain addressing modes allow us to determine the
address of an operand dynamically.
 Types of Addressing Modes
• Register Addressing Mode
• Direct Addressing Mode
• Immediate Addressing Mode
• Register Indirect Addressing Mode
• Index Addressing Mode
• Relative Addressing Mode
• Auto Increment Addressing Mode
• Auto Decrement Addressing Mode
 Register Addressing Mode
The instruction which uses processor registers to represent
operands is the instruction in register addressing mode.

Advantage: no memory references as the value to be

operated is present in the register.

Disadvantage: Registers have limited address space. So, it

has a limit on the size of value that can be stored.
 Cont..
Effective address is a register where the value of the
operand is present.
EA=R
we have two examples for register addressing mode.

Add R4, R3
Load R3, R2
 Direct Addressing Mode
• AKA Absolute Addressing mode.
• The instruction contains the address of the location in
memory where the value of the operand is stored.
• Advantage: simplest of all addressing mode.
• Disadvantage: provides a limited address space.
 Cont..
• Effective address is the
address of memory
location.
• EA = A

Examples
Add R2, A
Store R2, B
 Immediate Addressing Mode
• The value of the operand is explicitly mentioned in the
instruction.
• Effective address is not required as the operand is
explicitly defined in instruction.
• Advantage: memory reference is not required as the
value is explicitly present in the instruction
• Disadvantage: The instruction format provides a
limited size for the operand. So, the immediate
addressing mode has limited space for immediate
value.
 Cont..
Example of immediate
addressing mode:
• Add R2, #100
• Store R2, 100H
 Register Indirect Addressing Mode

• Processor register is used to hold the address of a

memory location where the operand is placed.
• This addressing mode allows executing the same set of
instructions for the different memory location.
• Advantage: same set of instructions can be used multiple
times.
• Disadvantage: the number of memory reference is more.
 Register Indirect Addressing Mode
• Effective address is the
content of memory location
present in the register.
EA=(R)

Example
• Load R3, (R2) // Load R2, A
 Index Addressing Mode
Helpful when the instructions in the program are accessing
the array or the large range of memory addresses.
EA is generated by adding a constant to the register’s
content.
The content of the register does not change.
Advantage: The index addressing mode provides flexibility
to specify memory locations.
Disadvantage: The index addressing mode is complex to
implement.
 Index Addressing Mode
The symbolic representation of index
addressing mode is denoted as: X(R)
And the effective address is denoted
by EA = X + (R)

Example
Load R2, A
Load R3, (R2)
Load R4, 4(R2)
Load R5, 8(R2)
Load R6, 12(R2)
 Relative Addressing Mode
In index addressing mode, there we were adding a
constant to the register content to refer the next operand
address.
In some computer instead of a register, the program
counter is used.
Representation of relative address mode is : X(PC)
EA = X + (PC)
Advantage: Relative addressing mode doesn’t require
memory references.
 Auto Increment Addressing Mode

Once the content of the register is accessed by the

instruction the register’s content is incremented to refer
the next operand.

Symbolically it is represented as : (R)+

 Auto Decrement Addressing Mode

It is just opposite of auto-increment mode.

In auto decrement mode the content of the register

is decremented initially and then the decremented content
of the register is used as effective address.

Symbolically it is presented as: -(R)

The auto-increment and decrement mode help to

implement the stack structure.
Summary - Addressing Modes
 Find the values Please …
What value is loaded into the accumulator for each
addressing mode?

Load #800
Load 800
Load 800
Load R1[800]
 Addressing Example
These are the values loaded into the accumulator for each
addressing mode.