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Electrical engineering (University of Nairobi)

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Lecture Notes

EECS 40
Introduction to Microelectronic Circuits

Prof. C. Chang-Hasnain
Spring 2007

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EE 40 Course Overview Important DATES

• EECS 40: • Office hours, Discussion and Lab
– One of five EECS core courses (with 20, 61A, 61B, and 61C)
• introduces “hardware” side of EECS Sessions will start on week 2
• prerequisite for EE105, EE130, EE141, EE150
– Prerequisites: Math 1B, Physics 7B
– Stay with ONE Discussion and Lab session
– Course involves three hours of lecture, one hour of discussion you registered.
and three hours of lab work each week.
• Course content: • Midterm and Final Dates:
– Fundamental circuit concepts and analysis techniques – Midterms: 6-7:40 pm on 2/21 and
– First and second order circuits, impulse and frequency response 4/11(Location TBD)
– Op Amps
– Diode and FET: Device and Circuits – Final: 8-11am on 5/14 (Location TBD)
– Amplification, Logic, Filter
• Text Book
• Best Final Project Contest
– Electrical Engineering: Principles and Applications”, third edition, – 5/4 3-5pm Location TBD
Allan R. Hambley, Pearson Prentice Hall, 2005
– Supplementary Reader – Winner projects will be displayed on second
floor Cory Hall.
EE40 Fall Slide 1 Prof. Chang-Hasnain EE40 Fall Slide 2 Prof. Chang-Hasnain
2006 2006

Grading Policy Grading Policy (Cont’d)

• Weights: • Weekly HW:
– 12%: 12 HW sets – Assignment on the web by 5 pm Wednesdays, starting 1/24/07.
– 15%: 11 Labs – Due 5 pm the following Wednesday in HW box, 240 Cory.
• 7 structured experiments (7%) – On the top page, right top corner, write your name (in the form:
• one 4-week final project (8%) Last Name, First Name) with discussion session number.
– 40%: 2 midterm exams – Graded homework will be returned one week later in discussion
– 33%: Final exam sessions.
• No late HW or Lab reports accepted • Labs
• No make-up exams unless Prof. Chang’s approval is – Complete the prelab section before going to the lab, or your
obtained at least 24 hours before exam time; proofs of points will be taken off.
extraneous circumstances are required. – Lab reports are supposed to be turned in at the end of each lab,
except for the final project, which is due at the end of the last lab
– If you miss one of the midterms, you lose 20 % of the grade.
session.
• Departmental grading policy:
• It is your responsibility to check with the head GSI from
– A typical GPA for courses in the lower division is 2.7. This GPA
would result, for example, from 17% A's, 50% B's, 20% C's, 10% time to time to make sure all grades are entered
D's, and 3% F's. correctly.
EE40 Fall Slide 3 Prof. Chang-Hasnain EE40 Fall Slide 4 Prof. Chang-Hasnain
2006 2006
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Classroom Rules Chapter 1

• Please come to class on time. There is no • Outline
web-cast this semester. – Electrical quantities
• Turn off cell phones, pagers, radio, CD, • Charge, Current, Voltage, Power
DVD, etc. – The ideal basic circuit element
• No food. – Sign conventions
– Circuit element I-V characteristics
• No pets.
– Construction of a circuit model
• Do not come in and out of classroom.
– Kirchhoff’s Current Law
• Lectures will be recorded and webcasted. – Kirchhoff’s Voltage Law

EE40 Fall Slide 5 Prof. Chang-Hasnain EE40 Fall Slide 6 Prof. Chang-Hasnain
2006 2006

Electric Charge Classification of Materials

• Electrical effects are due to • Solids in which the outermost atomic electrons
– separation of charge electric force (voltage) are free to move around are metals.
– charges in motion electric flow (current) – Metals typically have ~1 “free electron” per atom
• Macroscopically, most matter is electrically – Examples:
neutral most of the time. • Solids in which all electrons are tightly bound to
– Exceptions: clouds in a thunderstorm, people on atoms are insulators.
carpets in dry weather, plates of a charged capacitor, – Examples:
etc.
• Electrons in semiconductors are not tightly
• Microscopically, matter is full of electric charges bound and can be easily “promoted” to a free
– Electric charge exists in discrete quantities, integral state.
multiples of the electronic charge -1.6 x 10-19
– Examples:
Coulomb

EE40 Fall Slide 7 Prof. Chang-Hasnain EE40 Fall Slide 8 Prof. Chang-Hasnain
2006 2006
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Electric Current
Definition: rate of positive charge flow
Symbol: i
Units: Coulombs per second Amperes (A)
Note: Current has polarity.
i = dq/dt where
q = charge (Coulombs)
t = time (in seconds)

André-Marie Ampère's
1775-1836
EE40 Fall Slide 9 Prof. Chang-Hasnain EE40 Fall Slide 10 Prof. Chang-Hasnain
2006 2006

Electric Current Examples Current Density

1. 105 positively charged particles (each with charge Definition: rate of positive charge flow per unit area
1.6×10-19 C) flow to the right (+x direction) every Symbol: J
nanosecond
Units: A / cm2
Q 105 ×1.6 ×10−19
I = =+ −9
= 1.6 ×10−5 A Example 1:
t 10

2 cm
1 cm
C2
2. 105 electrons flow to the right (+x direction) every C1
10 cm
microsecond X

Suppose we force a current of 1 A to flow from C1 to C2:

Q 105 ×1.6 ×10−19 • Electron flow is in -x direction:
I = =− −9
= −1.6 ×10−5 A
t 10 1C / sec electrons
−19
= −6.25 × 1018
− 1.6 ×10 C / electron sec
EE40 Fall Slide 11 Prof. Chang-Hasnain EE40 Fall Slide 12 Prof. Chang-Hasnain
2006 2006
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Current Density Example (cont’d) Electric Potential (Voltage)

• Example 2: • Definition: energy per unit charge
Typical dimensions of integrated circuit • Symbol: v
components are in the range of 1 µm. What is • Units: Joules/Coulomb Volts (V)
the current density in a wire with 1 µm² area Alessandro Volta
carrying 5 mA? v = dw/dq (1745–1827)

where w = energy (in Joules), q = charge (in Coulombs)

Note: Potential is always referenced to some point.

a
Subscript convention:
vab means the potential at a
minus the potential at b.
b vab va - vb
EE40 Fall Slide 13 Prof. Chang-Hasnain EE40 Fall Slide 14 Prof. Chang-Hasnain
2006 2006

Electric Power The Ideal Basic Circuit Element

• Definition: transfer of energy per unit time i

• Symbol: p + Polarity reference for voltage can be

• Units: Joules per second Watts (W) v indicated by plus and minus signs
_ • Reference direction for the current
p = dw/dt = (dw/dq)(dq/dt) = vi is indicated by an arrow

• Concept: Attributes:
As a positive charge q moves through a James Watt • Two terminals (points of connection)
1736 - 1819
drop in voltage v, it loses energy
• Mathematically described in terms of current
energy change = qv and/or voltage
rate is proportional to # charges/sec
• Cannot be subdivided into other elements

EE40 Fall Slide 15 Prof. Chang-Hasnain EE40 Fall Slide 16 Prof. Chang-Hasnain
2006 2006
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A Note about Reference Directions Sign Convention Example

• A problem like “Find the current” or “Find the Suppose you have an unlabelled battery and you measure
voltage” is always accompanied by a definition its voltage with a digital voltmeter (DVM). It will tell you the
of the direction: magnitude and sign of the voltage.
i - v +
a With this circuit, you are
measuring vab.
−1.401 The DVM indicates −1.401, so
• In this case, if the current turns out to be 1 mA DVM va is lower than vb by 1.401 V.
flowing to the left, we would say i = -1 mA.
Which is the positive battery
• In order to perform circuit analysis to determine b +
terminal?
the voltages and currents in an electric circuit,
you need to specify reference directions.
• There is no need to guess the reference Note that we have used the “ground” symbol ( ) for the reference
direction so that the answers come out positive. node on the DVM. Often it is labeled “C” for “common.”

EE40 Fall Slide 17 Prof. Chang-Hasnain EE40 Fall Slide 18 Prof. Chang-Hasnain
2006 2006

Another Example Sign Convention for Power

Find vab, vca, vcb a
+ 2V −
c Passive sign convention
+ +

−1 V vcd p = vi p = -vi
− − i i i i
b d
+ vbd − _ _
+ +
v v v v
_ + _ +

• If p > 0, power is being delivered to the box.

Note that the labeling convention has nothing to do with
whether or not v is positive or negative. • If p < 0, power is being extracted from the box.
EE40 Fall Slide 19 Prof. Chang-Hasnain EE40 Fall Slide 20 Prof. Chang-Hasnain
2006 2006
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Power Power Calculation Example

If an element is absorbing power (i.e. if p > 0), positive Find the power absorbed by each element:
charge is flowing from higher potential to lower potential.
Conservation of energy
p = vi if the “passive sign convention” is used: total power delivered
i i equals
_ total power absorbed
+
Aside: For electronics these are unrealistically
v or v large currents – milliamperes or smaller is more
_ + typical
vi (W) p (W)
918
- 810
How can a circuit element absorb power? - 12
- 400
By converting electrical energy into heat (resistors in toasters), - 224
light (light bulbs), or acoustic energy (speakers); by storing 1116
energy (charging a battery).
EE40 Fall Slide 21 Prof. Chang-Hasnain EE40 Fall Slide 22 Prof. Chang-Hasnain
2006 2006

Circuit Elements Electrical Sources

• 5 ideal basic circuit elements: • An electrical source is a device that is capable
– voltage source active elements, capable of
of converting non-electric energy to electric
– current source generating electric energy energy and vice versa.
– resistor Examples:
passive elements, incapable of
– inductor generating electric energy
– battery: chemical electric
– capacitor – dynamo (generator/motor): mechanical electric
(Ex. gasoline-powered generator, Bonneville dam)
• Many practical systems can be modeled with
just sources and resistors Electrical sources can either deliver or absorb power
• The basic analytical techniques for solving
circuits with inductors and capacitors are
similar to those for resistive circuits
EE40 Fall Slide 23 Prof. Chang-Hasnain EE40 Fall Slide 24 Prof. Chang-Hasnain
2006 2006
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Ideal Voltage Source Ideal Current Source

• Circuit element that maintains a prescribed • Circuit element that maintains a prescribed
voltage across its terminals, regardless of the current through its terminals, regardless of the
current flowing in those terminals. voltage across those terminals.
– Voltage is known, but current is determined by the – Current is known, but voltage is determined by the
circuit to which the source is connected. circuit to which the source is connected.
• The voltage can be either independent or • The current can be either independent or
dependent on a voltage or current elsewhere in dependent on a voltage or current elsewhere in
the circuit, and can be constant or time-varying. the circuit, and can be constant or time-varying.
Device symbols: Device symbols:

vs +_ vs=µ vx +_ vs=ρ ix +_ is is=α vx is=β ix

independent voltage-controlled current-controlled independent voltage-controlled current-controlled

EE40 Fall Slide 25 Prof. Chang-Hasnain EE40 Fall Slide 26 Prof. Chang-Hasnain
2006 2006

Electrical Resistance Electrical Conductance

• Resistance: the ratio of voltage drop and • Conductance is the reciprocal of resistance.
current. The circuit element used to model this
behavior is the resistor. Symbol: G
R Ω
Circuit symbol: Units: siemens (S) or mhos ( )

Units: Volts per Ampere ohms (Ω

Ω) Example:
Consider an 8 Ω resistor. What is its conductance?
• The current flowing in the resistor
is proportional to the voltage
across the resistor:
Georg Simon Ohm
v = i R (Ohm’s Law) 1789-1854

where v = voltage (V), i = current (A), and R = resistance (Ω) Werner von Siemens
1816-1892
EE40 Fall Slide 27 Prof. Chang-Hasnain EE40 Fall Slide 28 Prof. Chang-Hasnain
2006 2006
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Short Circuit and Open Circuit Example: Power Absorbed by a Resistor

• Short circuit p = vi = ( iR )i = i2R
–R=0 no voltage difference exists p = vi = v ( v/R ) = v2/R
– all points on the wire are at the same Note that p > 0 always, for a resistor a resistor
potential.
dissipates electric energy
– Current can flow, as determined by the circuit
Example:
• Open circuit a) Calculate the voltage vg and current ia.
–R=∞ no current flows b) Determine the power dissipated in the 80Ω resistor.
– Voltage difference can exist, as determined
by the circuit

EE40 Fall Slide 29 Prof. Chang-Hasnain EE40 Fall Slide 30 Prof. Chang-Hasnain
2006 2006

More Examples Summary

• Are these interconnections permissible? • Current = rate of charge flow i = dq/dt
This circuit connection is • Voltage = energy per unit charge created by
permissible. This is because
the current sources can charge separation
sustain any voltage across; • Power = energy per unit time
Hence this is permissible.
• Ideal Basic Circuit Elements
– two-terminal component that cannot be sub-divided
– described mathematically in terms of its terminal
voltage and current
This circuit connection is – An ideal voltage source maintains a prescribed voltage
NOT permissible. It violates regardless of the current in the device.
the KCL. – An ideal current source maintains a prescribed current
regardless of the voltage across the device.
– A resistor constrains its voltage and current to be
proportional to each other: v = iR (Ohm’s law)
EE40 Fall Slide 31 Prof. Chang-Hasnain EE40 Fall Slide 32 Prof. Chang-Hasnain
2006 2006
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Summary (cont’d) Current vs. Voltage (I-V) Characteristic

• Passive sign convention • Voltage sources, current sources, and
– For a passive device, the reference direction resistors can be described by plotting the
for current through the element is in the current (i) as a function of the voltage (v)
direction of the reference voltage drop across i
the element
+
v
_

Passive? Active?

EE40 Fall Slide 33 Prof. Chang-Hasnain EE40 Fall Slide 34 Prof. Chang-Hasnain
2006 2006

I-V Characteristic of Ideal Voltage Source I-V Characteristic of Ideal Voltage Source
i i
a i a i
+ +
Vab +_ vs Vab +_ vs
_ _
i=0
b v b v
Vs>0 Vs<0

1. Plot the I-V characteristic for vs > 0. For what 2. Plot the I-V characteristic for vs < 0. For what
values of i does the source absorb power? For values of i does the source absorb power? For
what values of i does the source release power? what values of i does the source release power?
2. Repeat
Vs>0 (1)i<0for vs < 0.power; i>0 absorb power
release Vs<0 i>0 release power; i<0 absorb power
3. What is the I-V characteristic for an ideal wire?
EE40 Fall Slide 35 Prof. Chang-Hasnain EE40 Fall Slide 36 Prof. Chang-Hasnain
2006 2006
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I-V Characteristic of Ideal Voltage Source I-V Characteristic of Ideal Current Source
i i
a i i
+ +
Vab +_ vs v is
_ _
b v v

3. What is the I-V characteristic for an ideal wire? 1. Plot the I-V characteristic for is > 0. For what values
of v does the source absorb power? For what
values of v does the source release power?
Do not forget Vab=-Vba V>0 absorb power; V<0 release power

EE40 Fall Slide 37 Prof. Chang-Hasnain EE40 Fall Slide 38 Prof. Chang-Hasnain
2006 2006

Short Circuit and Open Circuit I-V Characteristic of Ideal Resistor

Wire (“short circuit”): i i
a
• R=0 no voltage difference exists +
(all points on the wire are at the same potential) v R
• Current can flow, as determined by the circuit _
b v
Air (“open circuit”): 1. Plot the I-V characteristic for R = 1 kΩ
Ω. What is the
• R=∞ no current flows slope?
• Voltage difference can exist, a a
as determined by the circuit +
Vab Vab
R R
_
b b
EE40 Fall Slide 39 Prof. Chang-Hasnain EE40 Fall Slide 40 Prof. Chang-Hasnain
2006 2006
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More Examples: Correction from last Lec. Construction of a Circuit Model

• Are these interconnections permissible? • The electrical behavior of each physical
This circuit connection is
permissible. This is because component is of primary interest.
the current sources can
sustain any voltage across;
Hence this is permissible.
• We need to account for undesired as well
as desired electrical effects.

This circuit connection is

NOT permissible. It violates
• Simplifying assumptions should be made
the KCL. wherever reasonable.

EE40 Fall Slide 41 Prof. Chang-Hasnain EE40 Fall Slide 42 Prof. Chang-Hasnain
2006 2006

Terminology: Nodes and Branches Circuit Nodes and Loops

Node: A point where two or more circuit elements • A node is a point where two or more circuit
are connected elements are connected.
• A loop is formed by tracing a closed path in a
circuit through selected basic circuit elements
without passing through any intermediate node
more than once

Branch: A path that connects two nodes

EE40 Fall Slide 43 Prof. Chang-Hasnain EE40 Fall Slide 44 Prof. Chang-Hasnain
2006 2006
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Kirchhoff’s Laws Notation: Node and Branch Voltages

• Kirchhoff’s Current Law (KCL): • Use one node as the reference (the “common”
– The algebraic sum of all the currents entering or “ground” node) – label it with a symbol
any node in a circuit equals zero. • The voltage drop from node x to the reference
• Kirchhoff’s Voltage Law (KVL): node is called the node voltage vx.
– The algebraic sum of all the voltages around • The voltage across a circuit element is defined
any loop in a circuit equals zero. as the difference between the node voltages at
its terminals
– v1 +
Example: a R1 b
+ +
va +_ vs R2 vb
Gustav Robert Kirchhoff _ _
1824-1887 c  REFERENCE NODE
EE40 Fall Slide 45 Prof. Chang-Hasnain EE40 Fall Slide 46 Prof. Chang-Hasnain
2006 2006

Using Kirchhoff’s Current Law (KCL) Formulations of Kirchhoff’s Current Law

Consider a node connecting several branches: (Charge stored in node is zero.)
Formulation 1:
i2 Sum of currents entering node
i3 = sum of currents leaving node
i1
Formulation 2:
Algebraic sum of currents entering node = 0
i4
• Currents leaving are included with a minus sign.

• Use reference directions to determine whether Formulation 3:

currents are “entering” or “leaving” the node – Algebraic sum of currents leaving node = 0
with no concern about actual current directions • Currents entering are included with a minus sign.
EE40 Fall Slide 47 Prof. Chang-Hasnain EE40 Fall Slide 48 Prof. Chang-Hasnain
2006 2006
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A Major Implication of KCL KCL Example

• KCL tells us that all of the elements in a single

branch carry the same current. Currents entering the node:
-10 mA
• We say these elements are connected in series. i
5 mA Currents leaving the node:

15 mA

3 formulations of KCL:
Current entering node = Current leaving node
1.
i1 = i2 2.
3.
EE40 Fall Slide 49 Prof. Chang-Hasnain EE40 Fall Slide 50 Prof. Chang-Hasnain
2006 2006

Generalization of KCL Generalized KCL Examples

• The sum of currents entering/leaving a closed
surface is zero. Circuit branches can be inside 50 mA
this surface, i.e. the surface can enclose more
than one node! 5µA
i2
i3
2µA i
This could be a big i
chunk of a circuit, i4
e.g. a “black box” i1

EE40 Fall Slide 51 Prof. Chang-Hasnain EE40 Fall Slide 52 Prof. Chang-Hasnain
2006 2006
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Using Kirchhoff’s Voltage Law (KVL) Formulations of Kirchhoff’s Voltage Law

Consider a branch which forms part of a loop: (Conservation of energy)
Formulation 1:
Sum of voltage drops around loop
+ – = sum of voltage rises around loop
loop v1 loop v2
_ Formulation 2:
+
Algebraic sum of voltage drops around loop = 0
Moving from + to - Moving from - to + • Voltage rises are included with a minus sign.
We add V1 We subtract V1 ! ! "#

• Use reference polarities to determine whether a Formulation 3:

voltage is dropped Algebraic sum of voltage rises around loop = 0
• No concern about actual voltage polarities • Voltage drops are included with a minus sign.
EE40 Fall Slide 53 Prof. Chang-Hasnain EE40 Fall Slide 54 Prof. Chang-Hasnain
2006 2006

A Major Implication of KVL KVL Example

• KVL tells us that any set of elements which are Three closed paths:
connected at both ends carry the same voltage. a + v2 − b
− v3 +
c
• We say these elements are connected in parallel. 1 2
+ + +
va vb vc
+ + − - −
va vb
_ _ 3
Path 1:
Applying KVL in the clockwise direction, Path 2:
starting at the top:
vb – va = 0 vb = va Path 3:
EE40 Fall Slide 55 Prof. Chang-Hasnain EE40 Fall Slide 56 Prof. Chang-Hasnain
2006 2006
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An Underlying Assumption of KVL I-V Characteristic of Elements

• No time-varying magnetic flux through the loop i Find the I-V characteristic.
a
Otherwise, there would be an induced voltage (Faraday’s Law)
+ i
R +
Vab _ vs
• Note: Antennas are designed to “pick up”
_
electromagnetic waves; “regular circuits” B( t )
often do so undesirably. b

Avoid these loops! + − v

v( t )

How do we deal with antennas (EECS 117A)?

Include a voltage source as the circuit representation
of the induced voltage or “noise”.
(Use a lumped model rather than a distributed (wave) model.)

EE40 Fall Slide 57 Prof. Chang-Hasnain EE40 Fall Slide 58 Prof. Chang-Hasnain
2006 2006

Summary Chapter 2
• An electrical system can be modeled by an electric circuit • Outline
(combination of paths, each containing 1 or more circuit
elements) – Resistors in Series – Voltage Divider
– Lumped model
• The Current versus voltage characteristics (I-V plot) is – Conductances in Parallel – Current Divider
a universal means of describing a circuit element.
– Node-Voltage Analysis
• Kirchhoff’s current law (KCL) states that the algebraic
sum of all currents at any node in a circuit equals zero. – Mesh-Current Analysis
– Comes from conservation of charge – Superposition
• Kirchhoff’s voltage law (KVL) states that the algebraic – Thévenin equivalent circuits
sum of all voltages around any closed path in a circuit
equals zero. – Norton equivalent circuits
– Comes from conservation of potential energy – Maximum Power Transfer

EE40 Fall Slide 59 Prof. Chang-Hasnain EE40 Fall Slide 60 Prof. Chang-Hasnain
2006 2006
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Resistors in Series Voltage Divider

Consider a circuit with multiple resistors connected in series.
I I = VSS / (R1 + R2 + R3 + R4)
Find their “equivalent resistance”. +
R1
• KCL tells us that the same – V1
I
current (I) flows through R2
R1 VSS +
every resistor +
− R3
R2 – V3
+ • KVL tells us
VSS R4
− R3

R4

Equivalent resistance of resistors in series is the sum

EE40 Fall Slide 61 Prof. Chang-Hasnain EE40 Fall Slide 62 Prof. Chang-Hasnain
2006 2006

When can the Voltage Divider Formula be Used? Resistors in Parallel

I I Consider a circuit with two resistors connected in parallel.
R1 R1
Find their “equivalent resistance”.
+ + x
R2 R2 • KVL tells us that the
+ – V2 VSS + – V2
VSS same voltage is dropped
− R3 − R3 I1 I2
across each resistor
ISS R1 R2
R4 R4 R5 Vx = I1 R1 = I2 R2
• KCL tells us
R R
V = 2 ⋅V V 2 ⋅V
2 SS 2 SS
R +R +R +R R +R +R +R
1 2 3 4 1 2 3 4
Correct, if nothing else Why? What is V2?
is connected to nodes
EE40 Fall Slide 63 Prof. Chang-Hasnain EE40 Fall Slide 64 Prof. Chang-Hasnain
2006 2006
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General Formula for Parallel Resistors Current Divider

What single resistance Req is equivalent to three resistors in parallel? x
I I
I1 I2
+ +
V R1 R2 R3 eq ISS R1 R2 Vx = I1 R1 = ISS Req
≡ V Req
− −

Equivalent conductance of resistors in parallel is the sum

EE40 Fall Slide 65 Prof. Chang-Hasnain EE40 Fall Slide 66 Prof. Chang-Hasnain
2006 2006

Generalized Current Divider Formula Measuring Voltage

Consider a current divider circuit with >2 resistors in parallel: To measure the voltage drop across an element in a
real circuit, insert a voltmeter (digital multimeter in
+ I voltage mode) in parallel with the element.
I1 I2 I3 V V=
I R1 R2 R3 1 1 1
+ + Voltmeters are characterized by their “voltmeter input
R1 R2 R3
− resistance” (Rin). Ideally, this should be very high
(typical value 10 MΩ)
V 1/R 3
I3 = =I
R3 1/R 1 + 1/R 2 + 1/R 3 Ideal
Voltmeter

Rin

EE40 Fall Slide 67 Prof. Chang-Hasnain EE40 Fall Slide 68 Prof. Chang-Hasnain
2006 2006
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Effect of Voltmeter Measuring Current

undisturbed circuit circuit with voltmeter inserted To measure the current flowing through an element in a
real circuit, insert an ammeter (digital multimeter in
current mode) in series with the element.
R1 R1
+ + Ammeters are characterized by their “ammeter input
VSS +
_ V2
+
VSS _ resistance” (Rin). Ideally, this should be very low
R2 R2 Rin V2
– – (typical value 1Ω).

Compare to R2 Ideal
Ammeter
R2 R 2 || Rin
V2 = VSS V2′ = VSS
R1 + R 2 R 2 || Rin + R1
Rin
Example: VSS = 10 V , R 2 = 100 K , R1 = 900 K V2 = 1V
Rin = 10 M , V2′ = ?
EE40 Fall Slide 69 Prof. Chang-Hasnain EE40 Fall Slide 70 Prof. Chang-Hasnain
2006 2006

Effect of Ammeter Using Equivalent Resistances

Measurement error due to non-zero input resistance: Simplify a circuit before applying KCL and/or KVL:
undisturbed circuit circuit with ammeter inserted Example: Find I
I Imeas
ammeter I
R1 R1 R1 R1 = R2 = 3 kΩ
Rin R3 R3 = 6 kΩ
R2
V1 +
_ V1 +
_ +
R2 7V R4
−
R2 R4 = R5 = 5 kΩ
R6
R5 R6 = 10 kΩ
V1 V1
I= Imeas =
R1 + R 2 R1 + R 2 + Rin
Example: V1 = 1 V, R1= R2 = 500 Ω, Rin = 1Ω Compare to
1V R2 + R2
I= = 1mA, I meas = ?
500Ω + 500Ω
EE40 Fall Slide 71 Prof. Chang-Hasnain EE40 Fall Slide 72 Prof. Chang-Hasnain
2006 2006
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Node-Voltage Circuit Analysis Method Nodal Analysis: Example #1

R1 R
1. Choose a reference node (“ground”) 3

Look for the one with the most connections!

+
- V1 R2 R4 IS
2. Define unknown node voltages
those which are not fixed by voltage sources
1. Choose a reference node.
3. Write KCL at each unknown node, expressing
current in terms of the node voltages (using the 2. Define the node voltages (except reference node and
I-V relationships of branch elements) the one set by the voltage source).
Special cases: floating voltage sources 3. Apply KCL at the nodes with unknown voltage.
4. Solve the set of independent equations
N equations for N unknown node voltages
4. Solve for unknown node voltages.
EE40 Fall Slide 73 Prof. Chang-Hasnain EE40 Fall Slide 74 Prof. Chang-Hasnain
2006 2006

Nodal Analysis: Example #2 Nodal Analysis w/ “Floating Voltage Source”

R1 A “floating” voltage source is one for which neither side is
Va R5 connected to the reference node, e.g. VLL in the circuit below:
Va VLL Vb
R3 I1 - +
V R2 R4 V2
1

I1 R2 R4 I2

Challenges:
Determine number of nodes needed Problem: We cannot write KCL at nodes a or b because
Deal with different types of sources there is no way to express the current through the voltage
source in terms of Va-Vb.
Solution: Define a “supernode” – that chunk of the circuit
containing nodes a and b. Express KCL for this supernode.
Incorporate voltage source constraint into KCL equation.
EE40 Fall Slide 75 Prof. Chang-Hasnain EE40 Fall Slide 76 Prof. Chang-Hasnain
2006 2006
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Nodal Analysis: Example #3 Formal Circuit Analysis Methods

supernode MESH ANALYSIS
NODAL ANALYSIS
(“Mesh-Current Method”)
Va VLL (“Node-Voltage Method”)
Vb 1) Select M independent mesh
- + 0) Choose a reference node currents such that at least one
1) Define unknown node voltages mesh current passes through each
branch*
I1 R2 R4 I2 2) Apply KCL to each unknown
M = #branches - #nodes + 1
node, expressing current in
terms of the node voltages 2) Apply KVL to each mesh,
=> N equations for expressing voltages in terms of
N unknown node voltages mesh currents
Eq’n 1: KCL at supernode
=> M equations for
3) Solve for node voltages
M unknown mesh currents
=> determine branch currents
3) Solve for mesh currents
=> determine node voltages
Substitute property of voltage source: *Simple method for planar circuits
A mesh current is not necessarily identified with a branch current.
EE40 Fall Slide 77 Prof. Chang-Hasnain EE40 Fall Slide 78 Prof. Chang-Hasnain
2006 2006

Mesh Analysis: Example #1 Mesh Analysis with a Current Source

ia ib

1. Select M mesh currents.

Problem: We cannot write KVL for meshes a and b
2. Apply KVL to each mesh.
because there is no way to express the voltage drop
across the current source in terms of the mesh currents.
Solution: Define a “supermesh” – a mesh which avoids the
3. Solve for mesh currents.
branch containing the current source. Apply KVL for this
supermesh.
EE40 Fall Slide 79 Prof. Chang-Hasnain EE40 Fall Slide 80 Prof. Chang-Hasnain
2006 2006
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Mesh Analysis: Example #2 Mesh Analysis with Dependent Sources

• Exactly analogous to Node Analysis
• Dependent Voltage Source: (1) Formulate
ia ib and write KVL mesh eqns. (2) Include and
express dependency constraint in terms of
mesh currents
Eq’n 1: KVL for supermesh • Dependent Current Source: (1) Use
supermesh. (2) Include and express
dependency constraint in terms of mesh
currents
Eq’n 2: Constraint due to current source:

EE40 Fall Slide 81 Prof. Chang-Hasnain EE40 Fall Slide 82 Prof. Chang-Hasnain
2006 2006

Circuit w/ Dependent Source Example Superposition

Find i2, i1 and io A linear circuit is one constructed only of linear
elements (linear resistors, and linear capacitors and
inductors, linear dependent sources) and
independent sources. Linear
means I-V charcteristic of elements/sources are
straight lines when plotted
Principle of Superposition:
• In any linear circuit containing multiple
independent sources, the current or voltage at
any point in the network may be calculated as
the algebraic sum of the individual contributions
of each source acting alone.
EE40 Fall Slide 83 Prof. Chang-Hasnain EE40 Fall Slide 84 Prof. Chang-Hasnain
2006 2006
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Source Combinations Superposition

• Voltage sources in series can be replaced by an Procedure:
equivalent voltage source: 1. Determine contribution due to one independent source
• Set all other sources to 0: Replace independent voltage
+ source by short circuit, independent current source by open
v1 – + circuit
v1+v2 – 2. Repeat for each independent source
+
v2 – 3. Sum individual contributions to obtain desired voltage
or current
• Current sources in parallel can be replaced by
an equivalent current source:

i1 i2 i1+i2

EE40 Fall Slide 85 Prof. Chang-Hasnain EE40 Fall Slide 86 Prof. Chang-Hasnain
2006 2006

Open Circuit and Short Circuit Superposition Example

• Open circuit i=0 ; Cut off the branch • Find Vo 2Ω 4V
• Short circuit v=0 ; replace the element by wire +–
+
+
• Turn off an independent voltage source means 24 V – 4A 4 Ω Vo
– V=0
–
– Replace by wire
– Short circuit
• Turn off an independent current source means
– i=0
– Cut off the branch
– open circuit

EE40 Fall Slide 87 Prof. Chang-Hasnain EE40 Fall Slide 88 Prof. Chang-Hasnain
2006 2006
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Equivalent Circuit Concept Thévenin Equivalent Circuit

• A network of voltage sources, current sources, • Any* linear 2-terminal (1-port) network of indep. voltage
and resistors can be replaced by an sources, indep. current sources, and linear resistors can
be replaced by an equivalent circuit consisting of an
equivalent circuit which has identical terminal
independent voltage source in series with a resistor
properties (I-V characteristics) without without affecting the operation of the rest of the circuit.
affecting the operation of the rest of the circuit.
iA iB $ %& ' &
network A network B a RTh a
+ +
of of
sources vA sources vB network + iL + iL
of
and _ and _ vL
+
vL
resistors resistors sources RL VTh – RL
and
– –
resistors
iA(vA) = iB(vB) b b
“load” resistor
EE40 Fall Slide 89 Prof. Chang-Hasnain EE40 Fall Slide 90 Prof. Chang-Hasnain
2006 2006

I-V Characteristic of Thévenin Equivalent Thévenin Equivalent Example

• The I-V characteristic for the series combination of Find the Thevenin equivalent with respect to the terminals a,b:
elements is obtained by adding their voltage drops:
For a given current i, the voltage drop
vab is equal to the sum of the voltages i
dropped across the source (VTh)
and across the resistor (iRTh)
vab = VTh- iR
RTh a
i + v
+
VTh – vab I-V characteristic
of resistor: v = iR
–

I-V characteristic of voltage source: v = VTh

EE40 Fall Slide 91 Prof. Chang-Hasnain EE40 Fall Slide 92 Prof. Chang-Hasnain
2006 2006
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RTh Calculation Example #1 Norton Equivalent Circuit

• Any* linear 2-terminal (1-port) network of indep. voltage
sources, indep. current sources, and linear resistors can
be replaced by an equivalent circuit consisting of an
independent current source in parallel with a resistor
without affecting the operation of the rest of the circuit.

( ' &
a a
Set all independent sources to 0: network + iL + iL
of
sources vL RL iN RN vL RL
and
– –
resistors
b b

EE40 Fall Slide 93 Prof. Chang-Hasnain EE40 Fall Slide 94 Prof. Chang-Hasnain
2006 2006

I-V Characteristic of Norton Equivalent Finding IN and RN = RTh

• The I-V characteristic for the parallel combination of Analogous to calculation of Thevenin Eq. Ckt:
elements is obtained by adding their currents:
For a given voltage vab, the current i is
1) Find o.c voltage and s.c. current
equal to the sum of the currents in i I-V
each of the two branches: characteristic IN isc = VTh/RTh
of current
source: i = -IN
a i
+ i = IN-Gv
v 2) Or, find s.c. current and Norton (Thev) resistance
iN RN vab
– I-V characteristic
of resistor: i=Gv
b

EE40 Fall Slide 95 Prof. Chang-Hasnain EE40 Fall Slide 96 Prof. Chang-Hasnain
2006 2006
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Finding IN and RN Maximum Power Transfer Theorem

$ %& ' &
• We can derive the Norton equivalent circuit from RTh Power absorbed by load resistor:
a Thévenin equivalent circuit simply by making a 2

source transformation: + iL 2 VTh

+ p = i RL =
L RL
RTh VTh – vL RL RTh + RL
a a
–
+ iL + iL
+
vTh – vL RL iN RN vL RL dp
To find the value of RL for which p is maximum, set to 0:
– – dRL
b b dp
= VTh2
(RTh + RL ) − RL × 2(RTh + RL ) = 0
2

dRL (RTh + RL )4
voc v
RN = RTh = ; iN = Th = isc
isc RTh (RTh + RL )2 − RL × 2(RTh + RL ) = 0
) & & *
RTh = RL
' $ %& "
EE40 Fall Slide 97 Prof. Chang-Hasnain EE40 Fall Slide 98 Prof. Chang-Hasnain
2006 2006

The Wheatstone Bridge Finding the value of Rx

• Circuit used to precisely measure resistances in • Adjust R3 until there is no current in the detector
the range from 1 Ω to 1 MΩ, with ±0.1% accuracy R2
R1 and R2 are resistors with known values Then, Rx = R3
R3 is a variable resistor (typically 1 to 11,000Ω) R1 Derivation:

Rx is the resistor whose value is to be measured

R1 R2
battery R1 R2 i1 i2
+
+ V i3 ix
V –
current detector R3 Rx
–
R3 Rx
variable resistor
Typically, R2 / R1 can be varied
from 0.001 to 1000 in decimal steps
EE40 Fall Slide 99 Prof. Chang-Hasnain EE40 Fall Slide 100 Prof. Chang-Hasnain
2006 2006
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Finding the value of Rx Identifying Series and Parallel Combinations

• Adjust R3 until there is no current in the detector Some circuits must be analyzed (not amenable to simple inspection)
R1
R2 R1 R2
Then, Rx = R3 + R3 I
V
R1 Derivation: −
+ R2 R3
V -
R4 R5
KCL => i1 = i3 and i2 = ix R4

R1 R2 KVL => i3R3 = ixRx and i1R1 = i2R2 Special cases:

i1 i2 R3 = 0 OR R3 = ∞
+ R5
V i3 ix i1R3 = i2Rx
–
R3 Rx
R3 Rx
Typically, R2 / R1 can be varied
=
R1 R2
from 0.001 to 1000 in decimal steps
EE40 Fall Slide 101 Prof. Chang-Hasnain EE40 Fall Slide 102 Prof. Chang-Hasnain
2006 2006

Y-Delta Conversion Delta-to-Wye (Pi-to-Tee) Equivalent Circuits

• These two resistive circuits are equivalent for • In order for the Delta interconnection to be equivalent
to the Wye interconnection, the resistance between
voltages and currents external to the Y and ∆ corresponding terminal pairs must be the same
circuits. Internally, the voltages and currents Rc
are different. a b
Rc (Ra + Rb)
a b
Rc Rab = = R1 + R2
a b
R1 R2 Rb Ra
Ra + Rb + Rc

Rb Ra a c Ra (Rb + Rc)
R3 b Rbc = = R2 + R3
Ra + Rb + Rc
c c R1 R2
RbRc RaRc RaRb Rb (Ra + Rc)
R1 = R2 = R3 = Rca = = R1 + R3
Ra + Rb + Rc Ra + Rb + Rc Ra + Rb + Rc R3
Ra + Rb + Rc
Brain Teaser Category: Important for motors and electrical utilities. c
EE40 Fall Slide 103 Prof. Chang-Hasnain EE40 Fall Slide 104 Prof. Chang-Hasnain
2006 2006
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∆-Y and Y-∆

∆ Conversion Formulas Circuit Simplification Example
Find the equivalent resistance Rab:
Delta-to-Wye conversion Wye-to-Delta conversion Ω
2Ω Ω
2Ω
a a
Rc
RbRc a b R1R2 + R2R3 + R3R1 Ω
18Ω Ω
12Ω
R1 = Ra = Ω
6Ω
Ra + Rb + Rc R1
Rb Ra
Ω
9Ω Ω
4Ω
RaRc c R1R2 + R2R3 + R3R1 b
R2 = Rb =
Ra + Rb + Rc R2
Ω
9Ω Ω
4Ω
a b b
RaRb R1R2 + R2R3 + R3R1
R3 = R1 R2
Rc =
Ra + Rb + Rc R3
R3

EE40 Fall Slide 105 Prof. Chang-Hasnain EE40 Fall Slide 106 Prof. Chang-Hasnain
2006 2006

Dependent Sources Comments on Dependent Sources

• Node-Voltage Method A dependent source establishes a voltage or current
– Dependent current source:
• treat as independent current source in organizing node eqns
whose value depends on the value of a voltage or
• substitute constraining dependency in terms of defined node voltages. current at a specified location in the circuit.
– Dependent voltage source: (device model, used to model behavior of transistors & amplifiers)
• treat as independent voltage source in organizing node eqns
• Substitute constraining dependency in terms of defined node voltages.
To specify a dependent source, we must identify:
• Mesh Analysis 1. the controlling voltage or current
– Dependent Voltage Source: 2. the relationship between the controlling voltage or current
• Formulate and write KVL mesh eqns.
and the supplied voltage or current
• Include and express dependency constraint in terms of mesh currents 3. the reference direction for the supplied voltage or current
– Dependent Current Source:
• Use supermesh. The relationship between the dependent source
• Include and express dependency constraint in terms of mesh currents and its reference cannot be broken!
– Dependent sources cannot be turned off for various
purposes (e.g. to find the Thévenin resistance, or in
analysis using Superposition).
EE40 Fall Slide 107 Prof. Chang-Hasnain EE40 Fall Slide 108 Prof. Chang-Hasnain
2006 2006
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Node-Voltage Method and Dependent Sources RTh Calculation Example #2

• If a circuit contains dependent sources, what to do? Find the Thevenin equivalent with respect to the terminals a,b:

Example: Ix
i∆

20 Ω +
10 Ω Vx
20 Ω
+ -
2.4 A – 80 V
–
+ 5i∆
Since there is no independent source and we cannot
arbitrarily turn off the dependence source, we can add a
voltage source Vx across terminals a-b and measure the
current through this terminal Ix . Rth= Vx/ Ix
EE40 Fall Slide 109 Prof. Chang-Hasnain EE40 Fall Slide 110 Prof. Chang-Hasnain
2006 2006

Summary of Techniques for Circuit Analysis -1

Circuit w/ Dependent Source Example (Chap 2)
Find i2, i1 and io • Resistor network
– Parallel resistors
– Series resistors
– Y-delta conversion
– “Add” current source and find voltage (or vice
versa)
• Superposition
– Leave one independent source on at a time
– Sum over all responses
– Voltage off SC
– Current off OC

EE40 Fall Slide 111 Prof. Chang-Hasnain EE40 Fall Slide 112 Prof. Chang-Hasnain
2006 2006
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Summary of Techniques for Circuit Analysis -2

(Chap 2)
Chapter 3
• Node Analysis • Outline
– Node voltage is the unknown – The capacitor
– Solve for KCL – The inductor
– Floating voltage source using super node
• Mesh Analysis
– Loop current is the unknown
– Solve for KVL
– Current source using super mesh
• Thevenin and Norton Equivalent Circuits
– Solve for OC voltage
– Solve for SC current
EE40 Fall Slide 113 Prof. Chang-Hasnain EE40 Fall Slide 114 Prof. Chang-Hasnain
2006 2006

The Capacitor Capacitor

Two conductors (a,b) separated by an insulator: Symbol: or + C
difference in potential = Vab
C C Electrolytic (polarized)
=> equal & opposite charge Q on conductors capacitor

Units: Farads (Coulombs/Volt)

Q = CVab (typical range of values: 1 pF to 1 µF; for “supercapa-
citors” up to a few F!)
where C is the capacitance of the structure, Current-Voltage relationship:
positive (+) charge is on the conductor at higher potential
ic
dQ dv dC
Parallel-plate capacitor: ic = = C c + vc +
• area of the plates = A (m2) dt dt dt vc
• separation between plates = d (m) If C (geometry) is unchanging, iC = C dvC/dt
–
• dielectric permittivity of insulator = ε
(F/m)
Aε Note: Q (vc) must be a continuous function of time
C= (FF)
=> capacitance d
EE40 Fall Slide 115 Prof. Chang-Hasnain EE40 Fall Slide 116 Prof. Chang-Hasnain
2006 2006
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Voltage in Terms of Current Stored Energy

CAPACITORS STORE ELECTRIC ENERGY
t
You might think the energy stored on a capacitor is QV =
Q(t ) = ic (t )dt + Q(0) CV2, which has the dimension of Joules. But during
0 charging, the average voltage across the capacitor was
t t only half the final value of V for a linear capacitor.
1 Q(0) 1
vc (t ) = ic (t )dt + = ic (t )dt + vc (0)
C0 C C0 Thus, energy is 1 QV = 1
CV 2 .
2 2

Uses: Capacitors are used to store energy for camera flashbulbs,

in filters that separate various frequency signals, and
they appear as undesired “parasitic” elements in circuits where Example: A 1 pF capacitance charged to 5 Volts
they usually degrade circuit performance has ½(5V)2 (1pF) = 12.5 pJ
(A 5F supercapacitor charged to 5
volts stores 63 J; if it discharged at a
constant rate in 1 ms energy is
discharged at a 63 kW rate!)
EE40 Fall Slide 117 Prof. Chang-Hasnain EE40 Fall Slide 118 Prof. Chang-Hasnain
2006 2006

A more rigorous derivation Example: Current, Power & Energy for a Capacitor
t
ic 1 i(t)
v(t ) = i (τ )dτ + v(0)
This derivation holds + v (V) C0 v(t)
+
– 10 µF
vc 1
independent of the circuit! –
t (µs)
0 1 2 3 4 5
t = t Final v = VFinal dQ v = VFinal i (µA) vc and q must be continuous
w= v c ⋅ ic dt = vc dt = v c dQ dv functions of time; however,
dt i =C ic can be discontinuous.
t = t Initial v = VInitial v = VInitial dt
0 t (µs)
v = VFinal 1 2 3 4 5
1 1
w= Cv c dv c = CVFinal2 − CVInitial2 Note: In “steady state”
(dc operation), time
v = VInitial 2 2
derivatives are zero
C is an open circuit
EE40 Fall Slide 119 Prof. Chang-Hasnain EE40 Fall Slide 120 Prof. Chang-Hasnain
2006 2006
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Capacitors in Series
p (W) i(t) + v1(t) – + v2(t) –
+
v(t) – 10 µF +
C1 C2
t (µs) i(t) i(t) v(t)=v1(t)+v2(t)
0 1 2 3 4 5 Ceq
–

p = vi
w (J) t
1
w = pdτ = Cv 2
2
0 1 1 1
0 1 2 3 4 5
t (µs) = +
Ceq C1 C2
EE40 Fall Slide 121 Prof. Chang-Hasnain EE40 Fall Slide 122 Prof. Chang-Hasnain
2006 2006

Capacitive Voltage Divider Inductor

Q: Suppose the voltage applied across a series combination
of capacitors is changed by ∆v. How will this affect the Symbol:
voltage across each individual capacitor? L

∆Q1=C1∆v1 Units: Henrys (Volts • second / Ampere)

∆v = ∆v1 + ∆v2 (typical range of values: µH to 10 H)
∆Q1
Q1+∆ + Note that no net charge can
C1 can be introduced to this node. Current in terms of voltage:
∆v1
v1+∆
-Q1−∆Q1 – Therefore, −∆Q1+∆Q2=0 1 iL
∆v
v+∆ + diL = vL (t )dt +
– L
∆Q2
Q2+∆ + C1∆v1 = C2 ∆v2 t
vL
C2 ∆v2
v2(t)+∆ C1 1 –
−Q2−∆Q2 – ∆v2 = ∆v iL (t ) = vL (τ )dτ + i (t0 )
C1 + C2 L t0
∆Q2=C2∆v2 ( + & Note: iL must be a continuous function of time
! "
EE40 Fall Slide 123 Prof. Chang-Hasnain EE40 Fall Slide 124 Prof. Chang-Hasnain
2006 2006
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Stored Energy Inductors in Series and Parallel

INDUCTORS STORE MAGNETIC ENERGY
Consider an inductor having an initial current i(t0) = i0
Common
p(t ) = v(t )i(t ) = Current

w(t ) = p(τ )dτ =

t0
Common
1 1 2
w(t ) = Li 2 − Li0 Voltage
2 2
EE40 Fall Slide 125 Prof. Chang-Hasnain EE40 Fall Slide 126 Prof. Chang-Hasnain
2006 2006

Summary Chapter 4
Capacitor Inductor • OUTLINE
dv 1 di 1
i = C ; w = Cv 2 v = L ; w = Li 2 – First Order Circuits
dt 2 dt 2
• RC and RL Examples
v cannot change instantaneously i cannot change instantaneously • General Procedure
i can change instantaneously v can change instantaneously – RC and RL Circuits with General Sources
Do not short-circuit a charged Do not open-circuit an inductor with • Particular and complementary solutions
capacitor (-> infinite current!) current (-> infinite voltage!) • Time constant
n
1 n
1 n ind.’s in series: Leq = Li – Second Order Circuits
n cap.’s in series: =
Ceq i =1 Ci i =1 • The differential equation
n
n 1 1 • Particular and complementary solutions
=
n cap.’s in parallel: Ceq = Ci n ind.’s in parallel: L i =1 Li • The natural frequency and the damping ratio
eq
i =1

In steady state (not time-varying), In steady state, an inductor • Reading

a capacitor behaves like an open behaves like a short circuit. – Chapter 4
circuit.
EE40 Fall Slide 127 Prof. Chang-Hasnain EE40 Fall Slide 128 Prof. Chang-Hasnain
2006 2006
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First-Order Circuits Response of a Circuit

• A circuit that contains only sources, resistors • Transient response of an RL or RC circuit is
and an inductor is called an RL circuit. – Behavior when voltage or current source are suddenly
• A circuit that contains only sources, resistors applied to or removed from the circuit due to switching.
and a capacitor is called an RC circuit. – Temporary behavior

• RL and RC circuits are called first-order circuits • Steady-state response (aka. forced response)
because their voltages and currents are – Response that persists long after transient has decayed
described by first-order differential equations. • Natural response of an RL or RC circuit is
R R – Behavior (i.e., current and voltage) when stored energy
in the inductor or capacitor is released to the resistive
part of the network (containing no independent
i i
vs
+
vs
+ sources).
– L – C

EE40 Fall Slide 129 Prof. Chang-Hasnain EE40 Fall Slide 130 Prof. Chang-Hasnain
2006 2006

Natural Response Summary First Order Circuits

RL Circuit RC Circuit + vr(t) - iL(t)
ic(t)
i + +
R
+ +
L R C v R vs(t) C vc(t) is(t) R L vL(t)
- -
–
-

• Inductor current • Capacitor voltage KVL around the loop: KCL at the node:
cannot change cannot change t
vr(t) + vc(t) = vs(t) v(t ) 1
instantaneously instantaneously + v( x)dx = is (t )
• In steady state, an • In steady state, a R L −∞
dvc (t )
inductor behaves like capacitor behaves like RC + vc (t ) = vs (t ) L diL (t )
dt + iL (t ) = is (t )
a short circuit. an open circuit R dt

EE40 Fall Slide 131 Prof. Chang-Hasnain EE40 Fall Slide 132 Prof. Chang-Hasnain
2006 2006
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Procedure for Finding Transient Response Procedure (cont’d)

1. Identify the variable of interest 3. Calculate the final value of the variable
• For RL circuits, it is usually the inductor current iL(t) (its value as t )
• For RC circuits, it is usually the capacitor voltage vc(t) • Again, make use of the fact that an inductor
behaves like a short circuit in steady state (t )
2. Determine the initial value (at t = t0- and t0+) of or that a capacitor behaves like an open circuit in
the variable steady state (t )
• Recall that iL(t) and vc(t) are continuous variables:
4. Calculate the time constant for the circuit
iL(t0+) = iL(t0−) and vc(t0+) = vc(t0−)
τ = L/R for an RL circuit, where R is the Thévenin
• Assuming that the circuit reached steady state before equivalent resistance “seen” by the inductor
t0 , use the fact that an inductor behaves like a short τ = RC for an RC circuit where R is the Thévenin
circuit in steady state or that a capacitor behaves like equivalent resistance “seen” by the capacitor
an open circuit in steady state

EE40 Fall Slide 133 Prof. Chang-Hasnain EE40 Fall Slide 134 Prof. Chang-Hasnain
2006 2006

Natural Response of an RC Circuit Solving for the Voltage (t ≥ 0)

• Consider the following circuit, for which the switch is • For t > 0, the circuit reduces to
closed for t < 0, and then opened at t = 0: i

Ro +

Ro t=0 Vo +
− C v R
+
Vo +
− R –
C v
– • Applying KCL to the RC circuit:
Notation:
0– is used to denote the time just prior to switching
0+ is used to denote the time immediately after switching
• The voltage on the capacitor at t = 0– is Vo
• Solution:
v(t ) = v(0)e−t / RC
EE40 Fall Slide 135 Prof. Chang-Hasnain EE40 Fall Slide 136 Prof. Chang-Hasnain
2006 2006
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Solving for the Current (t > 0) Solving for Power and Energy Delivered (t > 0)
i i

Ro + Ro +
Vo +
− C v R v(t ) = Voe−t / RC Vo +
− C v R v(t ) = Vo e − t / RC
– –

v 2 Vo2 −2 t / RC
• Note that the current changes abruptly: p= = e
i (0− ) = 0 R R
t t
v Vo −t / RC Vo2 −2 x / RC
for t > 0, i (t ) = = e w = p( x )dx = e dx
R R 0 0
R
V 1
i (0+ ) = o = CVo2 (1 − e −2 t / RC )
R 2
EE40 Fall Slide 137 Prof. Chang-Hasnain EE40 Fall Slide 138 Prof. Chang-Hasnain
2006 2006

Natural Response of an RL Circuit Solving for the Current (t ≥ 0)

• Consider the following circuit, for which the switch is • For t > 0, the circuit reduces to
closed for t < 0, and then opened at t = 0:
i +

t=0 Io Ro L R v
i +
–
Io Ro L R v
– • Applying KVL to the LR circuit:
Notation: • v(t)=i(t)R
0– is used to denote the time just prior to switching • At t=0+, i=I0,
0+ is used to denote the time immediately after switching di (t )
• At arbitrary t>0, i=i(t) and v(t ) = -L
• t<0 the entire system is at steady-state; and the inductor dt
is like short circuit
• The current flowing in the inductor at t = 0– is Io and V
across is 0. • Solution: i (t ) = i (0)e − ( R / L ) t = I0e-(R/L)t
EE40 Fall Slide 139 Prof. Chang-Hasnain EE40 Fall Slide 140 Prof. Chang-Hasnain
2006 2006
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Solving for the Voltage (t > 0) Solving for Power and Energy Delivered (t > 0)
−( R / L )t i (t ) = I o e − ( R / L )t
i(t ) = I oe
+
+
Io Ro L R v
Io Ro L R v
–
–
p = i 2 R = I o2 Re −2 ( R / L ) t
• Note that the voltage changes abruptly: t t
−
v (0 ) = 0 w = p ( x)dx = I o2 Re − 2 ( R / L ) x dx
−( R / L ) t 0 0
for t > 0, v(t ) = iR = I o Re
1 2
+
v(0 ) = I0R
=
2
(
LI o 1 − e − 2 ( R / L )t )
EE40 Fall Slide 141 Prof. Chang-Hasnain EE40 Fall Slide 142 Prof. Chang-Hasnain
2006 2006

Natural Response Summary Digital Signals

RL Circuit RC Circuit We compute with pulses.

voltage
i + We send beautiful pulses in:

L R C v R
time
–
But we receive lousy-looking

voltage
• Inductor current cannot • Capacitor voltage cannot pulses at the output:
change instantaneously change instantaneously

i ( 0 − ) = i (0 + ) v (0 − ) = v (0 + ) time

Capacitor charging effects are responsible!

i (t ) = i (0)e −t /τ v(t ) = v(0)e −t /τ
L • Every node in a real circuit has capacitance; it’s the charging
• time constant τ= • time constant τ = RC of these capacitances that limits circuit performance (speed)
R
EE40 Fall Slide 143 Prof. Chang-Hasnain EE40 Fall Slide 144 Prof. Chang-Hasnain
2006 2006
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Circuit Model for a Logic Gate Pulse Distortion

• Recall (from Lecture 1) that electronic building blocks R
The input voltage pulse
referred to as “logic gates” are used to implement width must be large
+
logical functions (NAND, NOR, NOT) in digital ICs + enough; otherwise the
– Any logical function can be implemented using these gates. Vin(t) C Vout output pulse is distorted.
– (We need to wait for the output to
• A logic gate can be modeled as a simple RC circuit: –
reach a recognizable logic level,
before changing the input again.)
R
Pulse width = 0.1RC Pulse width = RC Pulse width = 10RC
+ 6 6 6

Vin(t) + C Vout
5 5 5
4
− 4 4

Vout
Vout

Vout
3 3 3
– 2 2 2
1 1 1
0 0 0
switches between “low” (logic 0) 0 1 2 3 4 5 0 1 2 3 4 5 0 5 10 15 20 25
and “high” (logic 1) voltage states Time Time Time

EE40 Fall Slide 145 Prof. Chang-Hasnain EE40 Fall Slide 146 Prof. Chang-Hasnain
2006 2006

Example First Order Circuits: Forced Response

Suppose a voltage pulse of width R + vr(t) - iL(t)
5 µs and height 4 V is applied to the Vin Vout ic(t)
+
input of this circuit beginning at t = 0: C R
R = 2.5 k + +
vs(t) C vc(t) is(t) R L vL(t)
τ = RC = 2.5 µs C = 1 nF -
-
• First, Vout will increase exponentially toward 4 V. -
• When Vin goes back down, Vout will decrease exponentially
back down to 0 V. KVL around the loop: KCL at the node:
t
vr(t) + vc(t) = vs(t) v(t ) 1
What is the peak value of Vout? + v( x)dx = is (t )
R L −∞
The output increases for 5 µs, or 2 time constants.
dvc (t )
RC + vc (t ) = vs (t ) L diL (t )
It reaches 1-e-2 or 86% of the final value. dt + iL (t ) = is (t )
R dt
0.86 x 4 V = 3.44 V is the peak value
EE40 Fall Slide 147 Prof. Chang-Hasnain EE40 Fall Slide 148 Prof. Chang-Hasnain
2006 2006
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Complete Solution The Time Constant

• Voltages and currents in a 1st order circuit satisfy a • The complementary solution for any 1st
differential equation of the form
dx(t ) order circuit is
x(t ) + τ = f (t )
dt xc (t ) = Ke − t /τ
– f(t) is called the forcing function.
• The complete solution is the sum of particular solution
(forced response) and complementary solution (natural
response). • For an RC circuit, τ = RC
x(t ) = x p (t ) + xc (t )
• For an RL circuit, τ = L/R
– Particular solution satisfies the forcing function
– Complementary solution is used to satisfy the initial conditions.
– The initial conditions determine the value of K.
dxc (t ) Homogeneous
dx p (t )
xc (t ) + τ =0 equation
x p (t ) + τ = f (t ) dt
dt xc (t ) = Ke − t /τ
EE40 Fall Slide 149 Prof. Chang-Hasnain EE40 Fall Slide 150 Prof. Chang-Hasnain
2006 2006

What Does Xc(t) Look Like? The Particular Solution

• The particular solution xp(t) is usually a
xc (t ) = e− t /τ τ = 10-4 weighted sum of f(t) and its first derivative.
• If f(t) is constant, then xp(t) is constant.
• τ is the amount of time necessary
for an exponential to decay to • If f(t) is sinusoidal, then xp(t) is sinusoidal.
36.7% of its initial value.
• -1/τ is the initial slope of an
exponential with an initial value of
1.

EE40 Fall Slide 151 Prof. Chang-Hasnain EE40 Fall Slide 152 Prof. Chang-Hasnain
2006 2006
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The Particular Solution: F(t) Constant The Particular Solution: F(t) Sinusoid
dxP (t )
dx (t ) xP (t ) + τ = FA sin( wt ) + FB cos( wt )
xP (t ) + τ P = F dt
dt
Guess a solution Guess a solution xP (t ) = A sin( wt ) + B cos( wt )

xP (t ) = A + Bt d ( A sin( wt ) + B cos( wt ))
( A + Bt ) + τ
d ( A + Bt )
=F
( A sin( wt ) + B cos( wt )) + τ = FA sin( wt ) + FB cos( wt )
dt dt
Equation holds for all time ( A − τω B − FA ) sin(ωt ) + ( B + τω A − FB ) cos(ωt ) = 0
( A + Bt ) + τB = F
and time variations are ( A − τω B − FA ) = 0 ( B + τω A − FB ) = 0 Equation holds for all time and
independent and thus each time variations are independent
( A + τB − F ) + ( B )t = 0 F + τω F
B=−
τω FA − FB and thus each time variation
time variation coefficient is A= A 2 B
(τω ) + 1 (τω ) 2 + 1 coefficient is individually zero
individually zero
1 τω 1
xP (t ) = sin(ωt ) + cos(ωt )
2 2
( B) = 0 ( A + τB − F ) = 0 (τω ) + 1 (τω ) + 1 (τω ) 2 + 1
B=0 A= F 1
= cos(ωt − θ ); where θ = tan −1 (τω )
2
(τω ) + 1
EE40 Fall Slide 153 Prof. Chang-Hasnain EE40 Fall Slide 154 Prof. Chang-Hasnain
2006 2006

The Particular Solution: F(t) Exp. The Total Solution: F(t) Sinusoid
dxP (t )
dxP (t ) xP (t ) + τ
= FA sin( wt ) + FB cos( wt )
xP (t ) + τ = F1e −αt + F2 dt
dt F + τω F τω FA − FB
Guess a solution xP (t ) = A sin( wt ) + B cos( wt ) A= A 2 B B=−
(τω ) + 1 (τω ) 2 + 1
xP (t ) = A + Be −αt
d ( A + Be −αt )
( A + Be −αt ) + τ = F1e −αt + F2 −t
τ
dt xC (t ) = Ke
Equation holds for all time
( A + Be −αt ) − ατBe −αt = F1e −αt + F2 xT (t ) = A sin( wt ) + B cos( wt ) + Ke
−t
τ
and time variations are
independent and thus each ( A − F2 ) + ( B − ατ − F1 )e −αt = 0 Only K is unknown and
time variation coefficient is
is determined by the
individually zero
initial condition at t =0 Example: xT(t=0) = VC(t=0)
( A − F2 ) = 0 −0
τ
( B − ατ − F1 ) = 0 xT (0) = A sin(0) + B cos(0) + Ke = VC (t = 0)
B = ατ + F1 A = F2
xT (0) = B + K = VC (t = 0) K = VC (t = 0) − B

EE40 Fall Slide 155 Prof. Chang-Hasnain EE40 Fall Slide 156 Prof. Chang-Hasnain
2006 2006
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Example 2nd Order Circuits

• Any circuit with a single capacitor, a single
R t=0 inductor, an arbitrary number of sources,
+ +
Vs − C vc
and an arbitrary number of resistors is a
– circuit of order 2.
• Any voltage or current in such a circuit is
the solution to a 2nd order differential
• Given vc(0-)=1, Vs=2 cos(ωt), ω=200. equation.
• Find i(t), vc(t)=?

EE40 Fall Slide 157 Prof. Chang-Hasnain EE40 Fall Slide 158 Prof. Chang-Hasnain
2006 2006

A 2nd Order RLC Circuit The Differential Equation

i (t)
i (t) + vr(t) -
R R +
+ +
vs(t) C vs(t) C vc(t)
- - -
- vl(t) +
L
KVL around the loop: L
• Application: Filters vr(t) + vc(t) + vl(t) = vs(t)
– A bandpass filter such as the IF amp for 1
t
di (t )
the AM radio. Ri (t ) + i ( x)dx + L = vs (t )
C −∞ dt
– A lowpass filter with a sharper cutoff R di (t ) 1 d 2i (t ) 1 dvs (t )
+ i (t ) + =
than can be obtained with an RC circuit. L dt LC dt 2 L dt
EE40 Fall Slide 159 Prof. Chang-Hasnain EE40 Fall Slide 160 Prof. Chang-Hasnain
2006 2006
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The Differential Equation The Particular Solution

The voltage and current in a second order circuit is • The particular solution xp(t) is usually a
the solution to a differential equation of the weighted sum of f(t) and its first and
following form: second derivatives.
d 2 x(t ) dx(t ) • If f(t) is constant, then xp(t) is constant.
2
+ 2α + ω02 x(t ) = f (t )
dt dt • If f(t) is sinusoidal, then xp(t) is sinusoidal.
x(t ) = x p (t ) + xc (t )
Xp(t) is the particular solution (forced response)
and Xc(t) is the complementary solution (natural
response).

EE40 Fall Slide 161 Prof. Chang-Hasnain EE40 Fall Slide 162 Prof. Chang-Hasnain
2006 2006

The Complementary Solution Characteristic Equation

The complementary solution has the following • To find the complementary solution, we
form: st
xc (t ) = Ke need to solve the characteristic equation:
K is a constant determined by initial conditions.
s 2 + 2ζω0 s + ω02 = 0
s is a constant determined by the coefficients of α = ζω0
the differential equation. • The characteristic equation has two roots-
d 2 Ke st dKe st call them s1 and s2.
2
+ 2α + ω02 Ke st = 0
dt dt
2 st st 2 st xc (t ) = K1e s1t + K 2 e s2t
s Ke + 2α sKe + ω Ke = 0 0
s1 = −ζω0 + ω0 ζ 2 − 1
s 2 + 2α s + ω02 = 0
s2 = −ζω0 − ω0 ζ 2 − 1

EE40 Fall Slide 163 Prof. Chang-Hasnain EE40 Fall Slide 164 Prof. Chang-Hasnain
2006 2006
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Damping Ratio and Natural Frequency Overdamped : Real Unequal Roots

α s1 = −ζω0 + ω0 ζ 2 − 1 • If ζ > 1, s1 and s2 are real and not equal.
ζ =
ω0 −ςω 0 +ω 0 ς 2 −1 t −ςω 0 −ω 0 ς 2 −1 t
damping ratio s2 = −ζω0 − ω0 ζ 2 − 1 ic (t ) = K 1e + K 2e
• The damping ratio determines what type of 1 0.8

0.8 0.6
solution we will get: 0.6

i(t)
0.4

i(t)
– Exponentially decreasing (ζ >1) 0.4
0.2
0.2
– Exponentially decreasing sinusoid (ζ < 1) 0
0
-1.00E-06
-1.00E-06 -0.2

• The natural frequency is ω0 t t

– It determines how fast sinusoids wiggle.

EE40 Fall Slide 165 Prof. Chang-Hasnain EE40 Fall Slide 166 Prof. Chang-Hasnain
2006 2006

Underdamped: Complex Roots Critically damped: Real Equal Roots

• If ζ < 1, s1 and s2 are complex. • If ζ = 1, s1 and s2 are real and equal.
• Define the following constants:
xc (t ) = K1e −ςω0t + K 2te −ςω0t
α = ζω0 ω d = ω0 1 − ζ 2
xc (t ) = e −α t ( A1 cos ωd t + A2 sin ωd t )
1
Note: The
0.8
0.6
degeneracy of the
0.4
0.2
roots results in the
i(t)

-1.00E-05
0
-0.2 1.00E-05 3.00E-05
extra factor of ‘t’
-0.4
-0.6
-0.8
-1

t
EE40 Fall Slide 167 Prof. Chang-Hasnain EE40 Fall Slide 168 Prof. Chang-Hasnain
2006 2006
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Example Example
For the example, what are ζ and ω0? • ζ = 0.011
• ω0 = 2π455000
i (t) d 2i (t ) R di (t ) 1 1 dvs (t ) • Is this system over damped, under
+ + i (t ) =
dt 2
L dt LC L dt damped, or critically damped?
10Ω
+ • What will the current look like?
769pF d 2 xc (t ) dx (t )
- 2
+ 2ζω0 c + ω02 xc (t ) = 0 1

dt dt 0.8

159µH 0.6
0.4

1 R R C 0.2

i(t)
2
ω =
0 , 2ζω0 = , ζ = -1.00E-05
0
-0.2 1.00E-05 3.00E-05
LC L 2 L -0.4
-0.6
-0.8
-1

t
EE40 Fall Slide 169 Prof. Chang-Hasnain EE40 Fall Slide 170 Prof. Chang-Hasnain
2006 2006

Slightly Different Example Types of Circuit Excitation

• Increase the resistor to 1kΩ
Linear Time- Linear Time-
• What are ζ and ω0?
Invariant Invariant
i (t) Circuit
1 Circuit
0.8
1kΩ 0.6
Steady-State Excitation OR
i(t)

+ 0.4
vs(t) 769pF 0.2
(DC Steady-State)
- 0 Digital Linear Time-
159µH -1.00E-06
Pulse
Linear Time- Invariant
t Source
Invariant Circuit
ζ = 2.2 Circuit
ω0 = 2π455000 Sinusoidal (Single- Transient Excitation
Frequency) Excitation
AC Steady-State
EE40 Fall Slide 171 Prof. Chang-Hasnain EE40 Fall Slide 172 Prof. Chang-Hasnain
2006 2006
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Why is Single-Frequency Excitation Important? Representing a Square Wave as a Sum of Sinusoids

a b
• Some circuits are driven by a single-frequency

signal(V)

signal(V)
sinusoidal source.

Signal

Signal
• Some circuits are driven by sinusoidal sources
whose frequency changes slowly over time.
• You can express any periodic electrical signal as T i me (ms)
c d
a sum of single-frequency sinusoids – so you

Relative Amplitude
can analyze the response of the (linear, time-

Signal (V)
invariant) circuit to each individual frequency
component and then sum the responses to get
the total response. Frequency (Hz)

(a)Square wave with 1-second period. (b) Fundamental component

• This is known as Fourier Transform and is (dotted) with 1-second period, third-harmonic (solid black) with1/3-second
tremendously important to all kinds of engineering period, and their sum (blue). (c) Sum of first ten components. (d)
disciplines! Spectrum with 20 terms.
EE40 Fall Slide 173 Prof. Chang-Hasnain EE40 Fall Slide 174 Prof. Chang-Hasnain
2006 2006

Steady-State Sinusoidal Analysis Chapter 5

• Also known as AC steady-state • OUTLINE
• Any steady state voltage or current in a linear circuit with
– Phasors as notation for Sinusoids
a sinusoidal source is a sinusoid.
– This is a consequence of the nature of particular solutions for – Arithmetic with Complex Numbers
sinusoidal forcing functions.
– Complex impedances
• All AC steady state voltages and currents have the same
frequency as the source. – Circuit analysis using complex impdenaces
• In order to find a steady state voltage or current, all we – Dervative/Integration as multiplication/division
need to know is its magnitude and its phase relative to – Phasor Relationship for Circuit Elements
the source
– We already know its frequency. • Reading
• Usually, an AC steady state voltage or current is given – Chap 5
by the particular solution to a differential equation.
– Appendix A

EE40 Fall Slide 175 Prof. Chang-Hasnain EE40 Fall Slide 176 Prof. Chang-Hasnain
2006 2006
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Example 1: 2nd Order RLC Circuit Example 2: 2nd Order RLC Circuit

t=0 t=0

R R
+ +
Vs C L Vs C L
- -

EE40 Fall Slide 177 Prof. Chang-Hasnain EE40 Fall Slide 178 Prof. Chang-Hasnain
2006 2006

Sinusoidal Sources Create Too Much Algebra Complex Numbers (1)

dxP (t )
imaginary • x is the real part
xP (t ) + τ = FA sin( wt ) + FB cos( wt ) axis
dt
y
• y is the imaginary part
Guess a solution Two terms to be general j = (−1)
Dervatives • z is the magnitude

z
xP (t ) = A sin( wt ) + B cos( wt )
Addition θ • θ is the phase
d ( A sin( wt ) + B cos( wt )) real
( A sin( wt ) + B cos( wt )) + τ = FA sin( wt ) + FB cos( wt )
dt
axis x = z cos θ y = z sin θ
( A − τB − FA ) sin( wt ) + ( B + τA − FB ) cos( wt ) = 0 x
• Rectangular Coordinates y
Equation holds for all time ( A − τB − FA ) = 0 z = x2 + y2 θ = tan −1
Z = x + jy x
and time variations are ( B + τA − FB ) = 0
• Polar Coordinates: Z = z (cos θ + j sin θ )
independent and thus each F + τF
A = A2 B
τF − F
time variation coefficient is B = − A2 B Z=z∠θ
τ +1 τ +1 1 = 1e j 0 = 1∠0°
individually zero • Exponential Form:
π
Phasors (vectors that rotate in the complex Z = Z e = ze jθ jθ
j = 1e
j
2
= 1∠90°
plane) are a clever alternative.
EE40 Fall Slide 179 Prof. Chang-Hasnain EE40 Fall Slide 180 Prof. Chang-Hasnain
2006 2006
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Complex Numbers (2) Arithmetic With Complex Numbers

• To compute phasor voltages and currents, we
e jθ + e − jθ need to be able to perform computation with
Euler’s Identities cos θ =
2 complex numbers.
e − e − jθ
jθ
– Addition
sin θ =
2j
– Subtraction
e jθ = cos θ + j sin θ – Multiplication
e jθ = cos 2 θ + sin 2 θ = 1 – Division
• (And later use multiplication by jω to replace
Exponential Form of a complex number – Diffrentiation
jθ jθ
Z = Z e = ze = z∠θ – Integration

EE40 Fall Slide 181 Prof. Chang-Hasnain EE40 Fall Slide 182 Prof. Chang-Hasnain
2006 2006

Addition Addition
• Addition is most easily performed in
rectangular coordinates:
A = x + jy Imaginary
B = z + jw Axis
A+B

A + B = (x + z) + j(y + w)
B A
Real
Axis

EE40 Fall Slide 183 Prof. Chang-Hasnain EE40 Fall Slide 184 Prof. Chang-Hasnain
2006 2006
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Subtraction Subtraction
• Subtraction is most easily performed in
rectangular coordinates:
A = x + jy Imaginary
Axis
B = z + jw

A - B = (x - z) + j(y - w) B A
Real
Axis
A-B

EE40 Fall Slide 185 Prof. Chang-Hasnain EE40 Fall Slide 186 Prof. Chang-Hasnain
2006 2006

Multiplication Multiplication
• Multiplication is most easily performed in
polar coordinates:
A = AM ∠ θ Imaginary
Axis
B = BM ∠ φ A×B
B

A × B = (AM × BM) ∠ (θ + φ) A
Real
Axis

EE40 Fall Slide 187 Prof. Chang-Hasnain EE40 Fall Slide 188 Prof. Chang-Hasnain
2006 2006
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Division Division
• Division is most easily performed in polar
coordinates:
A = AM ∠ θ Imaginary
Axis
B = BM ∠ φ
B

A / B = (AM / BM) ∠ (θ − φ) A
Real
Axis
A/B

EE40 Fall Slide 189 Prof. Chang-Hasnain EE40 Fall Slide 190 Prof. Chang-Hasnain
2006 2006

Arithmetic Operations of Complex Numbers Phasors

• Add and Subtract: it is easiest to do this in rectangular • Assuming a source voltage is a sinusoid time-
format varying function
– Add/subtract the real and imaginary parts separately
• Multiply and Divide: it is easiest to do this in
v(t) = V cos (ωt + θ)
exponential/polar format • We can write:
– Multiply (divide) the magnitudes v(t ) = V cos(ωt + θ ) = V Re e j (ωt +θ ) = Re Ve j (ωt +θ )
– Add (subtract) the phases
Define Phasor as Ve jθ = V ∠θ
Z1 = z1e jθ1 = z1∠θ1 = z1 cos θ1 + jz1 sin θ1
Z 2 = z2 e jθ2 = z2∠θ 2 = z2 cos θ 2 + jz2 sin θ 2
• Similarly, if the function is v(t) = V sin (ωt + θ)
π
Z1 + Z 2 = ( z1 cos θ1 + z2 cos θ 2 ) + j ( z1 sin θ1 + z2 sin θ 2 ) π j (ω t +θ − )
v(t ) = V sin(ωt + θ ) = V cos(ωt + θ − ) = Re Ve 2
2
Z1 − Z 2 = ( z1 cos θ1 − z2 cos θ 2 ) + j ( z1 sin θ1 − z2 sin θ 2 )
Z1 × Z 2 = ( z1 × z2 )e j (θ1 +θ2 ) = ( z1 × z2 )∠(θ1 + θ 2 ) Phasor = V ∠ ( )
θ−
π

2
Z1 / Z 2 = ( z1 / z2 )e j (θ1 −θ2 ) = ( z1 / z2 )∠(θ1 − θ 2 )
EE40 Fall Slide 191 Prof. Chang-Hasnain EE40 Fall Slide 192 Prof. Chang-Hasnain
2006 2006
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Phasor: Rotating Complex Vector Complex Exponentials

• We represent a real-valued sinusoid as the real
{ } (
v(t ) = V cos(ωt + φ ) = Re Ve jφ e jwt = Re V e jωt ) part of a complex exponential after multiplying
by e jω.t
Imaginary • Complex exponentials
Axis Rotates at uniform – provide the link between time functions and phasors.
– Allow dervatives and integrals to be replaced by
angular velocity ωt multiplying or dividing by jω
– make solving for AC steady state simple algebra with
complex numbers.
V
Real • Phasors allow us to express current-voltage
ωt+φ
cos(ω φ)
Axis relationships for inductors and capacitors much
like we express the current-voltage relationship
The head start angle is φ. for a resistor.

EE40 Fall Slide 193 Prof. Chang-Hasnain EE40 Fall Slide 194 Prof. Chang-Hasnain
2006 2006

I-V Relationship for a Capacitor Capacitor Impedance (1)

i(t) + dv(t )
i (t ) = C
C v(t dt
i(t) +
dv(t ) -)
C v(t) i (t ) = C
dt v(t ) = V cos(ωt + θ ) =
V j (ωt +θ ) − j (ωt +θ )
e +e
- 2
dv(t ) CV d j (ωt +θ ) − j (ωt +θ ) CV
i (t ) = C = e +e = jω e j (ωt +θ ) − e − j (ωt +θ )
dt 2 dt 2
−ωCV j (ωt +θ ) − j (ωt +θ ) π
Suppose that v(t) is a sinusoid: = e −e = −ωCV sin(ωt + θ ) = ωCV cos(ωt + θ + )
2j 2
v(t) = Re{VM ej(ωt+θ)} V
Zc = =
V ∠θ
=
V π
∠(θ − θ − ) =
1 π
∠(− ) = − j
1
=
1
I π ωCV 2 ωC 2 ωC jωC
Find i(t). I∠ θ +
2

EE40 Fall Slide 195 Prof. Chang-Hasnain EE40 Fall Slide 196 Prof. Chang-Hasnain
2006 2006
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Capacitor Impedance (2) Example

v(t) = 120V cos(377t + 30°)
i(t) + dv(t )
i (t ) = C C = 2µF
C v(t dt
-)
Phasor definition
• What is V?
j (ωt +θ )
v(t ) = V cos(ωt + θ ) = Re Ve V = V ∠θ • What is I?
dv(t ) de j (ωt +θ ) • What is i(t)?
i (t ) = C = Re CV = Re jωCVe j (ωt +θ ) I = I ∠θ
dt dt
V V ∠θ V 1
Zc = = = ∠(θ − θ ) =
I I ∠θ jωCV jωC

EE40 Fall Slide 197 Prof. Chang-Hasnain EE40 Fall Slide 198 Prof. Chang-Hasnain
2006 2006

Computing the Current Inductor Impedance

i(t) +
di (t )
Note: The differentiation and integration L v(t) v(t ) = L
dt
operations become algebraic operations -
d 1
jω dt
dt jω V = jωL I

EE40 Fall Slide 199 Prof. Chang-Hasnain EE40 Fall Slide 200 Prof. Chang-Hasnain
2006 2006
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Example Phase
Voltage
i(t) = 1µA cos(2π 9.15 107t + 30°) 7 cos(ωt ) = 7∠0° inductor current
L = 1µH π
7 sin(ωt ) = 7 cos(ωt − ) = 7∠ −
π
8 2 2
6
lead Behind
• What is I? 4

• What is V? 2
0 t
• What is v(t)?
-2 0 0.01 0.02 0.03 0.04 0.05

-4
-6
-8 capacitor current
π π
−7 sin(ωt ) = 7 cos(ωt + ) = 7∠ +
2 2
EE40 Fall Slide 201 Prof. Chang-Hasnain EE40 Fall Slide 202 Prof. Chang-Hasnain
2006 2006

Phasor Diagrams Impedance

• A phasor diagram is just a graph of • AC steady-state analysis using phasors
several phasors on the complex plane allows us to express the relationship
(using real and imaginary axes). between current and voltage using a
• A phasor diagram helps to visualize the formula that looks likes Ohm’s law:
relationships between currents and V=IZ
voltages. • Z is called impedance.
• Capacitor: I leads V by 90o
• Inductor: V leads I by 90o

EE40 Fall Slide 203 Prof. Chang-Hasnain EE40 Fall Slide 204 Prof. Chang-Hasnain
2006 2006
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Some Thoughts on Impedance Example: Single Loop Circuit

• Impedance depends on the frequency ω.
20kΩ +
• Impedance is (often) a complex number. +
VC
10V ∠ 0° 1µF
• Impedance allows us to use the same - -
solution techniques for AC steady state as
we use for DC steady state. f=60 Hz, VC=?
How do we find VC?
First compute impedances for resistor and capacitor:
ZR = R= 20kΩ = 20kΩ ∠ 0°
ZC = 1/j (2πf x 1µF) = 2.65kΩ ∠ -90°

EE40 Fall Slide 205 Prof. Chang-Hasnain EE40 Fall Slide 206 Prof. Chang-Hasnain
2006 2006

Impedance Example What happens when ω changes?

20kΩ ∠ 0°

+ 20kΩ +
+ +
10V ∠ 0° VC 2.65kΩ ∠ -90° 10V ∠ 0° 1µF VC
- - - -

Now use the voltage divider to find VC: ω = 10

Find VC
2.65kΩ∠ - 90°
VC = 10V ∠0°
2.65kΩ∠ - 90° + 20kΩ∠0°
VC = 1.31V ∠ - 82.4°
EE40 Fall Slide 207 Prof. Chang-Hasnain EE40 Fall Slide 208 Prof. Chang-Hasnain
2006 2006
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Circuit Analysis Using Complex Impedances Steady-State AC Analysis

• Suitable for AC steady state.
• KVL +
v1 (t ) + v2 (t ) + v3 (t ) = 0 0.1µF
5mA ∠ 0° V
V1 cos (ωt + θ1 ) + V2 cos (ωt + θ 2 ) + V3 cos (ωt + θ3 ) = 0 1kΩ
-
Re V1e j (ωt +θ1 ) + V2 e j (ωt +θ2 ) + V3e j (ωt +θ3 ) = 0
Find v(t) for ω=2π 3000
Phasor Form KVL
V1e j (θ1 ) + V2e j (θ2 ) + V3e j (θ3 ) = 0
V1 + V2 + V3 = 0 +
• Phasor Form KCL I1 + I 2 + I 3 = 0
5mA ∠ 0° V -j530kΩ
• Use complex impedances for inductors and capacitors and
follow same analysis as in chap 2. 1kΩ
-
EE40 Fall Slide 209 Prof. Chang-Hasnain EE40 Fall Slide 210 Prof. Chang-Hasnain
2006 2006

Find the Equivalent Impedance Change the Frequency

+
+
0.1µF
5mA ∠ 0° V
5mA ∠ 0° Zeq V 1kΩ
-
-
Find v(t) for ω=2π 455000
1000(− j 530 ) 10 ∠0° × 530∠ − 90°
3
Z eq = =
1000 − j 530 1132∠ − 27.9°
+
Z eq = 468.2Ω∠ − 62.1° -j3.5Ω
5mA ∠ 0° V
V = IZ eq = 5mA∠0° × 468.2Ω∠ − 62.1°
1kΩ
V = 2.34V∠ − 62.1° -
v(t ) = 2.34V cos(2π 3000t − 62.1°)

EE40 Fall Slide 211 Prof. Chang-Hasnain EE40 Fall Slide 212 Prof. Chang-Hasnain
2006 2006
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Find an Equivalent Impedance Series Impedance

+
Z1
5mA ∠ 0° Zeq V
Z2 Zeq
- Z3
1000(− j 3.5) 10 3 ∠0° × 3.5∠ − 90°
Z eq = =
1000 − j 3.5 1000∠ − 0.2° Zeq = Z1 + Z2 + Z3
Z eq = 3.5Ω∠ − 89.8° For example:
V = IZ eq = 5mA∠0° × 3.5Ω∠ − 89.8°
V = 17.5mV∠ − 89.8° C1 C2
L1 L2
v(t ) = 17.5mV cos(2π 455000t − 89.8°) 1 1
Zeq = jω(L1+L2) Z eq = +
jωC1 jωC2

EE40 Fall Slide 213 Prof. Chang-Hasnain EE40 Fall Slide 214 Prof. Chang-Hasnain
2006 2006

Parallel Impedance Steady-State AC Node-Voltage Analysis

VC
+ -
Z1 Z2 Z3 Zeq I0sin(ωt) C I1cos(ωt)
R L

1/Zeq = 1/Z1 + 1/Z2 + 1/Z3

For example:
• Try using Thevinin equivalent circuit.

L1 L2 C1 C2 • What happens if the sources are at different

frequencies?
L1 L2 1
Z eq = jω Z eq =
( L1 + L2 ) jω (C1 + C2 )

EE40 Fall Slide 215 Prof. Chang-Hasnain EE40 Fall Slide 216 Prof. Chang-Hasnain
2006 2006
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Resistor I-V relationship

vR = iRR ………….VR = IRR where R is the resistance in ohms, R C L
VR = phasor voltage, IR = phasor current
(boldface indicates complex quantity)
v0 (t ) = V0 cos(ωt ) v0 (t ) = V0 cos(ωt ) v0 (t ) = V0 cos(ωt )
Capacitor I-V relationship
iC = CdvC/dt ...............Phasor current IC = phasor voltage VC / V 0 = V0 ∠0 V 0 = V0 ∠0 V 0 = V0 ∠0
capacitive impedance ZC: IC = VC/ZC
where ZC = 1/jωC , j = (-1)1/2 and boldface V0 V0
indicates complex quantity i0 (t ) = cos(ωt ) i0 (t ) = −ωCV0 sin(ωt ) i0 (t ) = sin(ωt )
R ωL
Inductor I-V relationship V0 V0
I0 = ∠0 I 0 = ωCV0∠90 I0 = ∠ − 90
vL = LdiL/dt ...............Phasor voltage VL = phasor current IL/ R ωL
inductive impedance ZL VL = ILZL
where ZL = jωL, j = (-1)1/2 and boldface
indicates complex quantity

EE40 Fall Slide 217 Prof. Chang-Hasnain EE40 Fall Slide 218 Prof. Chang-Hasnain
2006 2006

Thevenin Equivalent Root Mean Square (rms) Values

ZTH • rms valued defined as
10V ∠ 0° 20kΩ T
1 2
+ + + vRMS = v (t )dt T = period
T o
1µF VC VTH
- - - • Assuming a sinusoid gives
f=60 Hz T
1 2
vRMS = vm cos 2 (ωt + θ )dt
T o
ZR = R= 20kΩ = 20kΩ ∠ 0°
• Using an identity gives
ZC = 1/j (2πf x 1µF) = 2.65kΩ ∠ -90°
2 T
vm
vRMS = [1 + cos(2ωt + 2θ )]dt
2.65kΩ∠ - 90° 2T o
VTH = VOC = 10V ∠0° = 1.31∠ − 82.4
2.65kΩ∠ - 90° + 20kΩ∠0° • Evaluating at limits gives
2 vm
20kΩ∠0° ⋅ 2.65kΩ∠ - 90° vRMS =
vm
[T +
1
sin(2ωT + 2θ ) −
1
sin(2θ )] vRMS =
ZTH = Z R || Z C = ° = 2.62∠ − 82.4 2T 2ω 2w 2
2.65kΩ∠ - 90° + 20kΩ∠0°
EE40 Fall Slide 219 Prof. Chang-Hasnain EE40 Fall Slide 220 Prof. Chang-Hasnain
2006 2006
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Power: Instantaneous and Time-Average Maximum Average Power Transfer

For a Resistor
• The instantaneous power is v(t ) 2 ZTH
p(t ) = v(t )i (t ) =
R +
• The time-average power is VTH ZLOAD
T T T
-
1 1 v(t ) 2 1 1 v2
PAVE = p (t )dt = dt = [ v(t ) 2 dt ] = rms
T 0 T 0 R R T 0 R
For an Impedance v(t )i (t

• The instantaneous power is • Maximum time average power occurs when

p(t ) = v(t )i (t ) Z LOAD = Z*TH
• The time-average power isT • This presents a resistive impedance to the source
T
1 1 *
Z total = ZTH + Z*TH
PAVE = p(t )dt = v(t )i (t )dt = Re{Vrms ⋅ I rms }
T T 0
• The reactive power at 2ω is
0
• Power transferred is
V* V2
Q = Im{Vrms ⋅ I *rms } 2
PAVE + Q 2 = (Vrms ⋅ I rms ) 2 PAVE = Re{VI*} = Re{V } = 12 rms
2R R
EE40 Fall Slide 221 Prof. Chang-Hasnain EE40 Fall Slide 222 Prof. Chang-Hasnain
2006 2006

Chapter 6 Bel and Decibel (dB)

• OUTLINE • A bel (symbol B) is a unit of measure of ratios of power

levels, i.e. relative power levels.
– Frequency Response for Characterization – The name was coined in the early 20th century in honor of
– Asymptotic Frequency Behavior Alexander Graham Bell, a telecommunications pioneer.
– The bel is a logarithmic measure. The number of bels for a given
– Log magnitude vs log frequency plot ratio of power levels is calculated by taking the logarithm, to the
base 10, of the ratio.
– Phase vs log frequency plot
– one bel corresponds to a ratio of 10:1.
– dB scale – B = log10(P1/P2) where P1 and P2 are power levels.
– Transfer function example • The bel is too large for everyday use, so the decibel
(dB), equal to 0.1B, is more commonly used.
– 1dB = 10 log10(P1/P2)
• dB are used to measure
– Electric power, Gain or loss of amplifiers, Insertion loss of filters.

EE40 Fall Slide 223 Prof. Chang-Hasnain EE40 Fall Slide 224 Prof. Chang-Hasnain
2006 2006
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Logarithmic Measure for Power Logarithmic Measures for Voltage or Current

• To express a power in terms of decibels, one starts by From the expression for power ratios in decibels, we can
choosing a reference power, Preference, and writing readily derive the corresponding expressions for voltage
Power P in decibels = 10 log10(P/Preference) or current ratios.
• Exercise:
Suppose that the voltage V (or current I) appears across
– Express a power of 50 mW in decibels relative to 1 watt.
(or flows in) a resistor whose resistance is R. The
– P (dB) =10 log10 (50 x 10-3) = - 13 dB
corresponding power dissipated, P, is V2/R (or I2R). We
• Exercise: can similarly relate the reference voltage or current to the
– Express a power of 50 mW in decibels relative to 1 mW. reference power, as
– P (dB) =10 log10 (50) = 17 dB.
• dBm to express absolute values of power relative to a Preference = (Vreference)2/R or Preference= (Ireference)2R.
milliwatt.
– dBm = 10 log10 (power in milliwatts / 1 milliwatt) Hence,
– 100 mW = 20 dBm Voltage, V in decibels = 20log10(V/Vreference)
– 10 mW = 10 dBm Current, I, in decibels = 20log10(I/Ireference)
EE40 Fall Slide 225 Prof. Chang-Hasnain EE40 Fall Slide 226 Prof. Chang-Hasnain
2006 2006

Logarithmic Measures for Voltage or Current Logarithmic Measures for Voltage or Current
Note that the voltage and current expressions are just
like the power expression except that they have 20 as The gain produced by an amplifier or the loss of a filter
the multiplier instead of 10 because power is is often specified in decibels.
proportional to the square of the voltage or current.
The input voltage (current, or power) is taken as the
reference value of voltage (current, or power) in the
Exercise: How many decibels larger is the voltage of a decibel defining expression:
9-volt transistor battery than that of a 1.5-volt AA
battery? Let Vreference = 1.5. The ratio in decibels is Voltage gain in dB = 20 log10(Voutput/Vinput)
Current gain in dB = 20log10(Ioutput/Iinput
20 log10(9/1.5) = 20 log10(6) = 16 dB. Power gain in dB = 10log10(Poutput/Pinput)

Example: The voltage gain of an amplifier whose input

is 0.2 mV and whose output is 0.5 V is
20log10(0.5/0.2x10-3) = 68 dB.
EE40 Fall Slide 227 Prof. Chang-Hasnain EE40 Fall Slide 228 Prof. Chang-Hasnain
2006 2006
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Bode Plot Frequency Response

• Plot of magnitude of transfer function vs. • The shape of the frequency response of the complex
frequency ratio of phasors VOUT/VIN is a convenient means of
classifying a circuit behavior and identifying key
– Both x and y scale are in log scale parameters.
– Y scale in dB
• Log Frequency Scale Break point
VOUT Break point VOUT
– Decade Ratio of higher to lower frequency VIN Gain VIN Gain
= 10
Low Pass High Pass
– Octave Ratio of higher to lower frequency
=2 Frequency Frequency

FYI: These are log ratio vs log frequency plots

EE40 Fall Slide 229 Prof. Chang-Hasnain EE40 Fall Slide 230 Prof. Chang-Hasnain
2006 2006

Example Circuit Break Point Values

R2
• When dealing with resonant circuits it is convenient
to refer to the frequency difference between points at
+
+

VIN
+
AVT C which the power from the circuit is half that at the
+

VOUT
R1 VT −
peak of resonance.
• Such frequencies are known as “half-power
frequencies”, and the power output there referred to
VOUT A = 100 the peak power (at the resonant frequency) is
TransferFunction =
VIN • 10log10(Phalf-power/Presonance) = 10log10(1/2) = -3 dB.
R1 = 100,000 Ohms
VOUT AZ c R2 = 1000 Ohms
=
VIN Z R + Zc
C = 10 uF
VOUT A(1 / jwC ) A
= =
VIN R2 + 1 / jωC ) (1 + jωR2C )

EE40 Fall Slide 231 Prof. Chang-Hasnain EE40 Fall Slide 232 Prof. Chang-Hasnain
2006 2006
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Example: Circuit in Slide #3 Magnitude Example: Circuit in Slide #3 Phase

Magnitude

Phase
VOUT A
=
A = 100 VIN (1 + jωR2C ) A = 100
R2 = 1000 Ohms 180 R2 = 1000 Ohms
C = 10 uF 90 C = 10 uF
1000
A wp = 1/(R2C) = 100 0
100 VV OUT
=
A
100 1000
IN (1 + jωR2C )
100 100 1 10 Radian
Actual value = | 1 + j | = -90 Frequency
10 2
-180 -45o
1 Actual value is
1 10 100 1000 Radian
0.1 Frequency 100∠0 100∠0
Phase{ } = Phase{ } = 0 − 45 = −45
|1+ j | 2∠45

EE40 Fall Slide 233 Prof. Chang-Hasnain EE40 Fall Slide 234 Prof. Chang-Hasnain
2006 2006

Bode Plot: Label as dB Transfer Function

VOUT
=
A • Transfer function is a function of frequency
VIN (1 + jωR2C )
Magnitude in dB

A = 100 – Complex quantity

R2 = 1000 Ohms – Both magnitude and phase are function of
C = 100 uF frequency
60
A wp = 1/(R2C) = 100 Two Port
40 Vin filter network
Vout

20

0 Vout Vout
1 10 100 1000 Radian
H( f ) = = ∠ (θ out − θin )
-20
Vin Vin
Frequency
H(f) = H ( f )∠θ
Note: Magnitude in dB = 20 log10(VOUT/VIN)
EE40 Fall Slide 235 Prof. Chang-Hasnain EE40 Fall Slide 236 Prof. Chang-Hasnain
2006 2006
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Filters Common Filter Transfer Function vs. Freq

• Circuit designed to retain a certain

H( f ) H( f )
frequency range and discard others
Low-pass: pass low frequencies and reject high
frequencies Low Pass High Pass
High-pass: pass high frequencies and reject low Frequency Frequency
frequencies
H( f ) H( f )
Band-pass: pass some particular range of
frequencies, reject other frequencies outside
that band Band Pass Band Reject
Notch: reject a range of frequencies and pass Frequency Frequency
all other frequencies

EE40 Fall Slide 237 Prof. Chang-Hasnain EE40 Fall Slide 238 Prof. Chang-Hasnain
2006 2006

First-Order Lowpass Filter First-Order Highpass Filter

VC 1 ( jωC ) 1 1
∠ − tan −1 (ω RC )
VR R jω RC (ω RC ) ∠ π − tan −1 ω RC
H(f) = = = = H(f) = = = = ( )
V 1 ( jωC ) + R 1 + jω RC 1 + (ω RC )
2 V 1 ( jωC ) + R 1 + jω RC 1 + (ω RC )
2 2

1 1 f
Let ωB = and f B =
RC 2π RC fB π f
H( f ) = ,θ = − tan −1
H(f) = H ( f )∠θ f
2 2 fB
1+
1 −1 f fB VR
H( f ) = , θ = − tan
f
2 fB
1+ 1
fB R H ( fB ) = = 2−1/ 2 R
+ + 2 + +
1 V C VC V C VC
H ( fB ) = = 2−1/ 2 H ( fB ) 1
2 - - 20 log10 = 20(− ) log10 2 = −3 dB - -
H (0) 2
H ( fB ) 1
20 log10 = 20(− ) log10 2 = −3 dB
H (0) 2
EE40 Fall Slide 239 Prof. Chang-Hasnain EE40 Fall Slide 240 Prof. Chang-Hasnain
2006 2006
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First-Order Lowpass Filter First-Order Highpass Filter

VR 1 1 ωL jω L ωL
H(f) = = = ∠ − tan −1 VL π ωL
V jω L ωL
2 R H(f) = = R = R ∠ − tan −1
+1 1+ jω L
R V +1 ωL
2 2 R
R 1+
R R
R R
Let ωB = and f B = R R
L 2π L Let ωB = and f B =
H(f) = H ( f )∠θ L 2π L
VR H(f) = H ( f )∠θ VR
1 f
H( f ) = , θ = − tan −1 f
2 fB
f
1+ R fB π f R
fB + H( f ) = ,θ = − tan −1 +
+ 2 2 fB +
V L VL f V L VL
1+
- - fB - -

EE40 Fall Slide 241 Prof. Chang-Hasnain EE40 Fall Slide 242 Prof. Chang-Hasnain
2006 2006

Change of Voltage or Current with

First-Order Filter Circuits A Change of Frequency

One may wish to specify the change of a quantity

High Pass Low Pass such as the output voltage of a filter when the
frequency changes by a factor of 2 (an octave) or 10
(a decade).
VS + R Low VS + R High
– – L For example, a single-stage RC low-pass filter has at
C Pass Pass
frequencies above ω = 1/RC an output that changes
at the rate -20dB per decade.

HR = R / (R + 1/jωC) HR = R / (R + jωL)
HC = (1/jωC) / (R + 1/jωC) HL = jωL / (R + jωL)

EE40 Fall Slide 243 Prof. Chang-Hasnain EE40 Fall Slide 244 Prof. Chang-Hasnain
2006 2006
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High-frequency asymptote of Lowpass filter Low-frequency asymptote of Highpass filter

The high frequency asymptote of magnitude As f → 0

Bode plot assumes -20dB/decade slope f
fB f
As f → ∞ H( f ) = →
f
2 fB
−1 1+
f fB
H( f ) = f →∞
fB
H (10 f B )
20 log10 = −20dB H ( fB )
H ( fB ) 20 log10 = 20dB
H (0.1 f B )

The low frequency asymptote of magnitude

Bode plot assumes 20dB/decade slope
EE40 Fall Slide 245 Prof. Chang-Hasnain EE40 Fall Slide 246 Prof. Chang-Hasnain
2006 2006

Second-Order Filter Circuits Series Resonance

+
VIN
VOUT
−

Voltage divider
Band Pass
Z = R + 1/jωC + jωL VOUT
=
ZR Resonance quality factor
VIN Z L + Z R + ZC
ωL
R HBP = R / Z Substitute branch elements Q=
Low C R
VOUT R
=
VS + Pass Band HLP = (1/jωC) / Z VIN jω L + R + 1 / jω C
Ratio of reactance to resistance
–
Reject
High L HHP = jωL / Z Arrange in resonance form Closely related to number
Pass VOUT R of round trip cycles before
HBR = HLP + HHP VIN
=
R + j (ωL − 1 / ωC )
1/e decay.
Bandwidth is f0/Q
Maximum when w2 = 1/(LC)

EE40 Fall Slide 247 Prof. Chang-Hasnain EE40 Fall Slide 248 Prof. Chang-Hasnain
2006 2006
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Parallel Resonance Chapter 14

• OUTLINE

+
IIN
VOUT

– Op-Amp from 2-Port Blocks

Admittance
– Op-Amp Model and its Idealization
VOUT =
IS Resonance quality factor
YL + YR + YC – Negative Feedback for Stability
ωL
Substitute branch elements Q=
R – Components around Op-Amp define the
VOUT =
IS
Ratio of reactance to resistance Circuit Function
1 + 1 + jwC
j ωL R

Closely related to number

Arrange in resonance form • Reading
of round trip cycles before
IS
VOUT =
1 + j (ωC − 1 )
1/e decay. – Chap 14
R ωL
Bandwidth is f0/Q
Maximum = IS/R when w2 = 1/(LC)
EE40 Fall Slide 249 Prof. Chang-Hasnain EE40 Fall Slide 250 Prof. Chang-Hasnain
2006 2006

The Operational Amplifier High Quality Dependent Source In an Amplifier

• The operational amplifier (“op amp”) is a
basic building block used in analog circuits.
– Its behavior is modeled using a dependent source.
– When combined with resistors, capacitors, and Differential Amplifier
inductors, it can perform various useful functions: V0 = A( V+ − V− ) Circuit Model in linear region
• amplification/scaling of an input signal V+ + V0
• sign changing (inversion) of an input signal A + + +
V− − Ri V1 AV1 V0
• addition of multiple input signals − − −
• subtraction of one input signal from another
• integration (over time) of an input signal V0 depends only on input (V+ − V-)
• differentiation (with respect to time) of an input signal
• analog filtering
See the utility of this: this Model when used correctly
• nonlinear functions like exponential, log, sqrt, etc
mimics the behavior of an amplifier but omits the
– Isolate input from output; allow cascading complication of the many many transistors and other
components.
EE40 Fall Slide 251 Prof. Chang-Hasnain EE40 Fall Slide 252 Prof. Chang-Hasnain
2006 2006
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Op Amp Terminals Model for Internal Operation

• 3 signal terminals: 2 inputs and 1 output • A is differential gain or • Circuit Model
open loop gain
• IC op amps have 2 additional terminals for DC
• Ideal op amp
power supplies
A→∞ +
• Common-mode signal= (v1+v2)/2 Ri → ∞ i1
• Differential signal = v1-v2 v1
Ro = 0 Ro io
V+ – Common mode gain = 0 Ri vo
positive power supply
( v1 + v2 ) i2
Inverting input v2 vcm = , vd = v1 − v2 v2 +
- _ –
v0 output 2 A(v1–v2)
Non-inverting input v1 + vo = Acm vcm + Ad vd
Since vo = A(v1 − v2 ) , Acm = 0
V – negative power supply

EE40 Fall Slide 253 Prof. Chang-Hasnain EE40 Fall Slide 254 Prof. Chang-Hasnain
2006 2006

Model and Feedback Op-Amp and Use of Feedback

• Negative feedback • Circuit Model A very high-gain differential amplifier can function in an extremely linear
– connecting the output port to fashion as an operational amplifier by using negative feedback.
the negative input (port 2)
R1 R2 R1 R2
• Positive feedback
– connecting the output port to
+
the positive input (port 1)
i1 − - + +
v1 VIN +
V0 Ri V1 AV1 V0
• Input impedance: R Ro io − −
VIN +
looking into the input Ri vo Summing Point
terminals i2 Circuit Model
v2 +
• Output impedance: _ – Negative feedback
Impedance in series with A(v1–v2) Hambley Example pp. 644 for Power Steering
the output terminals
We can show that that for A → ∞ and Ri → ∞,
R1 + R 2
V 0 ≅ V IN ⋅
R1
EE40 Fall Slide 255 Prof. Chang-Hasnain EE40 Fall Slide 256 Prof. Chang-Hasnain
2006 2006
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Summing-Point Constraint Ideal Op-Amp Analysis Technique

• Check if under negative feedback Applies only when Negative Feedback is present in circuit!
– Small vi result in large vo
– Output vo is connected to the inverting input to reduce Assumption 1: The potential between the op-amp input terminals, v(+) –
vi v(-), equals zero.
– Resulting in vi=0
Assumption 2: The currents flowing into the op-amp’s two input
• Summing-point constraint terminals both equal zero.
– v1= v2
No Potential Difference
– i1 = i2 =0 No Currents R1 R2
• Virtual short circuit
– Not only voltage drop is 0 (which is short circuit), input − V0
current is 0 VIN +
– This is different from short circuit, hence called EXAMPLE
“virtual” short circuit.

EE40 Fall Slide 257 Prof. Chang-Hasnain EE40 Fall Slide 258 Prof. Chang-Hasnain
2006 2006

Ideal Op-Analysis: Non-Inverting Amplifier Non-Inverting Amplifier

Yes Negative Feedback is present in this circuit! • Ideal voltage amplifier vo

Closed loop gain = Av =
Assumption 1: The potential between the op-amp input terminals, v(+) – vin
v(-), equals zero. + v0 v1 = v2 = vin , i1 = i2 = 0
Assumption 2: The currents flowing into the op-amp’s two input v2 _ Use KCL At Node 2.
terminals both equal zero. vin +-
RL (v0 − v2 ) (v2 − 0)
KCL with currents in only two branches
2 i= =
R2 R2 R1
R1 R2 v v −v
in in out R1
+ =0 vo ( R1 + R2 )
R1 R2 A= =
− vin R1
V0 R + R2
VIN + vout = 1 vin vin
EXAMPLE R1 Input impedance = →∞
i
VIN appears here Non-inverting Amplifier

EE40 Fall Slide 259 Prof. Chang-Hasnain EE40 Fall Slide 260 Prof. Chang-Hasnain
2006 2006
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Ideal Op-Amp Analysis: Inverting Amplifier Inverting Amplifier

vo
Yes Negative Feedback is present in circuit! • Negative feedback Closed loop gain = Av =
R2 vin
checked
R1 v1 = v2 = 0 , i1 = i2 = 0
I2 • Use summing-point Use KCL At Node 2.
constraint (vin − v2 ) (vout − v2 )
VIN
RL V OUT R2 i= =
-VR 2 R1 R2
Voltage is VR
R1 v R2 vo
i 2 _
vo = −
Only two VR − VIN VR − VOUT v0 R1
+ =0
currents R1 R2 + vin
for KCL vin +- v1 Input impedance = = R1
RL i
R2
VOUT = VR − (Vin − VR )
R1
Inverting Amplifier with reference voltage Ideal voltage source – independent of load resistor
EE40 Fall Slide 261 Prof. Chang-Hasnain EE40 Fall Slide 262 Prof. Chang-Hasnain
2006 2006

Voltage Follower Example 1

2 i5 R
+ v0
i4
R v2 i 2 _
v2 v0
vin +
_
- RL +
i3 v1 i 1
R RL • Switch is open
vin +-

R2 = 0
v1 = v2 , i1 = 0 → i3 = 0
R1 → ∞
(vin − v1 )
(v − v ) (v − 0) i3 = → v1 = v2 = vin → i4 = 0 → i5 = 0
i= 0 2 = 2 R
R2 R1 (v − v )
i 5 = 0 2 → v0 = v2 = vin
vo ( R1 + R2 ) R R
A= = = 1+ 2 = 1 vo
vin R1 R1 A= = 1 , Rin → ∞
vin
EE40 Fall Slide 263 Prof. Chang-Hasnain EE40 Fall Slide 264 Prof. Chang-Hasnain
2006 2006
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Example 1 Example 2
• Switch is closed • Design an analog front end v1
+
circuit to an instrument system vin c v0
_
– Requires to work with 3 full-scale of v2
2 i5 R v1 = v2 = 0 , i1 = 0 → i3 = 0 input signals (by manual switch): vb b RL
2
0 ±1, 0 ±10, 0 ±100 V R2
i4
R v2 i 2 _ (v − v ) (v − v ) va a
v0 i4 = in 2 = i 5 = − 0 2 – For each input range, the output R1
R R needs to be 0 ±10 V
+
i3 v1 i 1 v0 = −vin – The input resistance is 1MΩ
R RL
vin +- vo R2
A= = −1 , Rin = R vo = (1 + )v1
vin 2 R1
v1 = vin Switch at c
Ra + Rb
v1 = vin Switch at b
Ra + Rb + Rc
Ra
v1 = vin Switch at a
Ra + Rb + Rc
EE40 Fall Slide 265 Prof. Chang-Hasnain EE40 Fall Slide 266 Prof. Chang-Hasnain
2006 2006

Example 2 (cont’d) Summing Amplifier

Rin = Ra + Rb + Rc = 1M Ω v1 R1

+
-
R2
Max Av = 10 = (1 + ) Switch at c R0
R1

+
-
Ra + Rb R Ra + Rb v2 R2
Av = 1 = (1 + 2 ) Switch at b ∴ = 0.1
Ra + Rb + Rc R1 Ra + Rb + Rc _ v0

+
-
Ra R Ra v3 R3
Av = 0.1 = (1 + 2 ) Switch at a ∴ = 0.01 +
Ra + Rb + Rc R1 Ra + Rb + Rc
∴ Ra = 10k Ω, Rb = 90k Ω, Rc = 900k Ω
R2 = 9 R1

EE40 Fall Slide 267 Prof. Chang-Hasnain EE40 Fall Slide 268 Prof. Chang-Hasnain
2006 2006
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Difference Amplifier Integrator

• Want v = K v dt
o in

R2 • What is the difference

v1 between:
R1
_ v0
+
-

+ R
+
-

R3 + +
v2 vin C V0
R4
- -

EE40 Fall Slide 269 Prof. Chang-Hasnain EE40 Fall Slide 270 Prof. Chang-Hasnain
2006 2006

Differentiator Bridge Amplifier

• Want
vx
R0(1+ε)
R0

_ v0
+
R +
vin -
Ra
C Ra
vx
_ v0
+
vin +-

EE40 Fall Slide 271 Prof. Chang-Hasnain EE40 Fall Slide 272 Prof. Chang-Hasnain
2006 2006
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Application: Digital-to-Analog Conversion Characteristic of 4-Bit DAC

A DAC can be used to convert the digital representation Binary Analog 8
number output

Analog Output (V)

of an audio signal into an analog voltage that is then (volts) 7
used to drive speakers -- so that you can hear it! 0000 0
0001 .5 6
“Weighted-adder D/A converter” 0010 1
10K 0011 1.5 5
S4
0100 2
20K 0101 2.5
4
S3
-
S2
40K 5K
0110
0111
3
3.5
3
8V
+
80K −
−
1000 4 2
+ V0 1001 4.5
+ 1010 5 1
S1
1011 5.5
4-Bit D/A 1100 6 0
S1 closed if LSB =1 1101 6.5 0 2 4 6 8 10 12 14 16
S2 " if next bit = 1 1110 7 0000
1111 7.5 0001 1000 1111
(Transistors are used S3 " if " " = 1 0100
as electronic switches) S4 " if MSB = 1 Digital Input
MSB LSB
EE40 Fall Slide 273 Prof. Chang-Hasnain EE40 Fall Slide 274 Prof. Chang-Hasnain
2006 2006

Active Filter Active Filter Example

• Contain few components

• Transfer function that is insensitive to C
component tolerance
v3
• Easily adjusted v1 +
v0

• Require a small spread of components

_
R R
vin + (k-1)Rf
- v2
values C

• Allow a wide range of useful transfer Rf

functions

EE40 Fall Slide 275 Prof. Chang-Hasnain EE40 Fall Slide 276 Prof. Chang-Hasnain
2006 2006
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Active Filter Solution Cascaded Active Filter Example

v
v1 = v 2 = o
k
( v3 − v1 )
Use KC L At Node A = jω C v1
R
( vin − v3 ) ( v − v1 ) C
Use KC L At Node B = jω C ( v 3 − v o ) + 3 C2
R R
vo k v3 v1
= + v0’ v3’ v1’
vin 1 − ω 2 R 2 C 2 + jω RC (3 − k ) R
+ v0
R _ R
Let ω B = 1 / RC + v2 R2 _
vin - (k-1)Rf 2 v2’
v k C (k2 -1)Rf
H (ω ) = o = C2
vin ω2
2
ω2 Rf
1− + (3 − k ) 2 Rf
ωB2 ωB2
ω = 0, H (ω ) = k DC gain
k
ω = ω B , H (ω ) =
3−k
k
ω >> ω B , H (ω ) = 2
ω −2
ω
ωB2
20 log H (ω ) decays at a rate of 40 dB / decade
EE40 Fall Slide 277 Prof. Chang-Hasnain EE40 Fall Slide 278 Prof. Chang-Hasnain
2006 2006

Cascaded Active Filter Solution Chapter 10

vo
=
k2 k • OUTLINE
vin 1 − ω 2 R2 2C2 2 + jω R2C2 (3 − k2 ) 1 − ω 2 R 2C 2 + jω RC (3 − k ) – Diode Current and Equation
Let ωB = 1/ RC , ωB 2 = 1/ R2C2 – Some Interesting Circuit Applications
vo k2 k – Load Line Analysis
H (ω ) = =
vin ω2
2
ω2 ω2
2
ω2 – Solar Cells, Detectors, Zener Diodes
1− + (3 − k2 ) 2 1− + (3 − k ) 2
ωB 2 2 ωB 2 2 ωB 2 ωB 2 – Circuit Analysis with Diodes
ω = 0, H (ω ) = k2 k DC gain – Half-wave Rectifier
k2 k – Clamps and Voltage Doublers using Capacitors
ω = ωB , H (ω ) =
3 − k2 3 − k • Reading
k2 k −4
ω >> ωB , H (ω ) = ω – Hambley 10.1-10.8
ω4
– Supplementary Notes Chapter 2
ωB 2 2ωB 2
20 log H (ω ) decays at a rate of 80dB / decade
EE40 Fall Slide 279 Prof. Chang-Hasnain EE40 Fall Slide 280 Prof. Chang-Hasnain
2006 2006
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I-V Characteristics Diode Physical Behavior and Equation

I Schematic Device Symbol

In forward bias (+ on p-side) we current increases I
rapidly with V N P
have almost unlimited flow
type type I
(very low resistance).
Qualitatively, the I-V VF − V+
− V+
characteristics must look like:
Qualitative I-V characteristics: Quantitative I-V characteristics:
I V positive,
I easy I = I 0 (e qV kT − 1)
conduction
In which kT/q is 0.026V and IO is a
In reverse bias (+ on n-side) constant depending on diode area.
almost no current can flow. Typical values: 10-12 to 10-16 A.
VF V
Qualitatively, the I-V Interestingly, the graph of this
characteristics must look like: The current is close V negative,
equation looks just like the figure to
to zero for any no
the left.
negative bias conduction
A non-ideality factor n times kT/q is often included.
EE40 Fall Slide 281 Prof. Chang-Hasnain EE40 Fall Slide 282 Prof. Chang-Hasnain
2006 2006

The pn Junction I vs. V Equation Diode Ideal (Perfect Rectifier) Model

The equation I = I 0 exp(qV kT − 1)
I-V characteristic of PN junctions Simple “Perfect Rectifier” Model
In EECS 105, 130, and other courses you will learn why the I vs. V is graphed below for I 0 = 10 −15 A
relationship for PN junctions is of the form 10 If we can ignore the small forward-
Current
in mA 8 bias voltage drop of a diode, a
simple effective model is the
I = I 0 (eqV kT − 1)
6
“perfect rectifier,” whose I-V
4
characteristic is given below:
2 Forward
where I0 is a constant proportional to junction area and depending Voltage in V
on doping in P and N regions, q = electronic charge = 1.6 × 10 −19 , 0 I
-5 0 5 10
k is Boltzman constant, and T is absolute temperature.
KT q = 0.026V at300°K , a typical value for I0 is 10 −12 − 10 −15 A The characteristic is described as Reverse bias Forward bias
a “rectifier” – that is, a device that I ≅ 0, any V < 0 V ≅ 0, any I > 0
permits current to pass in only one V
direction. (The hydraulic analog is
We note that in forward bias, I increases exponentially and is in
a “check value”.) Hence the
the µA-mA range for voltages typically in the range of 0.6-0.8V. A perfect rectifier
symbol: I
In reverse bias, the current is essentially zero.

− V+
EE40 Fall Slide 283 Prof. Chang-Hasnain EE40 Fall Slide 284 Prof. Chang-Hasnain
2006 2006
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Diode Large-Signal Model (0.7 V Drop) Rectifier Circuit

Assume the ideal
400
- 0.7+ I VS(t)
(microamp)
(perfect rectifier)
Current

300
model.
200
100 The Large-Signal
0 − V+ Diode Model +
-5 -3 -1 1 VS(t) +
− VR(t)
forward bias (V)
− t
Improved “Large-Signal Diode” Model: I
If we choose not to ignore the small
Reverse bias Forward bias
forward-bias voltage drop of a I ≅ 0, any V < 0 V ≅ 0.7, any I > 0 VR(t)
diode, it is a very good
approximation to regard the voltage V
drop in forward bias as a constant, 0.7
about 0.7V. the “Large signal “rectified” version of
model” results. input waveform
t
EE40 Fall Slide 285 Prof. Chang-Hasnain EE40 Fall Slide 286 Prof. Chang-Hasnain
2006 2006

Peak Detector Circuit pn-Junction Reverse Breakdown

Assume the ideal (perfect rectifier) model. • As the reverse bias voltage increases, the peak electric
field in the depletion region increases. When the electric
Vi(t) field exceeds a critical value (Ecrit ≅ 2x105 V/cm), the
reverse current shows a dramatic increase:
+
+ Vi
+ C
Vi(t) − VC(t)
reverse (leakage) current ID (A)
−
− forward current
t breakdown voltage VBD
VD (V)
VC(t) VC
Key Point:
The capacitor charges
due to one way current
behavior of the diode.

EE40 Fall Slide 287 Prof. Chang-Hasnain EE40 Fall Slide 288 Prof. Chang-Hasnain
2006 2006
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Zener Diode Load Line Analysis Method

A Zener diode is designed to operate in the breakdown mode. 1. Graph the I-V relationships for the non-linear
element and for the rest of the circuit
ID (A)
reverse (leakage) current
2. The operating point of the circuit is found from
forward
current the intersection of these two curves.
breakdown voltage VBD
VD (V) I
RTh I

Example: + VTh/RTh operating point

t +
R VTh − V
+ + – V
integrated VTh
vs(t) vo(t) circuit
– VBD = 15V – $ *
,
EE40 Fall Slide 289 Prof. Chang-Hasnain EE40 Fall Slide 290 Prof. Chang-Hasnain
2006 2006

Solar cell: Example of simple PN junction Photovoltaic (Solar) Cell

• What is a solar cell?
– Device that converts I D = I S (e qVD kT
− 1) − I optical
sunlight into electricity

• How does it work? ID (A)

– In simple configuration, it is a
diode made of PN junction in the dark
– Incident light is absorbed by
VD (V)
material
– Creates electron-hole pairs that
transport through the material with incident light
through Operating point
• Diffusion (concentration gradient) The load line a simple resistor.
• Drift (due to electric field)
PN Junction Diode
EE40 Fall Slide 291 Prof. Chang-Hasnain EE40 Fall Slide 292 Prof. Chang-Hasnain
2006 2006
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I-V characteristics of the device Example 2: Photodiode

• I-V characteristics of a PN • An intrinsic region is placed
junction is given by between the p-type and n-type
eV
regions
I = I S exp( ) −1 − I L
kT Voc Wj ≅ Wi-region, so that most of the
electron-hole pairs are generated
where Is is the saturation intensity
in the depletion region
depending on band gap and doping
(Vm, Im) faster response time
of the material and IL is the Isc
photocurrent generated due to light (~10 GHz operation)
ID (A)

• Efficiency is defined as

Voc - Open circuit voltage

in the dark
I m .Vm FF *Voc * I sc
η= =
Light Intensity Light Intensity Isc - Short circuit current VD (V)
Imp , Vmp- Current and voltage
operating point
FF is the Fill Factor at maximum power
with incident light
EE40 Fall Slide 293 Prof. Chang-Hasnain EE40 Fall Slide 294 Prof. Chang-Hasnain
2006 2006

Photodetector Circuit Using Load Line Ideal Diode Model of PN Diode

RTh I I Circuit symbol I-V characteristic Switch model
ID ID (A) ID
+ operating
−
points under
As light +
VTh +
intensity +
V different light increases.
conditions. Why? VD VD
– forward bias
–
reverse bias
As light shines on the photodiode, carriers V – VD (V)
are generated by absorption. These excess V
Th
carriers are swept by the electric field at the
junction creating drift current, which is same VTh/RTh • An ideal diode passes current only in one direction.
direction as the reverse bias current and
hence negative current. The current is • An ideal diode has the following properties:
proportional to light intensity and hence can
provide a direct measurement of light • when ID > 0, VD = 0
intensity photodetector. - . &
• when VD < 0, ID = 0 .
- What happens when Rth is too large? & .
- Why use Vth?
EE40 Fall Slide 295 Prof. Chang-Hasnain EE40 Fall Slide 296 Prof. Chang-Hasnain
2006 2006
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Large-Signal Diode Model Diode: Large Signal Model

Circuit symbol I-V characteristic Switch model • Use piece-wise linear model
ID ID (A) ID
+ +
+ VDon
−
VD VD
forward bias
reverse bias
– VD (V) –
VDon

/ 0 VDon ≅ "1 2

RULE 1: When ID > 0, VD = VDon

- . & & !
RULE 2: When VD < VDon, ID = 0
.
& .

EE40 Fall Slide 297 Prof. Chang-Hasnain EE40 Fall Slide 298 Prof. Chang-Hasnain
2006 2006

How to Analyze Circuits with Diodes Diode Logic: AND Gate

A diode has only two states: • Diodes can be used to perform logic functions:
• forward biased: ID > 0, VD = 0 V (or 0.7 V)
AND gate
• reverse biased: ID = 0, VD < 0 V (or 0.7 V) & ! ! Inputs A and B vary between 0
. ) 3 !
Volts (“low”) and Vcc (“high”)
Procedure: Vcc Between what voltage levels
1. Guess the state(s) of the diode(s) does C vary?
2. Check to see if KCL and KVL are obeyed.
RAND VOUT

3. If KCL and KVL are not obeyed, refine your guess 5

4. Repeat steps 1-3 until KCL and KVL are obeyed. A C

EOC

Example: If vs(t) > 0 V, diode is forward biased B Slope =1

Shift 0.7V Up

+ (else KVL is disobeyed – try it)

vs(t) + vR(t) 0
− If vs(t) < 0 V, diode is reverse biased 0 5 VIN

– (else KVL is disobeyed – try it)

EE40 Fall Slide 299 Prof. Chang-Hasnain EE40 Fall Slide 300 Prof. Chang-Hasnain
2006 2006
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Diode Logic: OR Gate Diode Logic: Incompatibility and Decay

• Diodes can be used to perform logic functions: • Diode Only Gates are Basically Incompatible:
OR gate AND gate OR gate
& ! ! & ! ! & ! !
Inputs A and B vary between 0 . #) 3 ! . ) 3 ! . #) 3 !
Volts (“low”) and Vcc (“high”) Vcc
Between what voltage levels
does C vary? A A
VOUT RAND
5 B C B COR
EOC ROR A CAND ROR
Slope =1
Shift 0.7V Down B
CAND High want RAND >> ROR
0
0 0.7V 5 VIN CAND Low want RAND << ROR
Signal Decays with each stage (Not regenerative)

EE40 Fall Slide 301 Prof. Chang-Hasnain EE40 Fall Slide 302 Prof. Chang-Hasnain
2006 2006

Device Isolation using pn Junctions Why are pn Junctions Important for ICs?
regions of n-type Si
• The basic building block in digital ICs is the
MOS transistor, whose structure contains
reverse-biased diodes.
n n n n n
– pn junctions are important for electrical isolation of
p-type Si transistors located next to each other at the
surface of a Si wafer.

No current flows if voltages are applied between n-type – The junction capacitance of these diodes can limit
regions, because two pn junctions are “back-to-back” the performance (operating speed) of digital
circuits
n-region n-region

p-region
=> n-type regions isolated in p-type substrate and vice versa
EE40 Fall Slide 303 Prof. Chang-Hasnain EE40 Fall Slide 304 Prof. Chang-Hasnain
2006 2006
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Power Conversion Circuits Rectifier Equivalent circuit

• Converting AC to DC
• Potential applications: Charging a battery V>0.6V, diode = short circuit
Vo=VI-0.6
V<0.6V, diode = open circuit
Vo=0
VI=Vm sin (ωt) R Vo

EE40 Fall Slide 305 Prof. Chang-Hasnain EE40 Fall Slide 306 Prof. Chang-Hasnain
2006 2006

Half-wave Rectifier Circuits Half-Wave Rectifier

• Adding a capacitor: what does it do?

+
Vm sin (ωt)
C R V0

-
Current
charging
up
capacitor

EE40 Fall Slide 307 Prof. Chang-Hasnain EE40 Fall Slide 308 Prof. Chang-Hasnain
2006 2006
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Level Shift Circuit Voltage Doubler Circuit

- VC1 + - VC1 +

VIN
+

+
+

+
C1 C1

+ VC21 -
VIN VOUT VIN VIN C2 VOUT
R1 R1 VOUT R2

- - -
- - -
t

VOUT
Level Shift Peak Detect

The final output is the peak to peak voltage of the input.

Once the capacitor is charged by the negative most voltage
the rest of the signal is shifted up by that amount.
EE40 Fall Slide 309 Prof. Chang-Hasnain EE40 Fall Slide 310 Prof. Chang-Hasnain
2006 2006

Week 12 Conductors, Insulators and Semiconductors

• OUTLINE • Solids with “free electrons” – that is electrons not
– Basic Semiconductor Materials directly involved in the inter-atomic bonding- are
– n and p doping
the familiar metals (Cu, Al, Fe, Au, etc).
– Bandgap • Solids with no free electrons are the familiar
– Gauss’s Law
insulators (glass, quartz crystals, ceramics, etc.)
– Poisson Equation • Silicon is an insulator, but at higher
temperatures some of the bonding electrons can
– Depletion approximation
get free and make it a little conducting – hence
– Diode I-V characteristics the term “semiconductor”
– Lasers and LEDs
• Pure silicon is a poor conductor (and a poor
– Solar Cells insulator). It has 4 valence electrons, all of
• Reading which are needed to bond with nearest
– Supplementary Notes Chap 3 neighbors. No free electrons.
EE40 Fall Slide 311 Prof. Chang-Hasnain EE40 Fall Slide 312 Prof. Chang-Hasnain
2006 2006
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The Periodic Table Electronic Bonds in Silicon

III IV V
2-D picture of perfect crystal of pure silicon; double line is a Si-Si
bond with each line representing an electron

Si ion
(charge
+4 q)

Two electrons in each bond

Actual structure is 3-dimensional tetrahedral- just like carbon

bonding in organic and inorganic materials.

Essentially no free electrons, and no conduction - insulator

EE40 Fall Slide 313 Prof. Chang-Hasnain EE40 Fall Slide 314 Prof. Chang-Hasnain
2006 2006

How to get conduction in Si? Doping Silicon with Donors (n-type)

We must either:
Donors donate mobile electrons (and thus “n-type” silicon)
1) Chemically modify the Si to produce free carriers (permanent) or Example: add arsenic (As) to the silicon crystal:
2) Electrically “induce” them by the field effect (switchable)

For the first approach controlled impurities, “dopants”, are added to

Si: Mobile electron
donated by As ion
Add group V elements (5 bonding electrons vs four for Si),
such as phosphorus or arsenic As
(Extra electrons produce “free electrons” for conduction.)

or

Add group III elements (3 bonding electrons), such as boron

Immobile (stuck) positively charged arsenic ion after 5th electron left
Deficiency of electrons results in “free holes”
The extra electron with As, “breaks free” and becomes a free
electron for conduction

EE40 Fall Slide 315 Prof. Chang-Hasnain EE40 Fall Slide 316 Prof. Chang-Hasnain
2006 2006
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Doping with Acceptors (p-type) Doping

Group III element (boron, typically) is added to the crystal

• Typical doping densities:
Immobile (stuck) negative boron ion after accepting electron from neighboring bond
1016~1019 cm-3
• Atomic density for Si: 5 x
1022 atoms/cm3
Mobile hole con- • 1018 cm-3 is 1 in 50,000
tributed by B ion
and later path – two persons in entire
B
Berkeley wearing a green
hat
• P-n junction effect is like

The “hole” which is a missing bonding electron, breaks free from

the B acceptor and becomes a roaming positive charge, free to
carry current in the semiconductor. It is positively charged.
EE40 Fall Slide 317 Prof. Chang-Hasnain EE40 Fall Slide 318 Prof. Chang-Hasnain
2006 2006

Shockley’s Parking Garage Analogy for Conduction in Si Shockley’s Parking Garage Analogy for Conduction in Si

Two-story parking garage on a hill: Two-story parking garage on a hill:

If the lower floor is full and top one is empty, no traffic is If one car is moved upstairs, it can move AND THE HOLE
possible. Analog of an insulator. All electrons are ON THE LOWER FLOOR CAN MOVE. Conduction is
locked up. possible. Analog to warmed-up semiconductor. Some
electrons get free (and leave “holes” behind).

EE40 Fall Slide 319 Prof. Chang-Hasnain EE40 Fall Slide 320 Prof. Chang-Hasnain
2006 2006
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Shockley’s Parking Garage Analogy for Conduction in Si

Shockley’s Parking Garage Analogy for Conduction in Si

Two-story parking garage on a hill: Two-story parking garage on a hill:

If an extra car is “donated” to the upper floor, it can move. If a car is removed from the lower floor, it leaves a HOLE
Conduction is possible. Analog to N-type semiconductor. which can move. Conduction is possible. Analog to P-type
(An electron donor is added to the crystal, creating free semiconductor. (Acceptors are added to the crystal,
electrons). “consuming” bonding electrons,creating free holes).

EE40 Fall Slide 321 Prof. Chang-Hasnain EE40 Fall Slide 322 Prof. Chang-Hasnain
2006 2006

Summary of n- and p-type silicon Junctions of n- and p-type Regions

p-n junctions form the essential basis of all semiconductor devices.

Pure silicon is an insulator. At high temperatures it conducts
weakly. A silicon chip may have 108 to 109 p-n junctions today.
How do they behave*? What happens to the electrons and holes?
If we add an impurity with extra electrons (e.g. arsenic,
What is the electrical circuit model for such junctions?
phosphorus) these extra electrons are set free and we have a
pretty good conductor (n-type silicon). n and p regions are brought into contact :

If we add an impurity with a deficit of electrons (e.g. boron) then aluminum ? aluminum
bonding electrons are missing (holes), and the resulting holes
can move around … again a pretty good conductor (p-type wire
silicon) n p

Now what is really interesting is when we join n-type and p-type

silicon, that is make a pn junction. It has interesting electrical
properties.
*Note that the textbook has a very good explanation.

EE40 Fall Slide 323 Prof. Chang-Hasnain EE40 Fall Slide 324 Prof. Chang-Hasnain
2006 2006
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The pn Junction Diode Depletion Region Approximation

Schematic diagram Circuit symbol • When the junction is first formed, mobile carriers diffuse
across the junction (due to the concentration gradients)
ID
p-type n-type – Holes diffuse from the p side to the n side,
leaving behind negatively charged immobile acceptor
+ VD – ions
,
– Electrons diffuse from the n side to the p side,
leaving behind positively charged immobile donor ions
Physical structure: ID acceptor ions donor ions
(an example) + metal
– +
SiO2 SiO2 – +
p – + n
p-type Si – +
VD – +
/ 0
n-type Si A region depleted of mobile carriers is formed at the junction.
! !
. 4 " • The space charge due to immobile ions in the depletion region
– metal establishes an electric field that opposes carrier diffusion.

EE40 Fall Slide 325 Prof. Chang-Hasnain EE40 Fall Slide 326 Prof. Chang-Hasnain
2006 2006

Summary: pn-Junction Diode I-V Charge Density Distribution

• Under forward bias, the potential barrier is reduced, so Charge is stored in the depletion region.
that carriers flow (by diffusion) across the junction acceptor ions donor ions
– Current increases exponentially with increasing forward bias
– +
– The carriers become minority carriers once they cross the – +
junction; as they diffuse in the quasi-neutral regions, they p – + n
– +
recombine with majority carriers (supplied by the metal contacts) – +
“injection” of minority carriers
quasi-neutral p region depletion region quasi-neutral n region
• Under reverse bias, the potential barrier is increased, so
that negligible carriers flow across the junction charge density (C/cm3)
– If a minority carrier enters the depletion region (by thermal
generation or diffusion from the quasi-neutral regions), it will be
swept across the junction by the built-in electric field
“collection” of minority carriers reverse current ID (A)
distance

VD (V)
EE40 Fall Slide 327 Prof. Chang-Hasnain EE40 Fall Slide 328 Prof. Chang-Hasnain
2006 2006
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Effect of Applied Voltage Forward Bias

– +
• As VD increases, the potential barrier to carrier
–
VD p –
+
+ n diffusion across the junction decreases*, and
– +
– + current increases exponentially.
$
– +
VD > 0 – + 4 .
p – + n ' , ! 5
• The quasi-neutral p and n regions have low resistivity, – +
whereas the depletion region has high resistivity. Thus, – + . 4 0
! "
when an external voltage VD is applied across the diode,
ID (Amperes)
almost all of this voltage is dropped across the depletion
region. (Think of a voltage divider circuit.)
• If VD > 0 (forward bias), the potential barrier to carrier
diffusion is reduced by the applied voltage. VD (Volts)
• If VD < 0 (reverse bias), the potential barrier to carrier
diffusion is increased by the applied voltage. * Hence, the width of the depletion region decreases.
EE40 Fall Slide 329 Prof. Chang-Hasnain EE40 Fall Slide 330 Prof. Chang-Hasnain
2006 2006

Reverse Bias Optoelectronic Diodes

• As |VD| increases, the potential barrier to carrier • Light incident on a pn junction generates electron-hole pairs
diffusion across the junction increases*; thus, no • Carriers are generated in the depletion region as well as n-
doped and p-doped quasi-neutral regions.
carriers diffuse across the junction.
)& & • The carriers that are generated in the quasi-neutral regions
VD < 0 – +
6 # 0
diffuse into the depletion region, together with the carriers
– +
p – + n !
generated in the depletion region, are swept across the
– + junction by the electric field
– + ' , !
! ! 4 "
ID (Amperes)

• This results in an additional component of current flowing in

VD (Volts) the diode: qVD kT
I D = I S (e − 1) − I optical
* Hence, the width of the depletion region increases. where Ioptical is proportional to the intensity of the light
EE40 Fall Slide 331 Prof. Chang-Hasnain EE40 Fall Slide 332 Prof. Chang-Hasnain
2006 2006
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Example: Photodiode Planck Constant

• An intrinsic region is placed • Planck’s constant h = 6.625·10-34 J·s
between the p-type and n-type • E=hν=hc/λ
regions • C is speed of light and hν is photon energy
• The first type of quantum effect is the quantization of
Wj ≅ Wi-region, so that most of the certain physical quantities.
electron-hole pairs are generated
in the depletion region
• Quantization first arose in the mathematical formulae of
Max Planck in 1900. Max Planck was analyzing how the
faster response time radiation emitted from a body was related to its
(~10 GHz operation) temperature, in other words, he was analyzing the
ID (A) energy of a wave.
• The energy of a wave could not be infinite, so Planck
used the property of the wave we designate as the
in the dark frequency to define energy. Max Planck discovered a
constant that when multiplied by the frequency of any
operating point VD (V) wave gives the energy of the wave. This constant is
referred to by the letter h in mathematical formulae. It is
with incident light
a cornerstone of physics.
EE40 Fall Slide 333 Prof. Chang-Hasnain EE40 Fall Slide 334 Prof. Chang-Hasnain
2006 2006

Bandgap Versus Lattice Constant Chapter 12 MOSFET

• OUTLINE
– The MOSFET as a controlled resistor
– Pinch-off and current saturation
– MOSFET ID vs. VGS characteristic
– NMOS and PMOS I-V characteristics
– Load-line analysis; Q operating point; Bias circuits
– Small-signal equivalent circuits
– Common source amplifier
– Source follower
Si – Common gate amplifier
– Gain
• Reading
– Supplementary Notes Chapter 4
– Hambley: Chapter 12.1-12.5

EE40 Fall Slide 335 Prof. Chang-Hasnain EE40 Fall Slide 336 Prof. Chang-Hasnain
2006 2006
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MOSFET Terminals MOSFET Structure

• The voltage applied to the GATE terminal determines whether DEVICE IN CROSS-SECTION
current can flow between the SOURCE & DRAIN terminals. “Metal” “Semiconductor”
“Oxide”
– For an n-channel MOSFET, the SOURCE is biased at a lower G “Metal” gate (Al or Si)
potential (often 0 V) than the DRAIN D
(Electrons flow from SOURCE to DRAIN when VG > VT) S
gate
– For a p-channel MOSFET, the SOURCE is biased at a higher oxide insulator
potential (often the supply voltage VDD) than the DRAIN n n
(Holes flow from SOURCE to DRAIN when VG < VT ) P

• The BODY terminal is usually connected to a fixed potential. • In the absence of gate voltage, no current can flow between S and D.
– For an n-channel MOSFET, the BODY is connected to 0 V
• Above a certain gate to source voltage Vt (the “threshold”), electrons are
– For a p-channel MOSFET, the BODY is connected to VDD induced at the surface beneath the oxide. (Think of it as a capacitor.)
• These electrons can carry current between S and D if a voltage is applied.

EE40 Fall Slide 337 Prof. Chang-Hasnain EE40 Fall Slide 338 Prof. Chang-Hasnain
2006 2006

MOSFET MOSFET
• Symbol and subscript convention • PMOS: Three regions of operation (interchange
– Upper case for both (e.g. VD) = DC signal (often as bias) > and < from NMOS)
– Lower case for both (e.g. vd) = AC signal (often small signal)
– Lower symbol and upper sub (e.g. vD ) = total signal = VD+vd – VDS and VGS Normally negative values
• NMOS: Three regions of operation – VGS>Vt :cut off mode, IDS=0 for any VDS
– VDS and VGS normally positive valus – VGS<Vt :transistor is turned on
• VDS> VGS-Vt: Triode Region iD = K 2(vGS − Vt )vDS − vDS 2
– VGS<Vt :cut off mode, IDS=0 for any VDS
– VGS>Vt :transistor is turned on • VDS< VGS-Vt: Saturation Region iD = K 2(vGS − Vt ) 2
• VDS< VGS-Vt: Triode Region iD = K 2(vGS − Vt )vDS − vDS 2 • Boundary vGS − Vt = vDS W KP
K=
2 L 2
• VDS> VGS-Vt: Saturation Region iD = K 2(vGS − Vt )
• Boundary v − V = v W KP
GS t DS K=
L 2

EE40 Fall Slide 339 Prof. Chang-Hasnain EE40 Fall Slide 340 Prof. Chang-Hasnain
2006 2006
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MOSFET Operating Regions Bias Circuits

• Use load line to find Quiescent operating point.
• Remember no current flow through the gate.
NMOS Fixed-plus Self-Bias CKT
VDD VDD
Cut-off Saturation Triode
vGS
0 Vto vDS + Vto
RD RD
R1
PMOS
VG+vin
Triode Saturation Cut-off
vGS
vDS + Vto Vto 0 R2
RS

EE40 Fall Slide 341 Prof. Chang-Hasnain EE40 Fall Slide 342 Prof. Chang-Hasnain
2006 2006

MOSFET Circuit Common Source Amplifier

• First look at DC case to find Q point

VDD
– Use load line technique
– All capacitors are open circuit
RD
– From Q-point, get gm and rd for small signal C
R1
AC model
+
• AC Small signal analysis C RL vo
VG -
– DC source is AC ground (because there is no +
+
AC signal variation). v(t) vin R2
RS C
- -
– All capacitors are short circuit (unless
otherwise specified).

EE40 Fall Slide 343 Prof. Chang-Hasnain EE40 Fall Slide 344 Prof. Chang-Hasnain
2006 2006
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Step 1: find Q point Load line

R2
VG = VDD VDD
R1 + R2
VGS = VG − I D RS
VDD = I D ( RD + RS ) + VDS RD C
R1
+
C VG RL vo
VDS -
+ +
v(t) vin R2
- RS C
-

From load lines, we get ID and hence gm and rd

EE40 Fall Slide 345 Prof. Chang-Hasnain EE40 Fall Slide 346 Prof. Chang-Hasnain
2006 2006

Small Signal Model Source Follower

VDD

For output impedance Rout: R1

vg = vin , vs = 0 → vgs = vin 1. Turn off all independent C
RR sources. VG C
vo = L D (− g m vgs ) 2. Take away load
RL + RD +
impedance RL + vin R2 +
v RR v(t) - RS vo
Av = o = − g m L D - RL
vin RL + RD vin = 0, vgs = 0, g m vgs = 0 -
vin RR rd RD
Rin = = 1 2 Rout =
iin R1 + R2 rd + RD
EE40 Fall Slide 347 Prof. Chang-Hasnain EE40 Fall Slide 348 Prof. Chang-Hasnain
2006 2006
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Step 1: find Q point Load line

R2
VG = VDD VDD
R1 + R2
VGS = VG − I D RS
VDD = I D RS + VDS

R1

C
VG C

+ + +
v(t) vin R2
- RS RL vo
- -

From load lines, we get ID and hence gm and rd

EE40 Fall Slide 349 Prof. Chang-Hasnain EE40 Fall Slide 350 Prof. Chang-Hasnain
2006 2006

Small Signal Model Common Gate Amplifier

VDD

RD C
1
RL′ =
rd −1 + RS −1 + RL −1 For output impedance Rout: +
vgs = vin − vo 1. Turn off all independent sources. vo
2. Take away RL VG RL
-
vo = g m vgs RL′ 3. Add Vx and find ix
vin = vgs (1 + g m RL′ ) vx = vs , vg = 0, vgs = −vx
+ + C
g m RL′ rR v
v
Av = o =
vin 1 + g m RL′ rd + Rs Rs′
(
Rs′ = d s , ix = x − g m (−vx ) = vx Rs′−1 + g m ) v(t)
-
vin
- RS
vin RR 1 -VSS
Rin = = 1 2 Rout =
iin R1 + R2 g m + rd −1 + Rs −1

EE40 Fall Slide 351 Prof. Chang-Hasnain EE40 Fall Slide 352 Prof. Chang-Hasnain
2006 2006
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Step 1: find Q point Load line

VDD
VGS = 0 − I D RS + VSS The only difference in all three circuits are
VDD + VSS = I D ( RD + RS ) + VDS the intercepts at the axes.
RD C Again from load lines, we get ID and
hence gm and rd
+
VG RL vo
-

+ + C
v(t) vin
- - RS
-VSS

EE40 Fall Slide 353 Prof. Chang-Hasnain EE40 Fall Slide 354 Prof. Chang-Hasnain
2006 2006

Small Signal Model Week 15

• OUTLINE
– Need for Input Controlled Pull-Up
– CMOS Inverter Analysis
– CMOS Voltage Transfer Characteristic
1 For output impedance Rout: – Combinatorial logic circuits
RL′ =
RL −1 + RD −1 1. Turn off all independent sources. – Logic
vgs = −vin 2. Take away RL
3. Add Vx and find ix – Binary representations
vo = − g m vgs RL′ RRs
vo R′ = – Combinatorial logic circuits
Av = = g m RL′ R + Rs
vin
v • Reading
vgs ix = x + g m vgs
iin = −( g m vgs +
Rs
) RD – Chap 7-7.5
vin 1 vgs = − g m vgs R′ , but g m R′ ≠ 1∴ vgs = 0 – Supplementary Notes Chapter 4
Rin = =
iin g m + Rs −1 Rout = RD
EE40 Fall Slide 355 Prof. Chang-Hasnain EE40 Fall Slide 356 Prof. Chang-Hasnain
2006 2006
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Digital Circuits – Introduction Analog vs. Digital Signals

• Analog: signal amplitude is continuous with time.
• Digital: signal amplitude is represented by a restricted • Most (but not all) observables are analog
set of discrete numbers.
– Binary: only two values are allowed to represent the signal: High
think of analog vs. digital watches
or low (i.e. logic 1 or 0).
• Digital word: but the most convenient way to represent & transmit
– Each binary digit is called a bit information electronically is to use digital signals
– A series of bits form a word think of telephony
• Byte is a word consisting of 8-bits
• Advantages of digital signal
– Digital signal is more resilient to noise can more easily Analog-to-digital (A/D) & digital-to-analog (D/A)
differentiate high (1) and low (0) conversion is essential (and nothing new)
• Transmission think of a piano keyboard
– Parallel transmission over a bus containing n wires.
• Faster but short distance (internal to a computer or chip)
– Serial transmission (transmit bits sequentially)
• Longer distance

EE40 Fall Slide 357 Prof. Chang-Hasnain EE40 Fall Slide 358 Prof. Chang-Hasnain
2006 2006

Analog Signal Example: Microphone Voltage Digital Signal Representations

Voltage with normal piano key stroke Voltage with soft pedal applied
50 microvolt 440 Hz signal 25 microvolt 440 Hz signal
Binary numbers can be used to represent any quantity.
60 60 We generally have to agree on some sort of “code”, and
V in microvolts

V in microvolts

40 40
20 20
the dynamic range of the signal in order to know the form
0 0 and the number of binary digits (“bits”) required.
-20 0 1 2 3 4 5 6 7 8 9 10 11 12 -20 0 1 2 3 4 5 6 7 8 9 10 11 12
-40 -40
-60 -60 Example 1: Voltage signal with maximum value 2 Volts
t in milliseconds
t in milliseconds
• Binary two (10) could represent a 2 Volt signal.
50 microvolt 220 Hz signal
60
• To encode the signal to an accuracy of 1 part in 64
V in microvolts

40 (1.5% precision), 6 binary digits (“bits”) are needed

20
0 Analog signal representing piano key A,
-20 0 1 2 3 4 5 6 7 8 9 10 11 12 below middle C (220 Hz) Example 2: Sine wave signal of known frequency and
-40
-60
maximum amplitude 50 µV; 1 µV “resolution” needed.
t in milliseconds
EE40 Fall Slide 359 Prof. Chang-Hasnain EE40 Fall Slide 360 Prof. Chang-Hasnain
2006 2006
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Decimal Numbers: Base 10 Numbers: positional notation

Digits: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 • Number Base B B symbols per digit:

–Base 10 (Decimal): 0, 1, 2, 3, 4, 5, 6, 7, 8, 9
–Base 2 (Binary): 0, 1
Example:
• Number representation:
3271 = (3x103) + (2x102) + (7x101) + (1x100) –d31d30 ... d1d0 is a 32 digit number
–value = d31 × B31 + d30 × B30 + ... + d1 × B1 + d0 × B0
This is a four-digit number. The left hand • Binary: 0,1 (In binary digits called “bits”)
most number (3 in this example) is often 11010 = 1×24 + 1×23 + 0×22 + 1×21 + 0×20
referred as the most significant number = 16 + 8 + 2
and the right most the least significant = 26
number (1 in this example). –Here 5 digit binary # turns into a 2 digit decimal #

EE40 Fall Slide 361 Prof. Chang-Hasnain EE40 Fall Slide 362 Prof. Chang-Hasnain
2006 2006

Hexadecimal Numbers: Base 16 Digital Signal Representations

• Hexadecimal: Binary numbers can be used to represent any quantity.

0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F We generally have to agree on some sort of “code”, and

the dynamic range of the signal in order to know the form
–Normal digits + 6 more from the alphabet and the number of binary digits (“bits”) required.
⇔Hex
• Conversion: Binary⇔
Example 1: Voltage signal with maximum value 2 V and
–1 hex digit represents 16 decimal values minimum of 0 V.
–4 binary digits represent 16 decimal values • Binary two (10) could represent a 2 Volt signal.
1 hex digit replaces 4 binary digits
• To encode the signal to an accuracy of 1 part in 64
(1.5% precision), 6 binary digits (“bits”) are needed

Example 2: Sine wave signal of known frequency and

maximum amplitude 50 µV; 1 µV “resolution” needed.
EE40 Fall Slide 363 Prof. Chang-Hasnain EE40 Fall Slide 364 Prof. Chang-Hasnain
2006 2006
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Resolution Decimal-Binary Conversion

• The size of the smallest element that can • Decimal to Binary

be separated from neighboring elements. – Repeated Division By 2
The term is used to describe imaging • Consider the number 2671.
systems, the frequency separation – Subtraction – if you know your 2N values by
achieved by spectrometers, and so on. heart.
• Binary to Decimal conversion
1100012 = 1x25 +1x24 +0x23 +0x22 + 0x21 + 1x20
= 3210 + 1610 + 110
= 4910
= 4x101 + 9x100

EE40 Fall Slide 365 Prof. Chang-Hasnain EE40 Fall Slide 366 Prof. Chang-Hasnain
2006 2006

Example 2 (continued) Binary Representation

Possible digital representation for the sine wave signal: • N bit can represent 2N values: typically
Analog representation: Digital representation: from 0 to 2N-1
Amplitude in µV Binary number
1 000001 – 3-bit word can represent 8 values: e.g. 0, 1, 2,
2 000010
3 000011
3, 4, 5, 6, 7
4 000100
5 000101 • Conversion
8 001000 – Integer to binary
16 010000 – Fraction to binary (13.510=1101.12 and
32 100000
0.39210=0.0110012)
50 110010 • Octal and hexadecimal
63 111111

EE40 Fall Slide 367 Prof. Chang-Hasnain EE40 Fall Slide 368 Prof. Chang-Hasnain
2006 2006
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Boolean algebras

• Logic gates • Algebraic structures

– "capture the essence" of the logical operations AND,
– Combine several logic variable inputs to OR and NOT
produce a logic variable output – corresponding set for theoretic operations
• Memory intersection, union and complement
– named after George Boole, an English mathematician
– Memoryless: output at a given instant at University College Cork, who first defined them as
depends the input values of that instant. part of a system of logic in the mid 19th century.
– Momory: output depends on previous and – Boolean algebra was an attempt to use algebraic
techniques to deal with expressions in the
present input values. propositional calculus.
– Today, Boolean algebras find many applications in
electronic design. They were first applied to switching
by Claude Shannon in the 20th century.

EE40 Fall Slide 369 Prof. Chang-Hasnain EE40 Fall Slide 370 Prof. Chang-Hasnain
2006 2006

Boolean algebras Boolean Algebra

• The operators of Boolean algebra may be • NOT operation (inverter)
A A=0
represented in various ways. Often they are
simply written as AND, OR and NOT. • AND operation A+ A =1
A A= A
• In describing circuits, NAND (NOT AND), NOR
(NOT OR) and XOR (eXclusive OR) may also be A 1= A
used. A 0=0
• Mathematicians often use + for OR and · for A B=B A
AND (since in some ways those operations are • OR operation
( A B) C = A ( B C )
analogous to addition and multiplication in other
algebraic structures) and represent NOT by a A+ A = A
line drawn above the expression being negated. A +1 = 1
A+0 = A
A+ B = B + A
( A + B) + C = A + ( B + C )
EE40 Fall Slide 371 Prof. Chang-Hasnain EE40 Fall Slide 372 Prof. Chang-Hasnain
2006 2006
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Graphic Representation Graphic Representation

A A=0 A+ B
A A+ A =1 A
A AB B

A ⊕ B = AB + AB = ( A + B ) ( A + B ) = A B + A + B
Full square = complete set =1 Exclusive OR=yellow and blue part –
Yellow part = NOT(A) =A intersection/overlap part
White circle = A =exactly when only one of the input is true

EE40 Fall Slide 373 Prof. Chang-Hasnain EE40 Fall Slide 374 Prof. Chang-Hasnain
2006 2006

Boolean Algebra Examples

• Distributive Property F = A•B•C + A•B•C + (C+D)•(D+E)

A (B + C) = A B + A C
( A + B) C = ( A + B) ( A + C )
• De Morgan’s laws
A+ B = A B
A B = A+ B
• An excellent web site to visit
– http://en.wikipedia.org/wiki/Boolean_algebra
F = C•(A+D+E) + D•E
EE40 Fall Slide 375 Prof. Chang-Hasnain EE40 Fall Slide 376 Prof. Chang-Hasnain
2006 2006
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Logic Functions, Symbols, & Notation Logic Functions, Symbols, & Notation 2
TRUTH A B F
NAME SYMBOL NOTATION TABLE A 0 0 1
“NOR” F F = A+B 0 1 0
A F B 1 0 0
0 1 1 1 0
“NOT” A F F=A 1 0

A B F
A B F 0 0 1
0 0 0 A
A “NAND” F F = A•B 0 1 1
“OR” F F = A+B 0 1 1 B 1 0 1
B 1 0 1 1 1 0
1 1 1

A B F
A B F
A 0 0 0 “XOR” A F F=A+B
0 0 0
“AND” F F = A•B 0 1 0 (exclusive OR) B
0 1 1
1 0 1
B 1 0 0
1 1 0
1 1 1
EE40 Fall Slide 377 Prof. Chang-Hasnain EE40 Fall Slide 378 Prof. Chang-Hasnain
2006 2006

Circuit Realization Logic Functions, Symbols, & Notation

TRUTH
A ⊕ B = AB + AB = ( A + B) ( A + B) = A B + A + B
NAME SYMBOL NOTATION TABLE
A A F
0 1
A AB “NOT” A F F=A 1 0
B A⊕ B
B A B F
0 0 0
A
“OR” F F = A+B 0 1 1
AB B 1 0 1
1 1 1

A B F

“AND” A F F = A•B
0 0 0
0 1 0
B 1 0 0
1 1 1
EE40 Fall Slide 379 Prof. Chang-Hasnain EE40 Fall Slide 380 Prof. Chang-Hasnain
2006 2006
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Logic Functions, Symbols, & Notation 2 Fan in/Fan out

A B F • Complex digital operations are formed with a
A 0 0 1 variety of gates interconnected to yield the
“NOR” F F = A+B 0 1 0
desired logic function.
B 1 0 0
1 1 0 • Sometimes a number of inputs are connected to
one gate input and output of a gate may be
A B F connected to a number of gates.
0 0 1
A • Fan-in: the maximum number of logic gates that
“NAND” F F = A•B 0 1 1
B 1 0 1 can be connected at the input of a gate without
1 1 0
altering its performance.
A B F
• Fan-out: the maximum number of logic gates
A 0 0 0 that can be connected to the output of a gate
“XOR” F F=A+B 0 1 1 without altering its performance.
(exclusive OR) B 1 0 1
1 1 0 • Typical fan-in and fan-out numbers are 3.
EE40 Fall Slide 381 Prof. Chang-Hasnain EE40 Fall Slide 382 Prof. Chang-Hasnain
2006 2006

Inverter = NOT Gate Terminology for a Logic Circuit

VDD = Power supply voltage (D is from

Vin Vout Drain) we do not draw the symbol.
VDD
Pull-Up Network = Set of devices used to
carry current from the power supply to
Ideal Transfer Characteristics the output node to charge the output
RPULL UP
node to the power supply voltage.
Vout IOUT Output Pull-Down Network = Set of devices used to
carry current from the output node to ground to
discharge the output node to ground.
VOUT
Pull-Down
VIN (NMOS) IOUT = Current for the device under study.

Vin VTD = Threshold Voltage value of VIN at which the

V/2 V Pull-Down (NMOS transistor) begins to conduct.
VOUT-SAT-D = Value of VOUT beyond which the current IOUT-D
saturates at the (drain) current saturation value IOUT-SAT-D.
EE40 Fall Slide 383 Prof. Chang-Hasnain EE40 Fall Slide 384 Prof. Chang-Hasnain
2006 2006
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Thevenin Model For Pull-Up Device Load Line For Pull-Up Device

IOUT vs. VOUT

VDD For the Pull-Up Resistor and VDD
IOUT(µA)
RPULL UP 100
IOUT vs. VOUT is constrained to be on this line
by the circuit external to the three-terminal
Output device
IOUT
VTHEVENIN = VDD 60
IOUT SHORT CIRCUIT = (VDD/RPULL UP) INORTON
Example: Thevenin VOUT
VDD = 5V and RPULL UP = 100kΩ looking VTHEVENIN
this way 20
VTHEVENIN = 5V
IOUT SHORT CIRCUIT = 50 µA
0 3 5 VOUT(V)
EE40 Fall Slide 385 Prof. Chang-Hasnain EE40 Fall Slide 386 Prof. Chang-Hasnain
2006 2006

NMOS Resistor Pull-Up Disadvantages of NMOS Logic Gates

VDD
Circuit: Voltage-Transfer Characteristic
vOUT • Large values of RD are required in order to
RD
iD – achieve a low value of VOL
VDD
+
F – keep power consumption low
A
+
vDS = vOUT
iD vIN
vIN = VDD
– – Large resistors are needed, but these take
0 VT VDD
vIN up a lot of space.
VDD/RD • One solution is to replace the resistor with an
NMOSFET that is always on.
!
7 8 A F
0 1
vDS 1 0
0 vGS = vin ≤ VT VDD
EE40 Fall Slide 387 Prof. Chang-Hasnain EE40 Fall Slide 388 Prof. Chang-Hasnain
2006 2006
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The CMOS Inverter: Intuitive Perspective CMOS Inverter Voltage Transfer Characteristic
(
CIRCUIT SWITCH MODELS <
VDD
VOUT
VDD VDD VDD ( G S
< C
VDD D

G S VIN VOUT
Rp ( D
<
D G
S
VIN VOUT VOUT VOUT A B D E
D VOL = 0 V VOH = VDD
(
G
Rn <
S
(
<
0 VIN
0
VIN = VDD VIN = 0 V 0 VDD
9: /;$
EE40 Fall Slide 389 Prof. Chang-Hasnain EE40 Fall Slide 390 Prof. Chang-Hasnain
2006 2006

CMOS Inverter Load-Line Analysis CMOS Inverter Load-Line Analysis: Region A

V VDD V VDD
VIN = VDD + VGSp
GS
p =V – VIN ≤ VTn GS
p =V –
IN -V – IN -V –
DD DD
VOUT = VDD + VDSp VDSp=VOUT-VDD VDSp=VOUT-VDD
IDn=-IDp + IDn=-IDp +
+ +
VIN VOUT VIN VOUT
! 7 2 7 IDn=-IDp IDn=-IDp

0 VOUT=VDSn 0 VOUT=VDSn
0 VDD 0 VDD
7, 7

EE40 Fall Slide 391 Prof. Chang-Hasnain EE40 Fall Slide 392 Prof. Chang-Hasnain
2006 2006
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CMOS Inverter Load-Line Analysis: Region B CMOS Inverter Load-Line Analysis: Region D
V VDD V VDD
VDD/2 > VIN > VTn GS
p =V – VDD – |VTp| > VIN > VDD/2 GS
p =V –
IN -V – IN -V –
DD DD
VDSp=VOUT-VDD VDSp=VOUT-VDD
IDn=-IDp + IDn=-IDp +
+ +
VIN VOUT VIN VOUT
IDn=-IDp IDn=-IDp

0 VOUT=VDSn 0 VOUT=VDSn
0 VDD 0 VDD

EE40 Fall Slide 393 Prof. Chang-Hasnain EE40 Fall Slide 394 Prof. Chang-Hasnain
2006 2006

CMOS Inverter Load-Line Analysis: Region E Features of CMOS Digital Circuits

V VDD
VIN > VDD – |VTp| GS
p =V –
IN -V – • The output is always connected to VDD or GND
DD
VDSp=VOUT-VDD in steady state
IDn=-IDp +
+ → Full logic swing; large noise margins
VIN VOUT
IDn=-IDp
→ Logic levels are not dependent upon the relative
sizes of the devices (“ratioless”)

• There is no direct path between VDD and GND

in steady state
→ no static power dissipation

0 VOUT=VDSn
0 VDD

EE40 Fall Slide 395 Prof. Chang-Hasnain EE40 Fall Slide 396 Prof. Chang-Hasnain
2006 2006
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The CMOS Inverter: Current Flow during Switching Power Dissipation due to Direct-Path Current
(
VDD VDD
VOUT < i VDD-VT
( S
vIN:
G
VDD < C
VDD D VT
vIN i vOUT
0
G S
(
<
D Ipeak
D
G
VIN i VOUT S
i:
D A B D E
G
S (
0
< tsc
time
(
<
0 VIN
0 VDD Energy consumed per switching period: Edp = t scVDD I peak
EE40 Fall Slide 397 Prof. Chang-Hasnain EE40 Fall Slide 398 Prof. Chang-Hasnain
2006 2006

NMOS NAND Gate NMOS NOR Gate

• Output is low only if both inputs are high • Output is low if either input is high
VDD
VDD

RD
RD
F
F
A
A B
Truth Table Truth Table
A B F A B F
B 0 0 1 0 0 1
0 1 1 0 1 0
1 0 1 1 0 0
1 1 0 1 1 0

EE40 Fall Slide 399 Prof. Chang-Hasnain EE40 Fall Slide 400 Prof. Chang-Hasnain
2006 2006
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N-Channel MOSFET Operation P-Channel MOSFET Operation

An NMOSFET is a closed switch when the input is high A PMOSFET is a closed switch when the input is low

A A
A B A B

B B
X Y X Y X Y X Y
Y = X if A and B Y = X if A and B
Y = X if A or B = (A + B) Y = X if A or B
= (AB)
NMOSFETs pass a “strong” 0 but a “weak” 1
PMOSFETs pass a “strong” 1 but a “weak” 0

EE40 Fall Slide 401 Prof. Chang-Hasnain EE40 Fall Slide 402 Prof. Chang-Hasnain
2006 2006

Pull-Down and Pull-Up Devices CMOS NAND Gate

• In CMOS logic gates, NMOSFETs are used to connect VDD
A B F
the output to GND, whereas PMOSFETs are used to 0 0 1
connect the output to VDD. 0 1 1
– An NMOSFET functions as a pull-down device when it 1 0 1
is turned on (gate voltage = VDD) A B 1 1 0

– A PMOSFET functions as a pull-up device when it is

turned on (gate voltage = GND)
VDD
F
A1 A
A2 Pull-up
input signals PMOSFETs only
AN network
F(A1, A2, …, AN)
A1 B
A2 Pull-down
NMOSFETs only
AN network

EE40 Fall Slide 403 Prof. Chang-Hasnain EE40 Fall Slide 404 Prof. Chang-Hasnain
2006 2006
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CMOS NOR Gate CMOS Pass Gate

VDD
A B F
0 0 1
0 1 0
A
A 1 0 0
1 1 0

B X Y Y = X if A
F

B A
A

EE40 Fall Slide 405 Prof. Chang-Hasnain EE40 Fall Slide 406 Prof. Chang-Hasnain
2006 2006

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