Real Time Embedded Systems

Course code: CoSc3026/SEng4033

By- Dr. Mohammad Nasre Alam

 Chapter 2
Embedded System Architecture
Contents
1. Hardware Architecture of ES
2. ARM Cortex M0+ Hardware Overview.
3. Communication
4. ATmega32 microcontroller Architecture.
5. Assembly language Programming with ATmega32 Instruction Set
6. Programming in C to Interface peripherals, Interrupts, ISR and Timers.
 1. Hardware Architecture of ES
Key Component of Embedded System
Microprocessor (CPU):
• The central unit that performs computation and control
tasks.
• Examples: ARM Cortex-M, AVR, PIC, etc.
Memory:
• ROM (Read-Only Memory): Stores firmware (non-volatile).
• RAM (Random Access Memory): Stores data and variables
(volatile).
• EEPROM/Flash: Non-volatile memory for data storage.
Input/Output Interfaces:
• Sensors/Actuators: Interaction with the physical world.
• Communication Ports: Serial (UART), USB, SPI, I2C, etc.
• Display/LEDs: Visual feedback for the user.
Power Supply:
• Provides the necessary voltage and current to the system.
• Can be battery-powered or use AC/DC adapters.
Peripherals:
• Specialized components like ADC/DAC converters, timers,
and watchdogs.
 1. Hardware Architecture of ES Cont…
Block diagram of Processor
The CPU is the heart of the embedded system, responsible for
executing instructions and managing control signals. It has two
essential units –
Execution Unit (EU):
• General Purpose Register: Contain the current data and operands
that are being manipulated by processor.
• Arithmetic Logical Unit (ALU): Responsible for performing
Arithmetic and Logical instructions.
Control Unit:
• Stack Point: It points to the instructions.
• Memory Address Register: It connected with address bus which
is responsible for providing the address of that particular memory
where addresses are stored.
• Instruction Pointer: It pointing to the next instruction.
• Memory Data Register: It is responsible for providing the data
which is bidirectionally connected to the data bus.
• Instruction Decoder: It is useful for decoding the instruction that
is also bidirectional connected to the control & Status Bus.
 1. Hardware Architecture of ES Cont…
Architecture of Processor
To do function the processor communicates with
other devices using three buses, a bus being a
group of signals– Data Bus, Address Bus and
Control and Status Bus.

1. Fundamental Architecture- The fundamental architecture of a

computer system refers to the actual physical hardware components
and how they are organized and connected to each other. It is three
types -
i. Von Neuman Architecture:- CPU connected with memory and
that memory contains instruction and data both.
ii. Harvard Architecture:- CPU connected with two memory, which
is Program memory and Data memory. Program memory contains
instructions and the data memory contains data only.
iii. Super-Harvard Architecture:- It is advanced version of Harvard
architecture. It additionally include instruction cache in the CPU.
The instruction cache is responsible for storing all the instructions.
 1. Hardware Architecture of ES Cont…
2. Instruction Set Architecture (ISA): - The ISA defines the set of instructions that the processor can execute. These
instructions are the fundamental operations that the CPU performs, and they are used by software (like operating systems and
applications) to interact with the hardware. The ARM ISA or the x86 instruction set used by Intel and AMD processors. It is
categorized in two group-
i. Complex instruction set computers (CISC):- A complex instruction set computer (CISC) is a computer architecture in which
single instructions can execute several low-level operations (such as a load from memory, an arithmetic operation, and a memory
store) or are capable of multi-step operations or addressing modes within single instructions.
ii. Reduced Instruction Set Computers (RISC):- A Reduced Instruction Set Computer is a type of microprocessor architecture
that utilizes a small, highly-optimized set of instructions rather than the highly-specialized set of instructions.
 1. Hardware Architecture of ES Cont…
Memory: Information Storage Device.
• All Digital systems store information in binary digits called bits. These bits are used for
representing Operators, operands, and addresses. There are two states for a binary bit. A `1'
represents the presence of a voltage and a `0' represents the absence of voltage. This
representation is called positive logic.
• To store binary information, CMOS circuits can be built and a collection of a large number
of such circuits is called memory. Memory stores data sequentially which is as shown in
Figure.
• Based on read and write operations, memories are grouped in two categories namely-
i. Read-Only Memory (ROM): The memory that allows the processor to only read its contents is Read Only Memory (ROM).
Another characteristic of ROM is that they can store information permanently even when no power is applied. The
information in the ROM is therefore non volatile. Example- PROM, EPROM, EEPROM, Flash Memory.
ii. Random Access Memory (RAM): The memory which allows the processor to read from and write to its locations is known
as Random Access Memory (RAM). One limitation of RAM is that information stored in it is lost as soon as the power
applied to it is removed. On the other hand, RAM is not limited by the number of read and write cycles and is more suitable
for storing data that is updated frequently. The read and write operations of RAMs are faster than those of ROMs. There are
different types of RAMs namely-
a. Dynamic RAM (DRAM):- is the most commonly used type of RAM. Each memory cell of a DRAM, can store one bit
of information. It is made up of two transistors and a capacitor. The transistor acts as a switch while the Capacitor holds
the charge.
b. Static RAM (SRAM):- employs a flip-flop for storing a bit in a memory cell. A Flip-flop requires 4 to 6 transistors and
does not require refreshing circuitry.
 2. ARM Cortex M0+ Hardware Overview
ARM Cortex M0+ Hardware Overview
• The ARM Cortex-M0+ is a processor core that is integrated into
microcontrollers by various manufacturers (e.g., STMicroelectronics,
NXP, Silicon Labs).
• The specific hardware features like ports, GPIO, ADC, and DAC
depend on the microcontroller implementation.
• It is 32-bit microprocessor core designed by ARM based on the
ARMv6-M architecture has 2-stage pipeline (Fetch and Execute).
• Operates at clock frequencies up to 100MHz.
• It has low-power consumption, low-cost and high-efficiency operation.
• It is used in IoT devices, wearable electronics, motor control,
automotive systems and industrial sensors.
 2. ARM Cortex M0+ Hardware Overview Cont…
Core Components
1. Processor Core- Implements a 2-stage pipeline for efficient instruction execution.
• Fetch Stage: Retrieves instructions from memory.
• Execute Stage: Decodes and executes instructions.
2. Register – Operate as temporary storage within a program which is 32-bit wide.
• General purpose Register (R0-R12) – total 13 registers used for storing data and
intermediate results during program execution. Accessible by instructions like ADD,
MOV, SUB, etc.
• Special Registers- these are used for specific purpose and system level operation.
o R13 (Stack Pointer (SP)):- Points to the top of the current stack frame. Cortex-M0+
supports two stack pointers- Main (MSP) and Process (PSP).
o R14 (Link Register (LR)):- Holds the return address for function calls.
o R15 (Program Counter (PC)):- Points to the address of the next instruction to
execute.
o Program Status Register (PSR):- Contains system state and condition flags (e.g.
Zero (Z), Negative (N), Overflow(V) and Carry (C)).
3. ALU (Arithmetic Logic Unit) – Handles arithmetic and logical operations.
 2. ARM Cortex M0+ Hardware Overview Cont…
Nested Vectored Interrupt Controller (NVIC)
• Manages up to 32 interrupts with priority levels.
• Fast interrupt handling.
• Supports tail-chaining for rapid interrupt processing.
• Ensures deterministic latency, critical for time-sensitive tasks.

Memory Interface
It has Havard Architecture i.e. separate instruction and data buses for concurrent access to code and data memory. Supports Code
Memory, Data Memory (SRAM), and Peripherals Memory.
• Code Memory – Stores instructions (typically Flash).
• Data Memory – SRAM for variables and stack.
• Peripheral Memory – Mapped regions for peripherals like GPIO, ADC and Communication interfaces.

Ports
Ports is an ARM Cortex-M0+ microcontroller refer to the hardware interfaces used to interact with external devices. These ports allow the
processor to connect with sensors, actuators, communication devices and other peripherals.
1. General Purpose I/O Ports (GPIO) – It is configurable as either input or output. They allow the microcontroller to interface directly
with digital signals. Each GPIO pin can be individually controlled for input or output.
2. Analog I/O Ports
• Analog – to – Digital Converter (ADC) - Converts analog signals (e.g. from a temperature sensor) into digital values for processing.
Ports connected to ADC channels are used for analog inputs.
• Digital – to – Analog Converter (DAC) – Converts digital values to analog signals e.g. for controlling actuators or sound output.
 3. Communication
Contex-M0+ microcontroller supports multiple communication protocols, making it highly versatile for embedded applications. These
communication peripherals allow data exchange wit sensors, actuators, other microcontrollers and external devices. The types of communication
in Cortex-M0+ are –
1. Serial Communication Protocols-
a. UART (Universal Asynchronous Receiver- Transmitter) – Use for serial communication. Transmit (TX) and Receive (RX) pins used
to send and receive data.
b. SPI (Serial Peripheral Interface) – High speed synchronous communication with multiple devices. Ports are –
o MOSI: Master Out, Slave In.
o MISO: Master In, Slave Out.
o SCK: Clock.
o SS/CS: Slave Select/Chip Select.
c. I2C (Inter-Integrated Circuit)/TWI (Two Wire Interface) – It is two-way synchronous protocol, uses only SDA (Serial Data) and SCL
(Serial Clock) line. It supports Multi-master, multi-slave. Use for EEPROMs, temperature sensors and real time clocks.
d. CAN (Controller Area Network) – Robust protocol designed for automotive and industrial systems. It is use for error detection and
fault tolerance.
2. Wireless Communication (via External Modules) – Although Contex-M0+ doesn’t have built-in wireless communication, it can interface
with external wireless modules:
a. Bluetooth: Using UART (e.g. HC-05 module).
b. Wi-Fi: Using SPI or UART (e.g. ESP8266, ESP32).
c. ZigBee/LoRa: Using UART or SPI for long-range communication.
3. Parallel Communication Protocols – Cortex-M0+ doesn’t include dedicated parallel communication peripherals, it can implement parallel
communication through its General Purpose Input/Output (GPIO) pins.
4. Ethernet Communication – Many Cortex-M0+ microcontrollers equipped with a MAC (Media Access Controller) or an external MAC/PHY
interface for Ethernet communication.
 4. ATmega32 microcontroller Architecture

• ATmega32 microcontroller is a member of AVR architecture.

• AVR architecture was designed by two students Alf-Egil Bogen
and Vegard Wollan at the Norwegian Institute of Technology
and then was bought and developed by Atmel Corporation in
1996.
• AVR stands for Advanced Virtual RISC or some call it as Alf
and Vegard RISC.
• AVR is super Harward architecture 8-bit RISCS single chip
microcontroller.
• AVR are generally classified into four board groups:
o Classic – e.g. AT90S2313, AT90S443
o Mega – e.g. ATmega8, ATmega32, ATmega128
o Tiny – e.g. ATtiny13, ATtiny25
o Special Purpose – e.g. AT90PWM216, AT90USB1287
• ATmega32 is most widely used and available.
 4. ATmega32 microcontroller Architecture Cont..

Pins and Ports Overview

• Atmega32 has got total 40 pins.
• Two for Power (pin no.10: +5v, pin no. 11: ground),
• two for oscillator (pin 12, 13), one for reset (pin 9),
• three for providing necessary power and reference voltage to its internal ADC.
• One for reset.
• 32 (4×8) I/O pins.
 4. ATmega32 microcontroller Architecture Cont..
Pins and Ports Overview
• VCC & GND: Digital supply voltage for ATmega32. Typically operating Voltage 2.7
– 5.5V. Should never exceed 6.0 V.
• XTAL1 &Xtal2: Connections to ceramic/crystal on-chip oscillator for generating
internal clocks.
• Reset: A low level on this pin for longer than 1.5 micro sec length will generate a
reset. During Reset, all I/O Register are set to their initial values, & the program starts
execution from the Reset vector.
• AVCC: The supply voltage pin for the ADC, should be externally connected to VCC.
• AREF: The analog reference pin for the ADC, connect to suitable voltage if external
reference is chosen.
• Port A (PA0-PA 7): Serves as an 8-bit bi-directional digital I/O port. Port A can be
programmed to serve as alternate function as analog input for the ADC.
• Port B (PB0- PB 7): Serves as an 8-bit bi-directional digital I/O port with optional
internal pull-ups. Port B pins are tri-stated when reset. Port B can be programmed to
serve as alternate function.
• Port C (PC0 – PC7): Serves as an 8-bit bi-directional digital I/O pins are tri-stated
when reset/ Port C can be programmed to serve as alternate function.
• Port D (PD0 – PD7): Serve as an 8-bit bi-directional I/O port with optional internal
pull-ups. Port D pins are tri-stated when reset. Port D can be programmed to serve as
alternate function.
5. Assembly language Programming with ATmega32 Instruction Set

AVR Data Types

• Hex Number – There is two way to represent hex number:
1. Put 0x or 0X in the front of the number – LDI R16, 0x99 OR LDI R16,
0X99.
2. Put $ in front of the number – LDI R28, $75.
• Binary Numbers – There is only one way to represent binary numbers in an AVR
assembler.
LDI R16, 0b10011001 or LDI R16 0B10011001
• Decimal Numbers – To indicate decimal numbers in an AVR assembler we
simply use the decimal and nothing before or after it.
LDI R17, 12
• ASCII Characters – To represent ASCII data in an AVR assembler we use single
quotes as follows
LDI R23, ‘2’ .
5. Assembly language Programming with ATmega32 Instruction Set Con..
Assembler Directives o .INCLUDE- The include directive tells the AVR assembler to
add the contents of a file to the program.
• While the instructions tell the CPU what to do, directives give direction Example
to the assembler. When we want to use ATmega32, we must write the following
• These are also called as pseudo instructions. instruction at the beginning of your program: .INCLUDE
“M32DEF.INC”.
• The following are mostly used assembler directives in AVR o .DB – This directive is used to define byte for the given
programming. address location or define set of bytes for the consecutive
o .EQU- This directive is use to define/name a constant or a fixed memory locations. The .DB directive reserves memory
address. The .EQU directive does not set aside storage for a data resource in the program memory or the EEPROM memory.
item/address label, but associates a constant number with a data or an o .DEF- The .DEF directive allows the registers to be referred
address label, so that when the label appears in the program, its to through symbols. A defined symbol can be used in the rest
constant will be substituted for the label. of the program to refer to the register it is assigned to. A
Example register can have several symbolic names attached to it. The
symbol can be redefined later in the program.
.EQU COUNT = 0x25……. LDI R21, COUNT Example
.EQU SUM = 0x12………….LDI R18, SUM .DEF temp = R16
.DEF ior = R0
o .SET – This directive is used to define a constant value or a fixed
o .UNDEF – The UNDEF directive is used to un-define a
address. .SET and .EQU directives are identical. The only difference is
symbol previously defined with the .DEF directive. This
that the value assigned by the .SET directive may be reassigned later.
provides a way to obtain a simple scoping of register
o .ORG- The .ORG directive is used to indicate the beginning of t he definitions, to avoid warnings about register reuse.
address. It can be used for both code and data. Example
Example .DEF var1 = R16
LDI var1, 0x20….. Do something more with var1
.ORG ox200 ……… start ad address 200. .UNDEF var1
5. Assembly language Programming with ATmega32 Instruction Set Con..
Instruction Set
1. Arithmetic and Logical Instructions 2. Branch /Jump/Call Instructions 3. Data Transfer Instructions.

1. Arithmetic and Logical Instructions

5. Assembly language Programming with ATmega32 Instruction Set Con..
1. Arithmetic and Logical Instructions Cont..
5. Assembly language Programming with ATmega32 Instruction Set Con..
1. Arithmetic and Logical Instructions Cont..
5. Assembly language Programming with ATmega32 Instruction Set Con..
2. Branch /Jump/Call Instructions
5. Assembly language Programming with ATmega32 Instruction Set Con..
2. Branch /Jump/Call Instructions Cont..
5. Assembly language Programming with ATmega32 Instruction Set Con..
2. Branch /Jump/Call Instructions Cont..
5. Assembly language Programming with ATmega32 Instruction Set Con..
2. Branch /Jump/Call Instructions Cont..
5. Assembly language Programming with ATmega32 Instruction Set Con..
3. Data Transfer Instructions
 6. Programming in C to Interface peripherals, Interrupts, ISR and Timers

Interfacing Peripherals
• Interfacing handles how to connect with peripherals to
another Embedded System. It includes how to integrate and
communicate ES with each other. It also includes designing
software handlers that perform the communication through
the peripherals.
• In ATmega32 has 32 Programmable I/O lines – PortA,
PortB, PortC and PortD.
• Each Port consists three registers :
o Data Direction Register (DDRx)
o Output Register (PORTx)
o Input Register (PINx)
6. Programming in C to Interface peripherals, Interrupts, ISR and Timers Cont..

Interfacing Peripherals Cont..

Input/Output Programming
• Programmer decide which port is Input and which is output.
o Configure the port direction by using register DDRx.
1 for Output and 0 for Input.
o In Read: Use register PINx.
o In Write: Use register PORTx.
6. Programming in C to Interface peripherals, Interrupts, ISR and Timers Cont..
Interrupts
Interrupt Service Routine (ISR)
Types • When an interrupt is invoked, the micro-controller
runs the ISR.
1. Exception handling - Reset and Software Interrupts.
2. Non maskable Interrupts – It doesn’t depend on global • For every interrupt, there is a fixed location in
interrupt in processor status word. Usually it’s external memory that holds the address of its ISR.
interrupts.
• It is a specialized function or routine that is called
3. Maskable Interrupts – Depend on global interrupt enable in when an interrupt is triggered by a hardware device.
processor status. It may be
• Example-
• External interrupt from external pin.
• Internal interrupt from peripheral.

What happens when an interrupt occurs?

• The current instruction finishes execution.
• The address of the next instruction is calculated and pushed on
the stack.
• All the CPU registers are pushed onto the stack.
• The program counter is loaded with the address pointed to by
the interrupt vector and execution continues.
6. Programming in C to Interface peripherals, Interrupts, ISR and Timers Cont..

Timer Module
The timer of the AVR can be monitor Three events through State Register (TIMSK):
• Timer Overflow – means that the counter has counted up to its maximum value and is reset to zero in
the next timer clock cycle. The resolution of the timer determines the maximum value of that timer.
The timer overflow event causes the Timer Overflow Flag (TOVx) to be set in the Timer Interrupt Flag
Register (TIFR).
• Compare Match – In case where it is not sufficient to monitor a timer overflow. The compare match
interrupt can be used. The Output Compare Register (OCRx) can be loaded with a value [0.. MaxVal]
which the timer will be checked against every timer cycle. When the timer reaches the compare value,
the corresponding Output Compare Flag (OCFx) in the TIFR register is set. The Timer can be
configured to clear the count register to “0” on a compare match.
• Input capture – The AVR has an input pin to trigger the input capture event. A signal change at this
pin causes the timer value to be read and saved in the Input Capture Register (ICRx). At the same time
the ICFx in the TIFR will be set. This is useful to measure the width of external pulses.
THANK YOU VERY MUCH
chapter 2 Completed