BEE 4206:Microprocessor Systems

Lec: Mourice Ojijo

School of Computing and Engineering Sciences, Strathmore University

January 14, 2025

 Course content

1 Basics of microcontroller and microprocessor

2 Differences between microcontroller and microprocessor
3 Microprocessor Architecture and Microcomputer systems
4 Microprocessor Architecture and Memory Interfacing
5 Interfacing I/O Devices
6 Interrupts
7 MCS-51 Microcontroller
8 Assembly Language

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 Microprocessors

What is a microprocessor: A microprocessor is a

multipurpose, programmable , clock-driven, register based
electronic device that reads binary instructions from a storage
device called memory, accepts binary data and provides results
A typical programmable machine consists of: a microprocessor,
a memory and input/output devices
The components of a programmable system include:
▶ Hardware: Which is the physical part of the system
▶ Program: Which is a set of instructions written for the
microprocessor to run
▶ Software: Which a group of programs combine to perform a
certain task

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 Microprocessors

A typical programmable system/microcomputer is shown in

figure 1

Figure 1: A programmable machine or microcomputer

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 Microprocessor as a programmable device

A microprocessor can receive instructions the perform a task

based on those instructions.
A modern microprocessor is designed to understand instructions
and execute them.
A programmer can select appropriate instructions and as the
microcomputer to perform various tasks on a given data.
The instructions are stored in a device called memory. A
memory is a set of finite size registers.
The registers are always grouped together in powers of two. For
instance, a group of 1024(210 ) 8-bit registers on a
semiconductor chip is known as 1K byte memory

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Sciences, Strathmore
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University) January 14, 2025 5 / 69
 Microprocessor as a programmable device

Input/output devices allow users to interact with a

microprocessor. Such devices include a keyboard, card reader, a
scanner, monitors, LED displays etc
The primary component of a microcomputer is a microprocessor
also known as the central processing unit (CPU)
The CPU contains various
▶ Registers to store temporary data
▶ The arithmetic logic unit (ALU) which performs arithmetic and
logical operations
▶ The instruction decoders, counters and control lines

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Sciences, Strathmore
Systems
University) January 14, 2025 6 / 69
 Microprocessor as a programmable device

Figure 2: A block diagram of a computer

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 Microprocessor as a programmable device

Figure 3: A block diagram of a computer with CPU and a block diagram

of a microcontroller

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 Advance semiconductor technology
The invention of integrated circuits in the 1950s prompted
development of large scale integration which eventually led to
the manufacturing of microprocessors.

Figure 4: The historical perspective of Intel microprocessors

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 Overview of other processors

Figure 5: 8086 pin out

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 Overview of other processors

Figure 6: Bus latching

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 Overview of other processors

Figure 7: Bus latching most applicable

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Sciences, Strathmore
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 Overview of other processors

Figure 8: 80186 block diagram

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 Overview of other processors

Figure 9: 80186 pin diagram

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 Overview of other processors

Figure 10: 80186 pin diagram

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 Overview of other processors

Figure 11: 80286 block diagram courtesy Intel Corporation

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 Overview of other processors

Figure 12: 80286 pin diagram courtesy Intel Corporation

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 Overview of other processors

Figure 13: 80386 pin diagram courtesy Intel Corporation

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Sciences, Strathmore
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University) January 14, 2025 18 / 69
 Overview of other processors

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 Overview of other processors

Figure 15: A pin diagram 80486 courtesy Intel Corporation

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 Overview of other processors

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Sciences, Strathmore
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University) January 14, 2025 21 / 69
 Overview of other processors

Figure 17: The pin out of Pentium microprocessor courtesy Intel

Corporation

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 Organization of a Microprocessor-Based System

The figure 18 shows a microprocessor based system with the

main components including the system bus.

Figure 18: A microprocessor based system

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 Microprocessor Internal Architecture
As seen in figure 18 the microprocessor unit is made up of the
following internal components.
▶ Arithmetic Logic Unit: It performs arithmetic operations such
addition and subtraction and logic operation such as AND, OR,
and exclusive OR.
▶ Register array: It consists of various registers identified by
letters such as A,B,C,D,E,H and L. These registers are primarily
used to store data temporarily during the execution of a
program and are accessible to the user.
▶ Control unit: The control unit provides the necessary timing
and control signals to all operations in the microcomputer. It
also controls the flow of data between the microprocessor and
memory and other peripherals.
The memory can be divide into two categories namely RAM and
ROM.
The system is the communication path between the MPU and
its peripherals
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 How does the microprocessor work?

Assume there is a program and data already entered in the RAM

When the MPU is given a command to execute the program
which is stored in the memory sequentially
It fetches the first instruction from memory, it decodes it the
executes it.
This process is continued until all the instructions and executed.

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 Address bus
The address bus is group of 16 bit lines generally identified as
A0 toA15
The address bus are unidirectional data flow in one direction.
That is from the MPU to the peripheral devices

Figure 19: The Intel 8085 bus structure

The 8085 with 16 address lines is capable of addressing upto

216 = 65536 known as 64K locations
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 Data bus

The data bus is a group of 8 lines used for data flow

The lines are bidirectional - data can flow in both directions
The 8 data lines enable the MPU to manipulate an 8 bit data
ranging from 00H − FFH
The largest number that can appear on the data bus is
11111111 (25510 )

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Sciences, Strathmore
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 Control bus

The control bus is comprised of various single lines that carry

synchronization signals
However control lines are not grouped together like address or
data buses.
They are individual lines which provide pulses which control
operations
It is the MPU which generates these control signals especially
when it performs memory read or write operations
These signals are used to identify the devices with which the
MPU is communicating

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Sciences, Strathmore
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 Memory read operation

To communicate with memory, the MPU places a 16 bit address

on the address lines
The addresses are the decoded by an external logic circuit and
the memory is identified
The MPU sends a pulse called memory read as the control signal
It is the MPU which generates these control signals especially
when it performs memory read or write operations
The pulse activates the memory chip and the contents of this
memory are place on the 8 bit data bus and brought into the
MPU

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 Memory Unit

The memory is an essential component of a microcomputer.

It stores binary instructions and data for the microprocessor.
To communicate with memory the MPU should do the following.

▶ Select the chip

▶ Identify the register
▶ Read from or write int the register.

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 Flip-Flop or Latch as storage element

A memory unit is a circuit that can store bits-high or low.

Generally voltage levels or capacitive charge.
A flip flop or a latch is a memory unit.
Data is written through input data DIN . The chip is enable
through pin EN
The data is read through pin DOUT

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 Flip-Flop or Latch as storage element

Figure 20: Latch as a four bit register

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 4X8 bit register

Figure 21: 4 X 8 bit register

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 Flip-Flop or Latch

Figure 20 Illustrates the arrangement of latches or flip flop in a 4

bit register.
Each register can store a bit and can be activated by the WR
and RD so that they can be written or read from.
The EN signal is part of the address bit the is used to enable a
chip so that it can be written to or read from.

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 4X8 bit register

Figure 22: Two memory chips with four registers each and chip select

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 RAM and ROM Chips

Figure 23: R/W memory model and ROM model

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 Memory map and addresses

Intel 8085 which is 8-bit has 16 address lines.

It can identify upto 65536 memory registes each with 16 bit.
A memory map is a pictorial representation in which memory
devices are located in the entire range of addresses for each
memory device
Assume that a memory chip with 256 registers. Meaning we
need only 256 out of 65236.
The question is what should we do with the remaining address
line of the microprocessor.

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 Memory map and addresses illustration

Figure 25 shows a memory chip with 256 registers and eight I/O
lines.
Memory size of the chip is expressed as 256 x 8.
It has 8 address lines (A7 − A0 ), one chip select signal and two
control signals RD and WR
Only 8 address lines A7 − A0 are required to identify 256
memory registers.
The remaining eight lines A7 − A0 are connected to the chip
select line through inverters and the NAND gate.

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 Memory map and addresses illustration

Figure 24: Memory map for 256 register memory

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 Memory map and addresses illustration

Figure 25: Address map for 256 register memory

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 Example
Describe the address map with a diagram showing how 1K (1028x8)
memory is mapped. Show all the control signals

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 Memory word size

Memory devices are aailable in various word sizes (1,4 and 8)

and the size of the memory chip is generally specified in terms of
the total number of bits it can store.
For instance a memory chip of size 1024 x 4 has 1024 registers
and each register has 4 bits, thus it can store a total of 4096 =
1024x4 bits.

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 Example
Calculate the number of memory chips needed to design 8K byte
memory if the available chip size is 1024x1

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 Memory address maps for different microprocessors
The diagrams below shows different memory ranges for different
microprocessors

Figure 26: Memory maps

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 Memory address maps for different microprocessors

The diagrams below shows different memory ranges for different

microprocessors

Figure 27: Memory maps

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 Memory address maps for different microprocessors
The diagrams below shows different memory ranges for different
microprocessors

Figure 28: Memory maps

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 Memory address maps for different microprocessors

Memory maps used by Window XP

Figure 29: Memory maps

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 Memory address maps for different microprocessors
Some I/O locations in a typical personal computer.

Figure 30: Memory maps

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 Intel 8086 Microprocessor and Its Architecture

Before a program is written or any instruction investigated, the

internal configuration of the microprocessor must be known.
Internal visible registers are detailed.
From Intel 80186 there exist program visible registers in different
categories
Only Intel 80286 and above have program invisible registers used
to control and operate the protected memory system and other
features of the microprocessor.

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 Intel 8086 Microprocessor and Its Architecture
Intel 8086 Registers and programming model

Figure 31: Intel 8086 registers

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 Intel 8086 Microprocessor and Its Architecture
Intel 8086 Registers and programming model

Figure 32: Intel 8086 registers

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 Intel 8086 Microprocessor and Its Architecture
Intel 8086 Registers and programming model

Figure 33: Intel 8086 registers

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 Intel 8086 Microprocessor and Its Architecture
Intel 8086 Registers and programming model

The architecture of the family of Intel microprocessors is

presented simultaneously, as are the ways that the family
members address the memory system.
The addressing modes for this powerful family of
microprocessors are described for the real, protected, and flat
modes of operation.
Real mode memory (DOS memory) exists at locations
00000H–FFFFFH, the first 1M byte of the memory system, and
is present on all versions of the microprocessor.
Protected mode memory (Windows memory) exists at any
location in the entire protected memory system, but is available
only to the 80286–Core2, not to the earlier 8086 or 8088
microprocessors.

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 Intel 8086 Microprocessor and Its Architecture
Intel 8086 Registers and programming model

Protected mode memory for the 80286 contains 16M bytes; for
the 80386 Pentium, 4G bytes; and for the Pentium Pro through
the Core2, either 4G or 64G bytes.
The programming model of the 8086 through the Core2 is
considered to be program visible because its registers are used
during application programming and are specified by the
instructions.
Other registers, are considered to be program invisible because
they are not addressable directly during applications
programming

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 Intel 8086 Microprocessor and Its Architecture
Intel 8086 Registers and programming model

Figure 34: Intel 8086 registers compared to other registers

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 Intel 8086 Microprocessor and Its Architecture
Intel 8086 Registers and programming model
The earlier 8086, 8088, and 80286 contain 16-bit internal
architectures, a subset of the registers
The 80386 through the Core2 microprocessors contain full 32-bit
internal architectures.
The architectures of the earlier 8086 through the 80286 are fully
upward-compatible to the 80386 through the Core2
The programming model contains 8-, 16-, and 32-bit registers.
The Pentium 4 and Core2 also contain 64-bit registers when
operated in the 64-bit mode as illustrated in the programming
model.
The 8-bit registers are AH, AL, BH, BL, CH, CL, DH, and DL
and are referred to when an instruction is formed using these
two-letter designations.
For example, an ADD AL,AH instruction adds the 8-bit contents
of AH to AL. (Only AL changes due to this instruction.)
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 Intel 8086 Microprocessor and Its Architecture
Intel 8086 Registers and programming model
The earlier 8086, 8088, and 80286 contain 16-bit internal
architectures, a subset of the registers
The 80386 through the Core2 microprocessors contain full 32-bit
internal architectures.
The architectures of the earlier 8086 through the 80286 are fully
upward-compatible to the 80386 through the Core2
The programming model contains 8-, 16-, and 32-bit registers.
The Pentium 4 and Core2 also contain 64-bit registers when
operated in the 64-bit mode as illustrated in the programming
model.
The 8-bit registers are AH, AL, BH, BL, CH, CL, DH, and DL
and are referred to when an instruction is formed using these
two-letter designations.
For example, an ADD AL,AH instruction adds the 8-bit contents
of AH to AL. (Only AL changes due to this instruction.)
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 Intel 8086 Registers and programming model
The 16-bit registers are AX, BX, CX, DX, SP, BP, DI, SI, IP,
FLAGS, CS, DS, ES, SS, FS, and GS.
General Purpose Register
▶ AX Accumulator- A 16-bit register (AX), or as either of two
8-bit registers (AH and AL). The accumulator is used for
instructions such as multiplication, division, and some of the
adjustment instructions
▶ BX (base index) The BX register sometimes holds the offset
address of a location in the memory system in all versions of the
microprocessor.
▶ CX (counter) CX, CH, or CL, is a general-purpose register that
also holds the count for various instructions.
▶ DX DX, DH, or DL, is a general-purpose register that holds a
part of the result from a multiplication or part of the dividend
before a division. (data)

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 Intel 8086 Registers and programming model

The 16-bit registers are AX, BX, CX, DX, SP, BP, DI, SI, IP,
FLAGS, CS, DS, ES, SS, FS, and GS.
General Purpose Register
▶ BP (base pointer) BP, points to a memory location in all
versions of the microprocessor for memory data transfers.
▶ DI (destination index): DI, often addresses string destination
data for the string instructions
▶ SI- Source Index: The source index register often addresses
source string data for the string instructions

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 Intel 8086 Registers and programming model
Special Purpose Registers

IP- Instruction Pointer: The instruction pointer, which points to

the next instruction in a program, is used by the microprocessor
to find the next sequential instruction in a program located
within the code segment.
SP- Stack Pointer: SP addresses an area of memory called the
stack. The stack memory stores data through this pointer and is
explained later in the text with the instructions that address
stack data. This register is referred to as SP if used as a 16-bit
register

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 Intel 8086 Registers and programming model
Special Purpose Registers

Flags: FLAGS indicate the condition of the microprocessor and

control its operation

Figure 35: The EFLAG and FLAG register counts for the entire 8086 and
Pentium microprocessor family.

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 Special Purpose Registers
Intel 8086 Registers and programming model
C (carry): Carry holds the carry after addition or the borrow
after subtraction. The carry flag also indicates error conditions,
as dictated by some programs and procedures. This is especially
true of the DOS function calls.
P (parity): Parity is a logic 0 for odd parity and a logic 1 for
even parity. Parity is the count of ones in a number expressed as
even or odd. For example, if a number contains three binary one
bits, it has odd parity. If a number contains no one bits, it has
even parity.
A (auxiliary carry): The auxiliary carry holds the carry
(half-carry) after addition or the borrow after subtraction
between bit positions 3 and 4 of the result. This highly
specialized flag bit is tested by the DAA instructions to adjust
the value of AL after a BCD addition or subtraction.
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 Intel 8086 Registers and programming model
Special Purpose Registers
Z (zero) The zero flag shows that the result of an arithmetic or
logic operation is zero. If , the result is zero; if Z = 0 , the
result is not zero. This may be confusing, but that is how Intel
decided to name this flag.
S (sign): The sign flag holds the arithmetic sign of the result
after an arithmetic or logic instruction executes. If S = 1 , the
sign bit (leftmost bit of a number) is set or negative; if S = 0 ,
the sign bit is cleared or positive.
T (trap): If the T flag is enabled (1), the microprocessor
interrupts the flow of the program on conditions as indicated by
the debug registers and control registers. If the T flag is a logic
0, the trapping (debugging) feature is disabled. The Visual C++
debugging tool uses the trap feature and debug registers to
debug faulty software.
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 Intel 8086 Registers and programming model
Special Purpose Registers

I (interrupt): The interrupt flag controls the operation of the

INTR (interrupt request) input pin. If I = 1 , the INTR pin is
enabled; if , the INTR pin is disabled. The state of the I flag bit
is controlled by the STI (set I flag) and CLI (clear I flag)
instructions.
D (direction): The direction flag selects either the increment or
decrement mode for the DI and/or SI registers during string
instructions. If D = 1 the registers are automatically
decremented; if D = 0 , , the registers are automatically
incremented. The D flag is set with the STD (set direction) and
cleared with the CLD (clear direction) instructions.

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 Intel 8086 Registers and programming model
Special Purpose Registers

O (overflow): Overflows occur when signed numbers are added

or subtracted. An overflow indicates that the result has exceeded
the capacity of the machine. For example, if 7FH ( +127 +1) is
added—using an 8-bit addition—to 01H (+1), the result is 80H
(–128).

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 Intel 8086 Registers and programming model
Special Purpose Registers: Segment Registers.
Additional registers, called segment registers, generate memory
addresses when combined with other registers in the
microprocessor.
There are either four or six segment registers in various versions
of the microprocessor
▶ Code Segment (CS): The code segment is a section of
memory that holds the code (programs and procedures) used by
the microprocessor. The code segment register defines the
starting address of the section of memory holding code.The
code segment is limited to 64K bytes in the 8088–80286, and
4G bytes in the 80386 and above.
▶ Data Segment(DS): The data segment is a section of memory
that contains most data used by a program. Data are accessed
in the data segment by an offset address or the contents of
other registers that hold the offset address. , the length is
limited to 64K bytes in the 8086–80286, and 4G bytes in the
Lec: Mourice Ojijo (School of Computing and Engineering
BEE 4206:Microprocessor
Sciences, Strathmore
Systems
University) January 14, 2025 66 / 69
 Intel 8086 Registers and programming model
Special Purpose Registers: Segment Registers.

Extra Segment (ES): The extra segment is an additional data

segment that is used by some of the string instructions to hold
destination data.
Stack Segment (SS): The stack segment defines the area of
memory used for the stack. The stack entry point is determined
by the stack segment and stack pointer registers. The BP
register also addresses data within the stack segment.

Lec: Mourice Ojijo (School of Computing and Engineering

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 Intel 8086 Registers and programming model
REAL MODE MEMORY ADDRESSING

The 80286 and above operate in either the real or protected

mode. Only the 8086 and 8088 operate exclusively in the real
mode. In the 64-bit operation mode of the Pentium 4 and
Core2, there is no real mode operation.
Real mode operation allows the microprocessor to address only
the first 1M byte of memory space—even if it is the Pentium 4
or Core2 microprocessor
Note that the first 1M byte of memory is called the real memory,
conventional memory, or DOS memory system.
The DOS operating system requires that the microprocessor
operates in the real mode.
Windows does not use the real mode.

Lec: Mourice Ojijo (School of Computing and Engineering

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University) January 14, 2025 68 / 69
 Intel 8086 Registers and programming model
Segments and Offsets

A combination of a segment address and an offset address

accesses a memory location in the real mode.
All real mode memory addresses must consist of a segment
address plus an offset address.
The segment address, located within one of the segment
registers, defines the beginning address of any 64K-byte memory
segment.
The offset address selects any location within the 64K byte
memory segment.
Segments in the real mode always have a length of 64K bytes.

Lec: Mourice Ojijo (School of Computing and Engineering

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University) January 14, 2025 69 / 69