1. What are direct addressing mode and immediate addressing mode?

Explain
with the instruction set example in 8085 microprocessors.
In the 8085 microprocessor, addressing modes define how the operand (data to be used) is
specified in an instruction. Let's explain the two modes: Direct Addressing Mode and Immediate
Addressing Mode, with examples.

1. Direct Addressing Mode

In direct addressing mode, the address of the operand (data) is explicitly specified in the instruction.
The microprocessor fetches the data from the memory location given in the instruction.

 Example:

 LDA 2500H

Explanation:

o Here, LDA (Load Accumulator) is the instruction to load a value into the accumulator.

o 2500H is the direct memory address (in hexadecimal) where the data to be loaded is
stored. The microprocessor fetches the data from this memory location and stores it in
the accumulator (A register).

Summary: In direct addressing, the operand is stored at a specific memory location, and that
location is provided directly in the instruction.

2. Immediate Addressing Mode

In immediate addressing mode, the operand (data) is specified explicitly in the instruction itself,
rather than from a memory location.

 Example:

 MVI A, 32H

Explanation:

o MVI (Move Immediate) is the instruction to load a value into a register.

o A is the destination register (Accumulator).

o 32H is the immediate data (in hexadecimal) to be loaded into the accumulator.

Summary: In immediate addressing mode, the operand is part of the instruction, and the
microprocessor doesn't need to fetch data from memory.

Key Differences:

 Direct Addressing Mode: Operand is in memory; the instruction specifies the memory location.

 Immediate Addressing Mode: Operand is part of the instruction itself.

2. Calculate the total time delay for the execution of the instructions as shown below. Consider the
internal frequency of the microprocessor to be 2 MHz

MVI C,05H

LOOP: DCR C

JNZ LOOP

RST3

3. Explain the operation of the instruction: RLC

The instruction RLC (Rotate Accumulator Left) in the 8085 microprocessor rotates the contents
of the accumulator one bit to the left, with the carry involved in the rotation.

Here's a breakdown of the operation:

Operation:
 Accumulator (A): The 8-bit contents of the accumulator are shifted left by one position.
 Bit 7 (MSB): The most significant bit (MSB) is moved to both:
o Bit 0 (LSB) (the least significant bit position), and
o The Carry flag (CY) in the flag register.
Detailed Explanation:
1. The bit in position 7 (MSB) moves to the carry flag (CY).
2. The bit in position 7 also moves to position 0 (LSB) of the accumulator.
3. All other bits in the accumulator shift one position to the left.
Example:
Let’s assume the contents of the accumulator (A) are 10101101 and the carry flag (CY) is 0.
 Before RLC:
o Accumulator (A) = 10101101
o Carry flag (CY) = 0
 After RLC:
o Accumulator (A) = 01011011
(The MSB 1 goes to the LSB, and all bits are shifted left.)
o Carry flag (CY) = 1
(The original MSB 1 is copied to the carry flag.)
Key Points:
 The instruction does not affect any other flags except the carry flag (CY).
 This is a circular shift, where the bit shifted out from the MSB wraps around to the LSB.
4. Explain in detail the 8085 addressing modes with examples.

The 8085 microprocessor uses addressing modes to specify how the operand (data) is selected
in an instruction. Each mode provides flexibility in accessing operands, which can be stored in
registers, memory locations, or within the instruction itself.
Addressing Modes of 8085:
There are five main types of addressing modes in the 8085 microprocessor:
1. Immediate Addressing Mode
2. Register Addressing Mode
3. Direct Addressing Mode
4. Indirect Addressing Mode
5. Implicit (Implied) Addressing Mode

1. Immediate Addressing Mode

In this mode, the operand (data) is specified immediately in the instruction itself, i.e., the data is
part of the instruction. The microprocessor does not need to fetch it from memory.
 Example:
 MVI A, 32H
o Explanation: MVI A, 32H moves the immediate value 32H (hexadecimal) into the
accumulator (register A).
o The data 32H is present in the instruction itself.

2. Register Addressing Mode

In register addressing mode, the operand is located in one of the registers of the
microprocessor. The instruction specifies the register where the data is stored.
 Example:
 MOV A, B
o Explanation: MOV A, B moves the contents of register B to register A.
o No memory access is needed; the data is transferred between the internal registers of
the microprocessor.

3. Direct Addressing Mode

In direct addressing mode, the instruction specifies the memory address where the operand
(data) is stored. The 16-bit memory address is provided directly in the instruction, and the
microprocessor fetches the operand from that memory location.
 Example:
 LDA 2500H
o Explanation: LDA 2500H loads the data from the memory location 2500H into the
accumulator.
o Here, 2500H is the direct memory address where the operand is stored.

4. Indirect Addressing Mode

In indirect addressing mode, the address of the operand is not specified directly in the
instruction. Instead, the instruction specifies a register pair that contains the address of the
 memory location where the operand is stored. The microprocessor uses the content of the
register pair as a pointer to the memory location.
 Example:
 MOV A, M
o Explanation: MOV A, M moves the data from the memory location pointed to by the H-L
register pair into the accumulator (A). Here, the content of the H-L register pair
(considered as a 16-bit address) is used to point to the memory location.
o If H-L = 2400H, then the data at memory location 2400H is copied to the accumulator.

5. Implicit (Implied) Addressing Mode

In implicit addressing mode, the operand is implicitly specified by the operation itself. The
instruction does not explicitly mention the operand because it is predefined by the instruction.
Usually, these instructions operate on specific registers or flags.
 Example:
 CMA
o Explanation: CMA (Complement Accumulator) takes the complement of the contents of
the accumulator. The operation is implied on the accumulator (A), and no explicit
operand is provided in the instruction.

Summary of Addressing Modes:

Addressing Explanation
Operand Example
Mode
Immediate Data is provided MVI A, Loads immediate data 32H
Addressing in the instruction. 32H into the accumulator.

Register Operand is in a MOV A, Moves the content of

Addressing register. B register B into register A.

Loads the data from

Direct Address is LDA memory location 2500H
Addressing specified directly. 2500H into A.

Loads data from the

Indirect Address is in a MOV A, memory location pointed
Addressing register pair. M by H-L into A.

Implicit Operand is Complements the data in

CMA the accumulator.
Addressing implied.
These addressing modes allow the 8085 microprocessor to handle data flexibly, either directly
from registers or from memory locations specified in various ways.
 SHLD 5 OF MR MR MW MW

LXI 3 OF MR MR

5. If CLK frequency is 3.5 MHZ for 8085, find the execution time for MOV A, B
and LDA 8700H.
To calculate the execution time of instructions in the 8085 microprocessor, you need to know two
things:

1. The number of machine cycles required by the instruction.

2. The clock period (which depends on the clock frequency).
Step 1: Determine the Clock Period

Step 2: Analyze the Instructions

1. MOV A, B (Register to Register Transfer)
 Instruction type: 1-byte instruction
 Machine cycles: 1
 T-states per cycle: 4 T-states
The number of T-states required by the MOV A, B instruction is 4.
 2. LDA 8700H (Load Accumulator Direct)
 Instruction type: 3-byte instruction (since the memory address 8700H is specified).
 Machine cycles: 4
 T-states per cycle:
o Opcode fetch: 4 T-states
o Memory read (low address byte): 3 T-states
o Memory read (high address byte): 3 T-states
o Memory read (data): 3 T-states
Total T-states = 4 + 3 + 3 + 3 = 13 T-states

Final Results:
 MOV A, B execution time = 1.14 microseconds
 LDA 8700H execution time = 3.71 microseconds

6. What is a subroutine?

 A subroutine is a set of instructions designed to perform a specific task or operation

that can be called and executed from different parts of a program.
 It allows for code reuse, making programs more organized, efficient, and easier to
maintain.
 Subroutines are typically used for tasks that need to be performed multiple times in a
program, such as mathematical calculations, data manipulations, or I/O operations.
 In the context of the 8085 microprocessor, subroutines can be invoked using the CALL
instruction and can return to the point from where they were called using the RET
instruction.
 Stack Usage: The return address is stored on the stack, enabling multiple subroutines to be
nested.
Stack in Subroutine:
The stack plays a crucial role in subroutine calls:
 When a CALL instruction is executed, the program counter (PC), which holds the address of the
next instruction, is pushed onto the stack.
 Upon RET execution, the PC is popped from the stack, and the program continues from the
return address.
 

7. What is the use of CALL and RET instructions? Give an example each for CALL and RET
instruction. Ans:- (SAME AS 6)

Classification of Interrupts
Maskable Non-Maskable
Maskable interrupts are those interrupts which The interrupts which are always in enabled mode
can be enabled or disabled. are called non-maskable interrupts.
RST 7.5 RST 6.5 RST 5.5 INTR TRAP

Vectored Non-Vectored
The interrupts which have fixed memory location The interrupts which don't have fixed memory
for transfer of control from normal execution. location for transfer of control from normal
Each vectored interrupt points to the particular execution.
location in memory.
RST 7.5 RST 6.5 RST 5.5 TRAP INTR

Edge Triggered Level Triggered

The interrupts which are triggered at leading or The interrupts which are triggered at high or low
trailing edge are called edge triggered interrupts. level are called level triggered interrupts.
RST 7.5 TRAP RST 6.5 RST 5.5 INTR TRAP
Priority of interrupts: Interrupt Priority
TRAP > RST 7.5 > RST 6.5 > RST 5.5 > INTR
8. What is vectored and Non-Vectored interrupt?
Interrupts are used in microprocessors to allow the CPU to respond to external events
asynchronously, such as I/O operations, hardware faults, or other important tasks that need
immediate attention.

1. Vectored Interrupt
In a Vectored Interrupt, the address of the interrupt service routine (ISR) is predefined and is
automatically provided by the hardware as soon as the interrupt occurs. When the interrupt is
triggered, the processor immediately jumps to a specific address, known as the interrupt vector,
where the ISR is located.

2. Non-Vectored Interrupt
In a Non-Vectored Interrupt, the address of the interrupt service routine (ISR) is not predefined.
Instead, the processor requires the external device to provide the address of the ISR, usually by
sending the address through data lines or by using some additional mechanism. The processor
does not know where to jump for the ISR without receiving this information.

9. What is TRAP and its significance?

Significance of TRAP
Emergency Handling: TRAP is used for handling critical or emergency situations in a system, such
as: Power failure. System shutdown. High-priority errors.
Uninterruptible: Since TRAP cannot be masked or ignored, it ensures that the processor always
responds to critical conditions.
Reliable Interrupt: Its dual nature (level and edge sensitivity) ensures reliability, reducing the
chance of missing the interrupt.
Fixed ISR Location: The predefined vector address (0024H) simplifies the implementation of the
interrupt routine.

Example:
A TRAP interrupt can be used in systems where:
A power failure signal triggers the processor to save critical data to non-volatile memory before
shutting down.

10.Draw and explain the internal architecture of 8254.

 Intel 8254 Programmable Interval Timer (PIT) - Summary of Internal Architecture
The Intel 8254 is a programmable timer used in microprocessor systems for tasks like event
counting, generating accurate time delays, and producing clock pulses. It contains three
independent 16-bit counters that can operate in various modes.
Key Components:
1. Three Independent 16-bit Counters:
o Counters 0, 1, and 2 operate independently as down-counters.
o Each counter has its own clock (CLK), gate (GATE), and output (OUT) pins.
o Registers:
 Counter Register (CR): Stores the preset count value.
 Output Latch Register (OLR): Holds the latched count value for reading.
2. Control Word Register:
o Configures the counters, specifying:
 Which counter is being programmed.
 Operation mode (six modes available, e.g., interrupt on terminal count, rate
generator).
 Whether the counter operates in binary or BCD.
 Selection of read/write for LSB, MSB, or both.
3. Data Bus Buffer:
o An 8-bit bidirectional buffer that interfaces with the system's data bus.
 o Allows the CPU to read from or write to the counters.
4. Read/Write Logic:
o Manages data transfer between the CPU and the counters/control registers.
o Uses RD, WR, A0, and A1 lines to address specific counters.
5. Control Logic:
o Manages clock and gate inputs, determines the counter mode, and generates output
signals.
o Controls the latching process for reading the current count without stopping the
counter.
Operational Modes:
 Mode 0: Interrupt on terminal count.
 Mode 1: Programmable monostable.
 Mode 2: Rate generator.
 Mode 3: Square wave generator.
 Mode 4: Software triggered strobe.
 Mode 5: Hardware triggered strobe.

11. Draw the timing diagram of 8000: SHLD 9050H.

12.Write a program to subtract two 16-bit numbers.

Example Program: Subtract Two 16-bit Numbers

Let’s assume the two 16-bit numbers to be subtracted are stored in memory locations:
 Number 1 (16-bit): stored in memory locations 5000H (lower byte) and 5001H (upper byte).
 Number 2 (16-bit): stored in memory locations 5002H (lower byte) and 5003H (upper byte).
 The result will be stored in 5004H (lower byte) and 5005H (upper byte).

Program:
LXI H, 5000H ; Load HL with address 5000H (starting address of Number 1)
MOV A, M ; Load A with the lower byte of Number 1 (5000H)
INX H ; Increment HL to point to 5001H (upper byte of Number 1)
MOV B, M ; Store upper byte of Number 1 in register B

LXI H, 5002H ; Load HL with address 5002H (starting address of Number 2)

MOV C, M ; Load C with the lower byte of Number 2 (5002H)
INX H ; Increment HL to point to 5003H (upper byte of Number 2)
MOV D, M ; Store upper byte of Number 2 in register D

; Subtract lower bytes (A - C)

MOV A, M ; Move the lower byte of Number 1 into the accumulator
SUB C ; Subtract lower byte of Number 2 from lower byte of Number

Subtract Two 8-bit Numbers

MVI D, 00H ; Clear the D register (for borrow flag, if needed)

LDA 4000H ; Load the first number from memory location 4000H into accumulator A
MOV B, A ; Copy the value in accumulator to register B (store the minuend)

LDA 4001H ; Load the second number from memory location 4001H into accumulator A
SUB B ; Subtract the value in register B (minuend) from accumulator A (subtrahend)

STA 4002H ; Store the result in memory location 4002H

HLT ; Halt the program

13. Illustrate a (256 x 8) bytes memory register considering the chip select to be the active low.
Draw the hardware and specify the possible address range.
14. Draw and explain the table for 8085 that how IO/M’ read and write, opcode fetch and interrupt
acknowledge are selected using select lines.
 15.What is DMA?
Direct Memory Access (DMA) uses hardware for accessing the memory, that hardware is called
a DMA Controller. It has the work of transferring the data between Input Output devices and
main memory with very less interaction with the processor. The direct Memory Access
Controller is a control unit, which has the work of transferring data.

The DMA controller registers have three registers as follows.

 Address register – It contains the address to specify the desired location in memory.
 Word count register – It contains the number of words to be transferred.
 Control register – It specifies the transfer mode.

Explanation: The CPU initializes the DMA by sending the given information through the data
bus.
 The starting address of the memory block where the data is available (to read) or where data
are to be stored (to write).
 It also sends word count which is the number of words in the memory block to be read or
written.
 Control to define the mode of transfer such as read or write.
 A control to begin the DMA transfer

Applications:

 Used in systems that require high-speed data transfer, such as:

o Hard disk data transfers.

o Audio or video streaming.

 o Network communications.

o High-speed I/O operations (e.g., USB, Ethernet).

Advantages of DMA Controller

 Data Memory Access speeds up memory operations and data transfer.

 CPU is not involved while transferring data.

 DMA requires very few clock cycles while transferring data.

 DMA distributes workload very appropriately.

 DMA helps the CPU in decreasing its load.

16.Explain different methods by which delay can be generated.

Methods to Generate Delay in Microprocessor Systems

In microprocessor systems like the 8085, delays are often required for synchronizing with
external hardware or for timing-specific tasks. Delays can be created using the following
methods:

1. Software Delay (Loop-based Delay)

 A simple delay can be generated by writing a loop in the program that repeatedly executes a set
of instructions without performing any actual work.
 The execution of these instructions takes a specific number of clock cycles, which creates a
delay.
 This loop takes time based on the number of iterations and the clock frequency of the system.
By adjusting the loop count, different delay lengths can be achieved.

2. Hardware Delay Using Timers
 Timers or Counters like the Intel 8253/8254 Programmable Interval Timer (PIT) can be used to
generate accurate delays.
 The timer is programmed with a specific value, and it counts down to zero, generating a signal
or interrupt when the delay period is over.

3. Instruction-Based Delay
 Specific instructions that inherently take longer to execute can be used for creating a delay. For
example, instructions like NOP (No Operation), which takes a few clock cycles to execute
without doing anything, can be used to create small delays.

4. Interrupt-based Delay
 Some microprocessors use interrupts from external devices to create delays. A periodic
interrupt (like a timer interrupt) can be used to create delays by counting how many times the
interrupt occurs.

5. External Hardware (Crystal Oscillator)
 External circuits like a crystal oscillator can be used to generate accurate timing delays. The
microprocessor can wait for a specific signal or pulse from the oscillator to create a delay.
 For example, connecting an external crystal oscillator to a timer/counter IC can produce highly
accurate delays by counting the number of oscillations.

Summary of Delay Methods:

1. Software Delay (Loops): Simple, adjustable using loops but not highly precise.
2. Hardware Delay (Timers): Uses timers like 8254 for precise delays.
3. Instruction-based Delay: Uses instructions like NOP for very short delays.
4. Interrupt-based Delay: Uses interrupts to create longer, periodic delays.
5. External Hardware: Uses external circuits (e.g., crystal oscillators) for highly accurate delays.

17. Write simple programs to generate delay using these different methods.

18.Write a program (8085) to add two 16-bit numbers.

19.Mention the purpose of SID and SOD lines. Explain the priority of interrupts
in 8085.

SID and SOD Lines in 8085 Microprocessor

The 8085 microprocessor has two important communication lines, SID and SOD, which are used
for serial communication:
1. SID (Serial Input Data):
o This is a serial input line.
o It is used to receive data bit by bit serially from an external device.
o The microprocessor reads the bit on the SID line using the RIM (Read Interrupt Mask)
instruction.
2. SOD (Serial Output Data):
o This is a serial output line.
o It is used to send data bit by bit serially to an external device.
o The microprocessor writes the bit to the SOD line using the SIM (Set Interrupt Mask)
instruction.
Use Case:
 These lines are useful in situations where serial communication is needed, such as with devices
like serial ports, modems, and sensors that use serial data transfer.

Priority of Interrupts in 8085 Microprocessor

In the 8085 microprocessor, there are five interrupt lines. The interrupts can be vectored or
non-vectored, and they have a fixed priority order, which determines which interrupt is serviced
first if multiple interrupts occur simultaneously.
The priority of interrupts in 8085 (from highest to lowest) is as follows:
1. TRAP (Highest Priority):
o Type: Non-maskable, vectored interrupt.
o Vector Address: 0024H.
o Purpose: Used for critical events like power failure or emergency stop.
o Characteristics: Cannot be disabled or masked. Once triggered, it cannot be ignored.
2. RST 7.5:
o Type: Maskable, vectored interrupt.
o Vector Address: 003C H.
o Purpose: Often used for important but not critical tasks like handling external
peripherals.
o Characteristics: Can be masked or enabled/disabled by the microprocessor. It has a
higher priority over RST 6.5 and RST 5.5.
3. RST 6.5:
o Type: Maskable, vectored interrupt.
o Vector Address: 0034 H.
o Purpose: Typically used for peripheral device servicing.
o Characteristics: Lower priority than RST 7.5 but higher than RST 5.5.
4. RST 5.5:
 o Type: Maskable, vectored interrupt.
o Vector Address: 002C H.
o Purpose: Used for less critical device servicing or events.
o Characteristics: Can be masked. Lowest priority among RST 7.5, 6.5, and 5.5.
5. INTR (Lowest Priority):
o Type: Non-vectored, maskable interrupt.
o Vector Address: Determined by the interrupting device.
o Purpose: General-purpose interrupt used when the interrupting device provides its own
ISR address.
o Characteristics: Requires the microprocessor to fetch the address of the interrupt
service routine (ISR) from the device. It has the lowest priority among all interrupts.

Summary of Interrupt Priorities (Highest to Lowest):

1. TRAP (Non-maskable, vectored).
2. RST 7.5 (Maskable, vectored).
3. RST 6.5 (Maskable, vectored).
4. RST 5.5 (Maskable, vectored).
5. INTR (Maskable, non-vectored).
TRAP is always serviced first if multiple interrupts occur, while INTR has the lowest priority. The
microprocessor checks these interrupts in this order and responds based on the highest-priority
interrupt that is active.
20.What is stack memory? Explain the PUSH, POP instruction.
 21.Write a program to search 40H in the given memory address set. If found
terminate the program. 8000: 01; 8001:32; 8002:40; 8003: 78

LXI H, 8000H ; Load HL register pair with starting address 8000H

MVI B, 04H ; Set counter B to 4 (number of memory locations to search)

SEARCH_LOOP:
MOV A, M ; Move the content of the memory (pointed by HL) into register A
CPI 40H ; Compare the content of A with 40H
JZ FOUND ; If A = 40H, jump to FOUND label
INX H ; Increment HL to point to the next memory address
DCR B ; Decrement the counter
JNZ SEARCH_LOOP ; If counter B is not zero, repeat the loop

HLT ; Halt if 40H is not found after searching all locations

FOUND:
HLT ; Halt the program if 40H is found

Explanation:

1. LXI H, 8000H: Loads the starting memory address 8000H into the HL register pair.
2. MVI B, 04H: Initializes the counter B with 4 because we need to check four memory locations
(8000H, 8001H, 8002H, 8003H).
3. MOV A, M: Moves the content of the memory location pointed to by HL into the accumulator A.
4. CPI 40H: Compares the value in A with 40H.
o If equal, the Zero (Z) flag is set, and the program jumps to the FOUND label.
5. INX H: Increments HL to point to the next memory location.
6. DCR B: Decreases the counter B by 1.
7. JNZ SEARCH_LOOP: If B is not zero, it jumps back to the SEARCH_LOOP to check the next
memory location.
8. HLT: If 40H is found, or if all locations have been checked and 40H was not found, the program
halts.
This program checks the memory from 8000H to 8003H and halts if 40H is found at any of those
locations.
22.Write a program to store first 10 Fibonacci numbers to memory address
starting from 9050H.
23.Define all the flags in 8085.

The purpose of flags in the 8085 microprocessor is to indicate the outcome of an operation
performed by the Arithmetic Logic Unit (ALU). These flags are bits in the flag register that reflect
the status of the processor after an arithmetic or logical operation, influencing subsequent
instructions (e.g., conditional jumps).

Flags in 8085
The 8085 flag register is an 8-bit register, but only 5 bits are used as flags:
Bit Name Description

D7 Sign Flag (S) Indicates the sign of the result.

D6 Unused Not used in the 8085.

D5 Zero Flag (Z) Set if the result is zero.

D4 Auxiliary Carry (AC) Used for BCD operations.

D3 Unused Not used in the 8085.

D2 Parity Flag (P) Indicates even or odd parity.

D1 Unused Not used in the 8085.

D0 Carry Flag (CY) Indicates a carry or borrow.

Detailed Explanation of Flags

1. Sign Flag (S)
o Purpose: Indicates the sign of the result after an operation.
o Set: When the Most Significant Bit (MSB) of the result is 1 (negative number in 2's
complement form).
o Reset: When the MSB is 0 (positive number).
o Example: After subtracting 10−20=−1010 - 20 = -1010−20=−10, the sign flag is set.
2. Zero Flag (Z)
o Purpose: Indicates whether the result of an operation is zero.
o Set: When the result is zero.
o Reset: When the result is non-zero.
o Example: After 5−5=05 - 5 = 05−5=0, the zero flag is set.
3. Auxiliary Carry Flag (AC)
o Purpose: Indicates a carry from bit 3 to bit 4 during operations. Used primarily for
Binary-Coded Decimal (BCD) arithmetic.
o Set: When there is a carry from bit 3 to bit 4.
o Reset: When there is no carry.
o Example: In 09H+07H=10H09H + 07H = 10H09H+07H=10H, the auxiliary carry flag is set.
 4. Parity Flag (P)
o Purpose: Indicates whether the number of 1s in the result is even or odd.
o Set: When the parity (number of 1s) is even.
o Reset: When the parity is odd.
o Example: After 101001101010 011010100110, the parity flag is set because there are 6
ones (even parity).
5. Carry Flag (CY)
o Purpose: Indicates a carry out of the most significant bit or a borrow during subtraction.
o Set: When there is a carry or borrow.
o Reset: When there is no carry or borrow.
o Example: In FFH+01H=100HFFH + 01H = 100HFFH+01H=100H, the carry flag is set.

Summary Table
Flag Name Bit Set Condition

Sign (S) 7 Result is negative (MSB = 1).

Zero (Z) 6 Result is zero.

Auxiliary Carry (AC) 4 Carry from bit 3 to bit 4 (BCD operations).

Parity (P) 2 Result has even parity (even number of 1s).

Carry (CY) 0 Carry/borrow out of MSB.

24.What is stack memory? (same as 20)

25. Explain the operation of the instruction set: 8000: LXI B, 9200H
(2nd pdf)

26.Draw the internal architecture of the 8255. In the 8255 mode 0

configuration, port A & B acts as an output port, and port C acts as an input
port. Write down the control word. (output port: 0; input port: 1)
27.State the function of 8085 instructions JP, JPE, JPO, JNZ.

1. JP (Jump if Positive)
Function: Transfers program control to the specified memory address if the Sign Flag (S) is reset
(i.e., S = 0). This occurs when the result of the previous operation is positive or zero.
 Syntax: JP address
 Condition: If S=0S = 0S=0, jump to the specified address.
 Example: If the result of an arithmetic operation is positive (e.g., the MSB of the accumulator is
0), this instruction jumps to the specified address.

2. JPE (Jump if Parity Even)

Function: Transfers program control to the specified memory address if the Parity Flag (P) is set
(i.e., P = 1). This indicates the parity of the result is even.
 Syntax: JPE address
 Condition: If P=1P = 1P=1, jump to the specified address.
 Example: If the result of an operation has an even number of 1s in binary, this instruction jumps
to the specified address.

3. JPO (Jump if Parity Odd)

Function: Transfers program control to the specified memory address if the Parity Flag (P) is
reset (i.e., P = 0). This indicates the parity of the result is odd.
 Syntax: JPO address
 Condition: If P=0P = 0P=0, jump to the specified address.
 Example: If the result of an operation has an odd number of 1s in binary, this instruction jumps
to the specified address.

4. JNZ (Jump if Not Zero)

Function: Transfers program control to the specified memory address if the Zero Flag (Z) is reset
(i.e., Z = 0). This occurs when the result of the previous operation is nonzero.
 Syntax: JNZ address
 Condition: If Z=0Z = 0Z=0, jump to the specified address.
 Example: After an arithmetic operation, if the result is not zero, this instruction jumps to the
specified address.

Summary Table
Instruction Condition Flag Involved Description

JP S=0S = 0S=0 Sign Flag (S) Jump if the result is positive.

JPE P=1P = 1P=1 Parity Flag (P) Jump if the parity is even.

JPO P=0P = 0P=0 Parity Flag (P) Jump if the parity is odd.

JNZ Z=0Z = 0Z=0 Zero Flag (Z) Jump if the result is not zero.

28.Mention the types of addressing modes of 8085 microprocessor (same as 4)

29.Draw the timing diagram of 9000: LXI B, 8000H

30.Explain the programming model of the 8085 microprocessor along with all
its segments.

The programming model of the 8085 microprocessor is a simplified representation of the

registers, memory, and data flow components used during programming. It shows how data is
managed and manipulated within the processor. Below is a detailed explanation:

Programming Model of 8085 Microprocessor

The 8085 programming model consists of:
1. Registers
2. Accumulator
3. Flags
4. Program Counter (PC)
5. Stack Pointer (SP)
6. Instruction Register and Decoder
7. Memory and I/O Addressing

1. Registers
 Definition: Registers are small storage units inside the microprocessor that hold data
temporarily for processing.
 Types of Registers:
o General-Purpose Registers: B, C, D, E, H, L (8-bit registers).
 Can be used individually or as 16-bit register pairs (BC, DE, HL) for operations
like addition, subtraction, and memory addressing.
o Temporary Register: Used internally by the processor; not accessible to the
programmer.

2. Accumulator (A Register)
 Definition: An 8-bit special-purpose register used for arithmetic, logic, and data transfer
operations.
 Function:
o Acts as the primary register for storing intermediate results.
o Works with the ALU for arithmetic and logical operations.

3. Flags
 Definition: A 5-bit register that reflects the outcome of operations.
 Components:
o Sign Flag (S): Set if the result is negative.
o Zero Flag (Z): Set if the result is zero.
o Auxiliary Carry Flag (AC): Set if there is a carry from bit 3 to bit 4 (used in BCD
operations).
o Parity Flag (P): Set if the number of 1s in the result is even.
o Carry Flag (CY): Set if there is a carry out or borrow in the result.

4. Program Counter (PC)

 Definition: A 16-bit register that holds the address of the next instruction to be executed.
 Function:
o Automatically increments after fetching each instruction.
o Used to sequence the execution of instructions in the program.

5. Stack Pointer (SP)

 Definition: A 16-bit register that holds the address of the top of the stack.
 Function:
o Points to the memory location where temporary data (like return addresses, register
content) is stored during function calls or interrupts.

6. Instruction Register and Decoder

 Instruction Register: Holds the current instruction fetched from memory.
 Decoder: Decodes the instruction and generates the necessary control signals for execution.
 7. Memory and I/O Addressing
 Memory Address Register (MAR): Holds the address of the memory location being accessed.
 Memory Buffer Register (MBR): Temporarily holds data being transferred to or from memory.
 I/O Addressing: Uses an 8-bit address space to access input/output ports.

Diagram: Programming Model of 8085

Here is a description of the layout:
1. General Purpose Registers
o B, C, D, E, H, L (can be paired as BC, DE, HL).
2. Special Purpose Registers
o Accumulator (A).
o Flag Register (S, Z, AC, P, CY).
3. Pointer Registers
o Program Counter (PC).
o Stack Pointer (SP).

Summary Table
Component Size Function

Accumulator (A) 8-bit Arithmetic, logic, and data transfer operations.

General Registers 8-bit Temporary data storage and manipulation.

Program Counter 16-bit Holds address of the next instruction.

Stack Pointer 16-bit Points to the top of the stack.

Flags Register 5-bit Reflects outcomes of operations (S, Z, AC, P, CY).

Instruction Decoder N/A Decodes fetched instructions.

31.What is the purpose of flag? Define all the flags in 8085. (same as 23)

32.Illustrate a (512 x 8) bytes memory register considering the chip select to

be the active low. Draw the hardware and specify the possible address
range.
33.Draw the timing diagram of the instruction 9050: MVI A, 20H.
34.Write a program to add the ten 8-bit numbers stored at the memory
addresses, 9000: 01H, 9001:02H, .…. 9009: 09H.
35. Explain the operation of the instruction: RAR
 36.Draw and explain the table for 8085 that how IO/M’ read and write, opcode
fetch and interrupt acknowledge are selected using select lines.
37.Describe the pin description of the 8085 with a suitable diagram.
38.Calculate the total time delay for the execution of the instructions as shown
below. Consider the internal frequency of the microprocessor to be 2 MHz
LXI B, 2384H

LOOP: DCX B

MOV A, C

ORA B

JNZ LOOP

39.Write a program to search 80H in the given memory address set. If found
terminate the program. 9000: 01; 9001:80; 9002:40; 9003: 78
MVI H, 90H ; Load HL pair with starting memory address 9000H (90H in H and 00H in L)

MVI L, 00H

MVI D, 80H ; Load register D with the value to search for (80H)

SEARCH:

MOV A, M ; Move the content of the memory at HL into accumulator A

CMP D ; Compare the value in A with 80H (value in D register)

JZ FOUND ; If A == 80H, jump to FOUND (end the program)

INX HL ; Increment HL to point to the next memory address

MOV A, L ; Move L register (address part) into A (used for comparison)

CPI 03H ; Check if we have checked all 4 locations (9000-9003)

JZ NOT_FOUND ; If we have checked all, jump to NOT_FOUND

JMP SEARCH ; Continue searching in the next memory location

FOUND:

HLT ; Terminate the program (halt)

NOT_FOUND:

HLT ; Terminate the program (halt, after checking all locations)

Explanation:

1. MVI H, 90H: Load H register with 90H (the high byte of the starting address 9000H).

2. MVI L, 00H: Load L register with 00H (the low byte of the starting address 9000H).

3. MVI D, 80H: Load D register with the value to search for, which is 80H.

4. SEARCH: The label for the loop that checks each memory location.

o MOV A, M: Move the content of the memory location pointed to by HL into the
accumulator.

o CMP D: Compare the accumulator with the value in D register (which is 80H).

o JZ FOUND: If the value in memory equals 80H, jump to the FOUND label (terminating
the program).

5. INX HL: Increment HL so that it points to the next memory location (9001H → 9002H → 9003H).

6. MOV A, L: Move the value in L register (the low byte of the memory address) into the
accumulator.

o CPI 03H: Compare the L register value to 03H, which is the offset for the last address to
check (9003H).

o JZ NOT_FOUND: If all addresses have been checked, jump to the NOT_FOUND label.

7. JMP SEARCH: Repeat the search for the next memory location.

8. FOUND: If 80H is found, jump to this label and HLT to halt the program.

9. NOT_FOUND: If the value 80H is not found in the memory range, it will also halt the program.

40.If CLK frequency is 3.5 MHZ for 8085, find the execution time for SHLD
9200H and LDA 8700H.
 41.What is stack memory? Explain the PUSH, POP instruction.

42.Explain the operation of the instruction SUB L, SBB H, STA 9000H, SHLD
8000H, RRC, JNC.
1. SUB L

 Operation: Subtracts the contents of register L from the accumulator (A).

 Syntax: SUB L

 Flags Affected:

o Carry Flag (CY): Set if there is a borrow.

o Zero Flag (Z): Set if the result is zero.

o Sign Flag (S): Set if the result is negative.

o Parity Flag (P): Set if the parity of the result is even.

 o Auxiliary Carry Flag (AC): Set if there is a borrow from bit 3 to bit 4.

 Operation: A=A−LA = A - LA=A−L The result is stored in the accumulator.

2. SBB H

 Operation: Subtracts the contents of register H and the carry flag (CY) from the accumulator (A).

 Syntax: SBB H

 Flags Affected: Same as SUB.

 Operation: A=A−(H+CY)A = A - (H + CY)A=A−(H+CY) The result is stored in the accumulator.

3. STA 9000H

 Operation: Stores the contents of the accumulator (A) into the memory location 9000H.

 Syntax: STA 9000H

 Steps:

1. The memory address (9000H) is placed on the address bus.

2. The contents of the accumulator are written to this memory location.

 Clock Cycles: 13 T-states.

4. SHLD 8000H

 Operation: Stores the contents of register pair HL into two consecutive memory locations
starting at 8000H.

 Syntax: SHLD 8000H

 Steps:

1. The lower byte (contents of L) is stored at memory location 8000H.

2. The higher byte (contents of H) is stored at memory location 8001H.

 Clock Cycles: 16 T-states.

5. RRC (Rotate Right Accumulator)

 Operation: Rotates the bits of the accumulator (A) one position to the right.

 Syntax: RRC
  Details:

1. The least significant bit (D0) is moved to the most significant bit (D7) and also to the
carry flag (CY).

2. All bits are shifted to the right by one position.

 Effect: A[D7]=A[D0],A[D6]=A[D7],…,CY=A[D0]A[D7] = A[D0], A[D6] = A[D7], \dots, CY =

A[D0]A[D7]=A[D0],A[D6]=A[D7],…,CY=A[D0]

 Flags Affected:

o Carry Flag (CY) is set based on the least significant bit.

6. JNC (Jump If No Carry)

 Operation: Transfers control to the specified address if the carry flag (CY) is reset (CY = 0).

 Syntax: JNC address

 Steps:

1. If CY = 0, the program counter (PC) is updated with the specified address, and the
program jumps to that location.

2. If CY = 1, execution continues sequentially.

 Example: If the carry flag is reset, the instruction will jump to the address provided.

Summary of Operations

Instruction Operation

SUB L Subtracts register L from the accumulator.

SBB H Subtracts register H and carry flag from the accumulator.

STA 9000H Stores the accumulator's value at memory location 9000H.

SHLD 8000H Stores register pair HL in memory locations 8000H and 8001H.

RRC Rotates the accumulator bits one position to the right.

JNC Jumps to the specified address if the carry flag is 0.

43.Draw the internal architecture of the 8254. (same as 10)

 44.Write the instruction to generate a pulse of 50 us from counter 0 in 8254.
Read only the LSB portion of that counter. Write the control word and
subroutine. Consider internal frequency to be 2 MHz

To generate a pulse of 50 µs using Counter 0 of the 8254 programmable interval timer, we need to
calculate the counter value, write the appropriate control word, and develop the necessary subroutine.
Here's a step-by-step explanation:
3. Subroutine

Here’s the assembly code for generating the pulse:

assembly

Copy code
; Initialize 8254 for Counter 0 pulse generation

MOV AL, 20H ; Control word for Counter 0, Mode 0, LSB only

OUT 43H, AL ; Send control word to Control Register (port 43H)

MOV AL, 64H ; Load LSB (100 in decimal) into Counter 0

OUT 40H, AL ; Send LSB to Counter 0 (port 40H)

; Wait for the pulse to complete

WAIT:

IN AL, 40H ; Read LSB of Counter 0

CMP AL, 00H ; Check if counter has reached 0

JNZ WAIT ; If not zero, keep waiting

RET ; Return after pulse generation

Explanation of Code

1. Control Word: The value 20H20H20H initializes Counter 0 in Mode 0 and selects LSB-only
read/write.

2. Load Counter: The value 64H64H64H (100 in decimal) is loaded as the initial count.

3. Wait for Pulse: The program waits until Counter 0 reaches 0 by continuously checking the
current value of the counter.

4. Pulse Output: The output of Counter 0 generates a pulse of 50 µs.

45.Write the BSR control word and subroutine in 8255 to set PC1 and PC3,
after 10 us reset those bits.
46.In 8255 I/O mode 8 push buttons are connected to port A and one seven
segment display connected to port C. Port B acts as i/p port. Write the
control word and draw the hardware. Consider o/p port=0, i/p port= 1.
 47.WAP to transfer ten 8-bit numbers from 8050H to 9050H.
8050: 01, 8051: 02, …. 8059:0A
To write a program to transfer ten 8-bit numbers from 8050H to 9050H in the 8051 microcontroller,
we'll perform the following steps:

1. Initialize source and destination memory addresses.

2. **Load the numbers from 8050H to a temporary register.
3. **Store each number to 9050H sequentially.
The numbers from 8050H to 8059H are:
 8050H: 01
 8051H: 02
 8052H: 03
 8053H: 04
 8054H: 05
 8055H: 06
 8056H: 07
 8057H: 08
 8058H: 09
 8059H: 0A
Assembly Code:
assembly
Copy code
; Program to transfer ten 8-bit numbers from 8050H to 9050H
ORG 00H ; Start of code

MOV DPTR, #8050H ; Load source address (8050H) into DPTR

MOV R0, #0 ; R0 for counting (index)
MOV A, #0 ; Clear accumulator

LOOP:
MOV A, @DPTR ; Load 8-bit number from source
MOV DPTR, #9050H ; Load destination address (9050H) into DPTR
MOV @DPTR, A ; Store the number to destination
INC DPTR ; Increment source address (8050H)
INC DPTR ; Increment destination address (9050H)
INC R0 ; Increment counter
CJNE R0, #10, LOOP ; Loop until 10 numbers are transferred

RET ; Return from subroutine

Explanation:
1. ORG 00H: Set the starting address for the program.
2. MOV DPTR, #8050H: Initialize the source address in the DPTR register.
3. MOV R0, #0: Initialize a counter (R0) to 0 to keep track of the number of transfers.
4. LOOP:
o MOV A, @DPTR: Load an 8-bit number from the source address pointed to by DPTR.
o MOV DPTR, #9050H: Update DPTR to point to the destination address.
o MOV @DPTR, A: Store the value from accumulator A to the destination address.
o INC DPTR: Increment DPTR to point to the next memory location in source.
o INC R0: Increment the counter.
o CJNE R0, #10, LOOP: Check if 10 numbers have been transferred. If not, jump back to
LOOP.
5. RET: Return from the subroutine after transferring all numbers.
Memory Layout:
 8050H: 01
 8051H: 02
  8052H: 03
 8053H: 04
 8054H: 05
 8055H: 06
 8056H: 07
 8057H: 08
 8058H: 09
 8059H: 0A
 9050H: 01
 9051H: 02
 9052H: 03
 9053H: 04
 9054H: 05
 9055H: 06
 9056H: 07
 9057H: 08
 9058H: 09
 9059H: 0A
This program reads data from 8050H to 8059H and writes them to 9050H to 9059H
sequentially, transferring each number one by one.

48.Practice decoding out the output programs done in the class. You should
be able to write the final output after the given set of instructions.

49.What is Program status word?

The Program Status Word (PSW) in the 8051 microcontroller is a 1-byte register that contains
information about the state of the microcontroller at any given point during the execution of a program.
It plays a crucial role in the functioning of the 8051 as it stores various status flags that provide
information about the last arithmetic and logical operations performed by the microcontroller.

Components of PSW:
The PSW is divided into two parts:

1. Status Flags (Bits 0-6):

o Carry Flag (C): Indicates if the last arithmetic or logic operation resulted in a carry.

o Auxiliary Carry Flag (AC): Used for binary-coded decimal (BCD) operations.

o Overflow Flag (OV): Indicates an arithmetic overflow.

o Sign Flag (S): Represents the most significant bit of the result, indicating the sign of the
result (negative if set).

o Parity Flag (P): Indicates if the result has an even number of 1s (set) or an odd number
(reset).

o Register Bank Select (RS1, RS0): These bits are used for switching between different
register banks (only RS0 is used in 8051).

o Interrupt Enable Flag (IE): Indicates whether interrupts are enabled (0) or disabled (1).

2. Accumulator (A) (Bit 7):

o This bit reflects the contents of the accumulator at any given point

50.Define instruction cycle, machine cycle.

Instruction Cycle:

An instruction cycle is the total time required by the microprocessor to fetch, decode, and execute an
instruction. It consists of several steps:

1. Fetch: The instruction is fetched from memory.

2. Decode: The fetched instruction is decoded to determine the required operation.

3. Execute: The operation is performed, and the result is stored.

In short, the instruction cycle involves all the operations needed to complete one instruction.

Machine Cycle:

A machine cycle is a part of the instruction cycle. It refers to the time required to complete one basic
operation (such as reading from memory, writing to memory, or fetching an instruction). Each
instruction may take multiple machine cycles to complete.

For example, an instruction like MOV A, B might require one machine cycle, while a more complex
instruction like LDA 2000H (load data from memory) requires multiple machine cycles (fetch, memory
read).
Key Difference:

 The instruction cycle consists of multiple machine cycles.

 A machine cycle is the basic unit of time for executing a single operation like fetching or
memory access.

51.Explain the function of ALU and IO/M signals in the 8085 architecture?
Function of ALU (Arithmetic Logic Unit) in 8085 Architecture:

The ALU (Arithmetic Logic Unit) is a critical component of the 8085 microprocessor responsible for
performing arithmetic and logical operations. Key functions include:

1. Arithmetic Operations:

o Performs addition, subtraction, increment, and decrement operations on 8-bit data.

2. Logical Operations:

o Carries out logical operations like AND, OR, XOR, and NOT (complement).

3. Comparison:

o Compares two values and sets flags based on the result (zero, carry, etc.).

4. Bit Shifting and Rotations:

o Shifts or rotates bits left or right within a register.

5. Flag Register Update:

o After each operation, the ALU updates the status flags (Zero, Sign, Carry, Parity, Auxiliary
Carry), which indicate the result of the operation.

Function of IO/M Signal in 8085 Architecture:

The IO/M signal is used to differentiate between memory and I/O operations in the 8085
microprocessor:

1. IO/M = 0:

o Indicates a memory operation (reading from or writing to memory).

o Used when the microprocessor is accessing program or data memory.

2. IO/M = 1:

o Indicates an I/O operation (input or output).

 o Used when the microprocessor is communicating with an I/O device (reading data from
an input port or writing to an output port).

The IO/M signal helps the microprocessor identify whether it is accessing memory or interacting with
external input/output devices.

52.What is 8254? Discuss its various operating modes. What are its areas of
applications?
53.Write a program(8085) to multiply two 8-bit numbers.
 54.Mention the purpose of STACK and delay. Explain the priority of interrupts
in 8085.
Purpose of Stack:

1. Saving Return Addresses: Used during subroutine calls to store the return address.

2. Storing Register Data: Temporarily saves register contents using PUSH and restores them with
POP.

3. Handling Nested Subroutines and Interrupts: Allows storing multiple return addresses.

4. Temporary Data Storage: Holds intermediate data during complex operations.

Purpose of Delay:

1. Synchronization: Ensures the microprocessor waits for slower peripherals.

2. Timing Control: Maintains accurate timing for tasks like blinking LEDs or sending data.

3. Debouncing: Prevents false readings from mechanical switches.

4. Generating Time Intervals: Creates specific delays for tasks like running motors or controlling
lights.

!!Do not skip any questions. Prepare all of them carefully.

Develop an overall concept for MCQs.