List of Experiment
List of Experiment
S.NO Experiments
1 Series and Shunt feedback amplifiers-Frequency response, Input and output impedance.
6 Instrumentation amplifier.
13 Bistable Multivibrator
S.NO Experiments
S.NO Experiments
1 SOLDERING WORK:
1 Modeling of wireless communication systems using Matlab (Two ray channel and
Okumura –Hata model.
3 Design, analyze and test Wireless standards and evaluate the performance measurements
such as BER, PER, BLER, throughput, capacity, ACLR, EVM for 4G and 5G using
Matlab.
6 Modeling and simulation of TDMA, FDMA and CDMA for wireless communication.
Meenakshi Sundararajan Engineering College
(Managed by I.I.E.T Society)
Approved by AICTE and Affiliated to Anna University
Accredited by NAAC with ‘A’ Grade
Accredited by NBA for programs applied
363, Arcot Road, Kodambakkam, Chennai – 24
7 Pulse Position Modulation and Demodulation and Pulse Width Modulation and Demodulation.
1 GENERATION OF SIGNALS
17 WAVEFORM GENERATION
Meenakshi Sundararajan Engineering College
(Managed by I.I.E.T Society)
Approved by AICTE and Affiliated to Anna University
Accredited by NAAC with ‘A’ Grade
Accredited by NBA for programs applied
363, Arcot Road, Kodambakkam, Chennai – 24
LIST OF EXPERMIENTS
S.NO Experiments
1 Design of basic combinational and sequential (Flip-flops) circuits using HDL. Simulate it using
Xilinx/Altera Software and implement by Xilinx/Altera FPGA
2 Design an Adder ; Multiplier (Min 8 Bit) using HDL. Simulate it using Xilinx/Altera Software and
implement by Xilinx/Altera FPGA
3 Design and implement Universal Shift Register using HDL. Simulate it using Xilinx/Altera
Software
4 Design Memories using HDL. Simulate it using Xilinx/Altera Software and implement by
Xilinx/Altera FPGA
5 Design Finite State Machine (Moore/Mealy) using HDL. Simulate it using Xilinx/Altera Software
and implement by Xilinx/Altera FPGA
6 Design Finite State Machine (Moore/Mealy) using HDL. Simulate it using Xilinx/Altera Software
and implement by Xilinx/Altera FPGA
7 Design 4-bit Asynchronous up/down counter using HDL. Simulate it using Xilinx/Altera Software
and implement by Xilinx/Altera FPGA
8 Design and simulate a CMOS Basic Gates & Flip-Flops. Generate Manual/Automatic Layout .
9 Design and simulate a 4-bit synchronous counter using a Flip-Flops. Generate Manual/Automatic
Layout
11 Design and Simulate basic Common Source, Common Gate and Common Drain Amplifiers.
7 Mailbox.
9 Flashing of LEDS.