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Dvlsi Unit-5 Notes

The document contains a series of tasks related to Verilog and MIPS programming, including writing functions for 2's complement, bit comparison, and address decoding. It also includes machine language encoding for various MIPS instructions and assembly language programs for specific pseudo code segments. Each task is presented with a prompt followed by an answer section.

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Sasi Bhushan
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8 views

Dvlsi Unit-5 Notes

The document contains a series of tasks related to Verilog and MIPS programming, including writing functions for 2's complement, bit comparison, and address decoding. It also includes machine language encoding for various MIPS instructions and assembly language programs for specific pseudo code segments. Each task is presented with a prompt followed by an answer section.

Uploaded by

Sasi Bhushan
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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LAKIREDDY BALI REDDY COLLEGE OF ENGINEERING (AUTONOMOUS)

L.B.Reddy Nagar :: Mylavaram – 521 230 :: Krishna Dist.:: A.P.


20VE01 DIGITAL VLSI SYSTEM DESIGN

UNIT- 5

1 Write a Verilog function that will create the 2’s complement of an N-bit vector. Use a call of the form
comp2 (bit_vec, N), where ‘bit_vec’ is the vector and N is the length of the vector. Do the complement on a
bit-by-bit basis using a loop. You may declare N as a global parameter in the calling module.
Ans

2 A and B are bit vectors that represent unsigned binary numbers. Write a Verilog function that returns
TRUE (1) if A > B. The function call should be of the form GT(A, B, N), where N is the length of the bit
vectors. Hint: start comparing the most significant bits of A and B first and proceed from left to right. As
soon as you find a pair of unequal bits, you can determine whether A > B. For example, if A = 1011010
and B = 1010110, you can determine that A > B when you make the fourth comparison. You may declare
N as a global parameter in the calling module.
Ans

3 Write a Verilog model that uses only built-in primitives to implement the following circuit. Rise delay of
NAND gate is 15 ns. Rise delay of XOR gate is 14 ns, fall delay of XOR gate is 16 ns. Rise delay of NOR
gate is 12 ns, and fall delay of NOR gate is 14 ns.

Ans

4 Write a Verilog module of an address decoder/address match detector. One input to the address decoder
is an 8-bit address, addr. The second input is the 6-bit vector check. The address decoder will give output
Sel = 1 if the upper 6 bits of the 8-bit address match the 6-bit check vector.
Ans

5 Write a Verilog function to compare two 8-bit vectors to determine whether they are equal. Report an error
if any bit of either vector is not 0, 1, or z. The function call should pass only the vectors. The function
should return TRUE (1) if the vectors are equal, else FALSE (0). All bits including zs should match (i.e., z
only matches z).
Ans
6 Write structural Verilog code for a module that is an N-bit serial-in, serial-out right shift register. Inputs
to the shift register are bit signals: SI (serial input), Sh (shift enable), and CLK. Your module should have
a generate statement. Assume that a component for a D flip-flop with clock enable (CE) is available.
Ans

7 Write structural Verilog code for a module that has two inputs: an N-bit vector A, and a control signal B (1
bit). The module has an N-bit output vector, C. When B = 1, C <= A. When B = 0, C is all 0s. Use
parameter to specify the value of N (default = 4). To implement the logic, use a generate statement that
instantiates N 2-input AND gates.
Ans

8 What is the machine language encoding for the following MIPS instructions? Give the answers in
hexadecimal (hex). All offsets are in decimal.
(i) add $6, $7 , $8
(ii) lw $5, 4($6)
(iii) addiu $3, $2, -2000
(iv) sll $3, $7, 12
(v) beq $6, $5, -16
(vi) j 4000
Ans (i) 00E83020
(ii) 8CC50004
(iii) 2443F830
(iv) 00071B00
(v) 10C5FFF0
(vi) 080003E8
9 What is the machine language encoding for the following MIPS instructions? Give
the answers in hexadecimal (hex). All offsets are in decimal.
(i) addi $5, $4 ,4000
(ii) sw $5, 20($3)
(iii) addu $4, $5, $3
(iv) bne $2, $3, 32
(v) jr $5
(vi) jal 8000
Ans (i) 20850FA0
(ii) AC650014
(iii) 00A32021
(iv) 14430020
(v) 00A00008
(vi) 0C0007D0
10 What MIPS instruction do the following hexadecimal (hex) numbers correspond to? If it is not any
instruction of correct format, denote it as an illegal opcode.
(i) 33333300
(ii) 8D8D8D8D
(iii) 1777FF00
(iv) BDBD00BD
(v) 01010101
Ans (i) andi $19, $25, 13056
(ii) lw $13, -29299($12)
(iii) bne $27, $23, -256
(iv) illegal opcode
(v) illegal opcode
11 Write a MIPS assembly language program for the following pseudo code segment:
for(i = 0; i < 100; i++)
x(i) = x(i) * y(i)
Ans andi $3, $3, 0 ;initialize loop counter $3 to 0. See Note.
addi $2, $3, 400 ;loop bound. Since $3 has 0, it is used.
loop: lw $15, 4000($3) ;load x(i) to R15
lw $14, 8000($3) ;load y(i) to R14
mult $14, $15 ;hi, lo = $14 * $15
mflo $14 ;$14 = low bits
sw $14, 4000($3) ;save new x(i)
addi $3, $3, 4 ;update address register, address= address + 4
bne $3, $2, loop ;check if loop counter=loop bound
Note: In an actual MIPS, register $0 is always 0. So clearing register $3 can be done by add $3, $0, $0.
12 Write a MIPS assembly language program for the following pseudo code segment:
for(i = 1; i < 100; i++)
x(i) = x(i) + x(i-1)
Ans andi $3, $3, 0 ;clear loop counter $3. See Note.
addi $2, $3, 400 ;loop bound
lw $14, 4000($3) ;load x(i-1) to R14
loop: lw $15, 4004($3) ;load x(i) to R15
add $14, $14, $15 ;$14 = x(i) + x(i-1)
sw $14, 4004($3) ;save new x(i)
addi $3, $3, 4 ;update address register, address= address + 4
bne $3, $2, loop ;check if loop counter=loop bound
Note: In an actual MIPS, register $0 is always 0. So clearing register $3 can be done by add $3, $0, $0.
13 Write a MIPS assembly language program for the following pseudo code segment:
for(i = 0; i < 100; i++)
y(i) = a * x(i) + y(i)
Ans andi $3, $3, 0 ;initialize loop counter $3 to 0. See Note.
addi $2, $3, 400 ;loop bound
lw $16, 12000($3) ;$16 = a
loop: lw $15, 4000($3) ;load x(i) to R15
lw $14, 8000($3) ;load y(i) to R14
mult $16, $15 ;hi, lo = a * x(i)
mflo $15 ;$15 = low bits of a * x(i)
add $14, $14, $15 ;$14 = a * x(i) + y(i)
sw $14, 8000($3) ;save new y(i)
addi $3, $3, 4 ;update address register, address= address + 4
bne $3, $2, loop ;check if loop counter=loop bound
Note: In actual an MIPS, register $0 is always 0. So clearing register $3 can be done by add $3, $0, $0.

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