Analog and Discrete Electronics Lab Manual Spring 2020

LAB-1 (Tutorial)

Characterization of CMOS
DC Analysis of NMOS and
PMOS
Engineer. Hamza Atiq
Prof. Rashad M. Ramzan
Dr. Hassan Saif

Electrical Engineering Department

National University of Computer &
Emerging Sciences (FAST-NU)
Islamabad-44000, Pakistan
Copy Rights: This laboratory manual was designed at RFCS2/ICD LAB at NUCES (FAST_NU) Islamabad
using the open source material and related textbooks used in a respective theory course. You are free to use,
distribute, and modify this material for academic and noncommercial use. You are NOT allowed to use this
material for commercial purposes where the participants are charged for the training without the written
consent of the authors. You are not allowed to remove the author's name and put your own as part of the
academic honesty.

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Analog and Discrete Electronics Lab Manual Spring 2020

Introduction:
Cadence is an Electronic Design Automation (EDA) environment that integrates several design
tools in a single design suite. This course includes exercises in which you will use the Cadence
tools to design CMOS integrated circuits. Each lab will consist of designing and simulating
different microelectronic building blocks that you will reuse during this course. So, make sure to
carefully achieve all the requested items.
Instructions:
You can complete this tutorial in your own time, if there is any problem please send an email or
show up in the office of the TA. You must answer the questions in the LAB compendium before
you start the tutorial, this will help you to comprehend the tutorial material and simulations.

Objectives of this Lab

This Tutorial LAB you will learn how to use the schematic editing tool to create and simulate a
basic circuit schematic using the tsmc13rf (130 nm technology) design kit.
Analog Design Environment is used to simulate the DC parameters (operating points, vth, gm
etc.) of which are important in characterization of MOSFET. The solution type will be a DC
setup.
Follow are the parameters that are to be simulated and measured.

1) Threshold voltage (vth) of transistor.

2) Drain current (Id) variation with changing VGS.
3) Drain current (Id) variation with changing VDS.
4) Transconductance (gm) variation with changing VGS.
5) Transconductance (gm) variation with changing Id.
6) Drain current (Id) variation with changing VGS and VDS .

1. Background Preparation
Please answer the following questions before the LAB
1) Fill the below table and write the modes of transistor for NMOS Vtn=0.5V
VS VG VD VGS VOV VDS MODE OF OPERATION
+1 +1 +2
+1 +1.5 0
-1 0 0
+0.5 +2 +0.5
-1 +1 +1
-0.5 +0.5 +0.5

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Analog and Discrete Electronics Lab Manual Spring 2020

2) Draw small signal Ac model of PMOS transistor in Saturation and also write the biasing
conditions and equation of Drain current for Saturation.

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 2. Cadence Environment Setup
This tutorial assumes you know how to start cadence and have already launched the program in
the proper working directory. We will be using TSMC 130nm CMOS process for these LABs.
2.1 Creating a new Schematic
 Make a new library IC_lab in Cadence Library Manager. (File→New→library)
 Select reference existing technology libraries than select tsmc13rf add it into reference
technology libraries than press OK.
 Create a new schematic cell in IC_lab (put a meaningful name relevant to this lab1).
(File→New→Cell View).
 Click the OK button. The Composer schematic editing tool will open with an empty
Schematic Editing window.

2.2 Adding components

 In the Schematic Editing window Select Add => Instance to activate the Add Instance
tool for adding components (transistors, sources, etc.) to your schematic. You can also
invoke this tool by clicking on the Instance icon on the left-hand toolbar, or by pressing
the hot key ‘i’. Two windows (Component Browser window and Add Instance) will pop
open.
 In add instance window browse tsmc13rf library from cells select nmos3v which is low
vth CMOS click on symbol and place into schematic. (create→instance→tsmc13rf→
nmos3v). NOTE: You can also rotate a component by selecting Edit => Rotate or by
typing the hot key “r”.
 Right click on transistor select properties or hot key “q” change the number of fingers=1
(W/L=3.5u/350n).
 Again press ‘i’ browse into analogLib. Analog lib library includes the basic passive
elements and sources etc. From the cells pallet select ‘vdc’ and ‘gnd’ and place it into the
schematic.
 Similarly change the DC source properties (Dc voltage=1 & DC voltage=3) as shown in
Fig.1 and press ENTER.
2.3 Add wire connections
 In the Schematic Editing window select Add => Wire (or use hot key ‘w’) to begin
placing wires, which will connect the terminals of the components and pins in the
schematic. 
 Wire the schematic as appropriate for a CMOS design as shown in Fig 1.
 Now that you are familiar with the schematic editing tool, explore the menu commands in
the Schematic Editing window to do the following
Check the cell for errors. If errors exist the error section will blink in the Schematic
Editing window.
 Save the cell view.

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 Fig 1: Schematic Circuit for CMOS Characterization

2.4 Launch Analog Design Environment simulation tool

 We want to perform a DC sweep of the input voltage (VGS) "Vdc (V0)" from 0V to 3V
and observe the drain current Id. From the schematic window select Launch→ADE L.
Click OK on the popup window.
 In the Analog design environment window, go to Analysis→Choose→select
dc→"check save dc operating point"→"check component parameter"→Select
Component→click the voltage source “V0” labelled "Vdc"→double click the "DC"
option→set start to 0 and stop to 3→ OK.
 In the Analog design environment go to outputs -> to be plotted -> select on schematic,
and then click on the transistor drain node. Coloured circle will appear around the node as
shown in Fig 1. Press "Esc" to exit the net selection mode.
 In the Analog design environment go to simulation → Netlist and Run

Fig 2: VGS versus Id

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2.5 Parametric analysis
 Parametric analysis is used when two or more independent variables are present in a
single function. We can have the standard X-Y plot of VDS versus ID with a constant
VGS. But we need to plot the same X-Y plot multiple times for each of the discrete VGS
values.
 In V0 voltage source properties tab replace DC voltage with a variable “VGS”
(vdc=VGS V).
 Similarly in V1 replace DC voltage with a variable “VDS”
(vdc=VDS V).
 To run parametric analysis first go to Launch→ADE L→Variables→copy from
cellview→set values of VDS and VGS to "1" in the design variables sub-window.
 Next, choose dc analysis →check save dc operating point→check design variable
under the sweep variable field→select design variable→double click VDS in the popup
window→set start to "0" and stop to "3"→OK.
 Next, go to Outputs→to be saved→select on design→ click the drain node (where the
device meets the wire at the red dot to measure current instead of voltage).
 In the Analog design environment go to Tools→Parametric Analysis.
 Once the parametric analysis is open, select VGS from the dropdown window under the
"Variable" field→set "From" to 0 and "To" to 3→set the field "Step Mode" to "Linear
Steps" from the dropdown menu→set "Step Size" to 500m>.
 In parametric analysis tab Run sweeps.

Fig 3: VDS versus Id for varying VGS

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2.5 Calculating device parameters
 In the Analog design environment go to Tools→Calculator→ check wave & clip.
 In the Calculator editor window write expression for gm value (OP("/M0" "??")
"sweep" "gm") in the buffer.
 Under the expression editor menu add buffer expression to expression editor and
rename the plot to gm or press Evaluate

Fig 4: gm (transconductance) with varyin

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 Assignment
1) Repeat the Lab1 with PMOS transistor.
2) Also analyse the temperature variation on device parameters.

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