Sequential Logic Circuits

 The output of a sequential logic circuit is dependent not only on the present inputs, but
also on the past sequence of the inputs.
 A sequential logic circuit must “remember” the past history of the inputs.
 It does this using basic memory elements.

– Latches
– Flip-Flops

Basic Memory Elements

● Latch
– Clock input is level sensitive.

– Output can change multiple times during a clock cycle.

– Output changes while clock is active.

● Flip-Flop
– Clock input is edge sensitive.

– Output can change only once during a clock cycle.

– Output changes on clock transition.

Both latches and flip-flops use feedback to achieve “memory”.

1
Page

Digital logic design Samer A.Hamed

 Latches
Set-Reset (SR) Latch

● A Set-Reset Latch has two inputs

– Set (S) input
– Reset (R) input
● It can be constructed from two cross-coupled NOR gates or two cross-coupled NAND gates.
● It has three modes of operation
– Set: Latch output set to 1 (Q+ = 1)
– Reset: Latch output reset to 0 (Q+ = 0)
– Store: Latch output does not change (Q+ = Q)

SR Latch: using NOR gates

SR Latch: Behavior
2
Page

Digital logic design Samer A.Hamed

 SR Latch: Symbol

SR Latch: Timing Diagram

3
Page

Digital logic design Samer A.Hamed

 SR Latch: Characteristic Equation

Characteristic Equation: Q+ = S + R'.Q (S.R = 0)

4
Page

Digital logic design Samer A.Hamed

 SR Latch: using NAND gates
5
Page

Digital logic design Samer A.Hamed

 Gated D Latch
A Gated D Latch has two inputs
– Gate (G) input
– Data (D) input
● It can be constructed from an SR Latch and additional logic gates.
● It has the following behavior
– G = 1: D is passed to Q (Q+ = D)
– G = 0: Q remains unchanged (Q+ = Q)
● Also referred to as a transparent latch.

Gated D Latch: Circuit and Timing

Gated D Latch: Symbol and Truth Table

6
Page

Digital logic design Samer A.Hamed

 Characteristic Equation: Q+ = G'.Q + G.D
7
Page

Digital logic design Samer A.Hamed

 Flip-Flops
D Flip-Flop
● A D Flip-Flop has two inputs
– Clock (Ck) --- denoted by the small arrowhead
– Data (D)
● The output of the D Flip-Flop changes in response to the clock input only.
– not in response to a change in the D input
● The D Flip-Flop is edge-triggered not level-sensitive
– Positive (or rising) edge-triggered: 0 _ 1
– Negative (or falling) edge-triggered: 1 _ 0

Characteristic Equation: Q+ = D

D Flip-Flop: Timing Diagram

8
Page

Digital logic design Samer A.Hamed

 SR Flip-Flop

● The SR Flip-Flop has three inputs:

– Clock (Ck) --- denoted by the small arrowhead
– Set (S) and Reset (R)
● Similar to an SR Latch
– S = 1 sets the flip-flop (Q+ = 1)
– R = 1 resets the flip-flop (Q+ = 0)
● Like the D Flip-Flop, the Q output of an SR Flip-Flop only changes in response to an active
clock edge.
– Positive edge-triggered
– Negative edge-triggered

SR Flip-Flop
9
Page

Digital logic design Samer A.Hamed

 JK Flip-Flop

Characteristic Equation:

Q+ = J.Q' + K'.Q

T Flip-Flop
The Toggle (T) Flip-Flop has two inputs
– Clock (Ck) --- denoted by the small arrowhead
– Toggle (T)
● The T input controls the state change
– when T = 0, the state does not change (Q+ = Q)
– when T = 1, the state changes following an active clock edge (Q+ = Q')
● T Flip-Flops are often used in the design of counters.
10
Page

Digital logic design Samer A.Hamed

 Characteristic Equation: Q+ = T.Q' + T'.Q = T xor Q

Building a T Flip-Flop
11
Page

Digital logic design Samer A.Hamed

12
Page

Digital logic design Samer A.Hamed

13
Page

Digital logic design Samer A.Hamed

14
Page

Digital logic design Samer A.Hamed

15
Page

Digital logic design Samer A.Hamed

 Counters
 A counter is a sequential circuit that cycles through a fixed sequence of states.
 The state of the counter is stored in Flip-Flops.
 An n-bit counter
– has n Flip-Flops
– can cycle through at most 2n states.
16
Page

Digital logic design Samer A.Hamed

 Procedure to Design Synchronous Counters

The procedure to design a synchronous counter is listed here.

• Obtain the truth table of the logic sequence for intended counter to be

designed. Alternatively obtain the state diagram of the counter.

• Determine the number and type of flip-flop to be used.

• From the excitation table of the flip-flop, determine the next state logic.

• From the output state, use Karnaugh map for simplification to derive the circuit output
functions and the flip-flop output functions.

• Draw the logic circuit diagram.

• Simulate the circuit using software.

• Build the circuit.

17
Page

Digital logic design Samer A.Hamed

 Design a 3 bit up counter using T flip flop
18
Page

Digital logic design Samer A.Hamed

19
Page

Digital logic design Samer A.Hamed

 J0 = K0 = 1
J1 = K1 = Q0
J2 = K2 = Q1*Q0

Design a counter that goes through the sequence: 0, 3, 2, 4, 1, 5, 7 and repeat.

20
Page

Digital logic design Samer A.Hamed

21
Page

Digital logic design Samer A.Hamed

22
Page

Digital logic design Samer A.Hamed

 Analysis of Clocked Sequential Circuits

x
D Q A

D Q B

CLK Q

A(t+1) = DA

= A(t) x(t)+B(t) x(t)

=Ax+Bx

B(t+1) = DB

= A’(t) x(t)

= A’ x

y(t) = *A(t)+ B(t)+ x’(t)

23

= (A + B) x’
Page

Digital logic design Samer A.Hamed

  State Table (Transition Table)

Present state input Next state output

A B X A B Y
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 1
0 1 1 1 1 0
1 0 0 0 0 1
1 0 1 1 0 0
1 1 0 0 0 1
1 1 1 1 0 0

 State Diagram
24
Page

Digital logic design Samer A.Hamed

 Analysis of Clocked Sequential Circuits ( JK FLIP FLOP )

J Q A

x K Q

J Q B JA = B KA = B x’

JB = x’ KB = A  x
K Q

CLK

A(t+1) = JA Q’A + K’A QA

= A’B + AB’ + Ax

B(t+1) = JB Q’B + K’B QB

= B’x’ + ABx + A’Bx’

Present Next
input Flip Flop inputs
state state
A B X A B JA KA JB KB
0 0 0 0 1 0 0 1 0
0 0 1 0 0 0 0 0 1
0 1 0 1 1 1 1 1 0
0 1 1 1 0 1 0 0 1
1 0 0 1 1 0 0 1 1
1 0 1 1 0 0 0 0 0
1 1 0 0 0 1 1 1 1
1 1 1 1 1 1 0 0 0
25
Page

Digital logic design Samer A.Hamed

 Derive the state table and the state diagram of the sequential shown circuit.
Explain the function that the circuit performs

TA = A + B
TB = A’ + B

Q(next)= T’Q+TQ’

A(next) = TAA + TAA

= (A + B)A + (A + B)A= ABA + AA+ AB= 0 + 0 + AB= AB

B(next) = TBB + TBB= (A+ B)B + (A+ B)B= ABB + AB+ BB

= 0 + AB+ 0= AB
26


Page

Digital logic design Samer A.Hamed

 Example
A sequential circuit with two D flip-flops, A and B, two inputs, x and y, and one output
z, is specified by the next state and output equations:
A(t+1) = x’y + xA
B(t+1) = x’B + xA
z=B

a) Draw the logic diagram of the circuit

b) List the state table for the sequential circuit

c) Draw the corresponding state diagram

27
Page

Digital logic design Samer A.Hamed