Overview

• Testability measures: powerful heuristic

used during test generation
ECE-470 Digital Design II –Purpose and origins
Testability Measures –SCOAP measures
• Combinational circuit example
• Sources of correlation error
• Sequential circuit example

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Purpose: Testability Analysis Origins

• Need approximate measure of: • Control theory
– Difficulty of setting internal circuit lines to 0 or 1 by • Rutman 1972 - First definition of controllability
setting PIs • Goldstein 1979 - SCOAP
– Difficulty of observing internal circuit lines by observing – First definition of observability
POs – First elegant formulation
– First efficient algorithm to compute controllability
• Uses: and observability
– Analysis of difficulty of testing internal circuit parts – • Parker & McCluskey 1975
redesign or add special test hardware – Definition of Probabilistic Controllability
– Guidance for algorithms computing test patterns – • Brglez 1984 - COP
avoid using hard-to-control lines – 1st probabilistic measures
– Estimation of fault coverage (FC) • Seth, Pan & Agrawal 1985 - PREDICT
– 1st exact probabilistic measures
– Estimation of test vector length
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Testability Analysis - Constraints Types of Measures

• SCOAP – Sandia Controllability and
• Involves circuit topological analysis, but no Observability Analysis Program
test vectors and no search algorithm • Combinational measures:
– Static analysis – CC0 – Difficulty of setting circuit line to logic 0
• Linear computational complexity – CC1 – Difficulty of setting circuit line to logic 1
– CO – Difficulty of observing a circuit line
– Otherwise, is pointless – might as well use
• Sequential measures:
automatic test-pattern generation and calculate:
– SC0
• Exact fault coverage
• Exact test vectors – SC1
– SO
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 Ranges of SCOAP Measures Goldstein’s SCOAP Measures
• Controllabilities: • All PIs have set CC0=1 and CC1=1
1 (easiest) to infinity (hardest) • AND gate output 0 controllability:
• Observabilities: output_controllability = min (input_controllabilities) + 1
0 (easiest) to infinity (hardest) • AND gate output 1 controllability:
• Combinational measures:
– Roughly proportional to # circuit lines that must be output_controllability = ∑(input_controllabilities) + 1
set to control or observe given line • XOR gate output controllability
• Sequential measures: output_controllability = min(controllabilities of each input set) + 1
– Roughly proportional to # times a flip-flop must be • Fanout stem observability:
clocked to control or observe given line
∑ or min (fanout branch observabilities)
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Controllability Examples Controllability Examples

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Observability Examples Observability Examples

• To observe a gate input: Observe output and
make other input values non-controlling • To observe a fanout stem: Observe it through
branch with best observability

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 Error: Stems & Reconvergent Fanout Example: Correlation Error
• Exact computation of measures is NP-Complete and
• SCOAP measures wrongly assume that controlling impractical
or observing x, y, z are independent events • Italicized (blue) measures show correct values
– CC0 (x), CC0 (y), CC0 (z) correlate
– CC1 (x), CC1 (y), CC1 (z) correlate • SCOAP measures (red) are not italicized
– CO (x), CO (y), CO (z) correlate • Each signal line: CC0, CC1 (CO)
1,1(6) 2,3(4)
x x
2,3(4, ∞)
1,1(5, ∞) 6,2(0)
4,2(0)
y 1,1(5) (6) (5)
y
1,1(4,6) (4,6)
(6) 2,3(4)
z z
2,3(4, ∞)
1,1(6)
1,1(5, ∞)
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Levelization Algorithm Example

• Label each gate with max # of logic levels from
primary inputs or with max # of logic levels from
primary output
• Assign level #0 to all primary inputs (PIs)
• For each PI fanout:
– Label that line with the PI level number, &
– Queue logic gate driven by that fanout
• While queue is not empty:
– Dequeue next logic gate
– If all gate inputs have level #’s, label the gate with
the maximum of them +1
– Else, requeue the gate
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Controllability Through Level 0 Controllability Through Level 2

• Circled numbers give level number (CC0, CC1)

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 Final Combinational Controllability Combinational Observability for Level 1
Number in square box is level from primary outputs (POs)
(CC0, CC1) CO

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Combinational Observabilities for Level 2 Final Combinational Observabilities

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Sequential Measures Differences D Flip-Flop Equations

• Combinational • Assume a synchronous RESET line
– Increment CC0, CC1, CO whenever you pass through • CC1 (Q) = CC1 (D) + CC1 (C) + CC0 (C) + CC0 (RESET)
a gate, either forwards or backwards • SC1 (Q) = SC1 (D) + SC1 (C) + SC0 (C) + SC0 (RESET) + 1
• Sequential • CC0 (Q) = min [CC1 (RESET) + CC1 (C) + CC0 (C),
CC0 (D) + CC1 (C) + CC0 (C)]
– Increment SC0, SC1, SO only when you pass through
• SC0 (Q) is analogous
a flip-flop, either forwards or backwards, to Q, Q̄ , D, • CO (D) = CO (Q) + CC1 (C) + CC0 (C) + CC0 (RESET)
C, SET, or RESET • SO (D) is analogous
• Both
– Must iterate on feedback loops until controllabilities
stabilize
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 D Flip-Flop Clock and Reset Algorithm 6.2 for Testability Computation

• CO (RESET) = CO (Q) + CC1 (Q) + CC1 (RESET) + CC1 (C) + CC0 (C) 1. For all PIs, CC0 = CC1 = 1 and SC0 = SC1 = 0
• SO (RESET) is analogous 2. For all other nodes, CC0 = CC1 = SC0 = SC1 = ∞
• Three ways to observe the clock line: 3. Go from PIs to POs, using CC and SC equations to compute
1. Set Q to 1 and clock in a 0 from D controllabilities - Iterate on loops until SC stabilizes -
2. Set the flip-flop and then reset it convergence guaranteed
3. Reset the flip-flop and clock in a 1 from D 4. For all POs, set CO = SO = 0, ∞ for other nodes
• CO (C) = min [ CO (Q) + CC1 (Q) + CC0 (D) + CC1 (C) + CC0 (C), 5. Work from POs to PIs, Use CO, SO, and controllabilities to get
CO (Q) + CC1 (Q) + CC1 (RESET) + CC1 (C) + CC0 (C), observabilities
CO (Q) + CC0 (Q) + CC0 (RESET) + CC1 (D) + CC1 (C) + CC0 (C)] 6. Fanout stem (CO, SO) = min branch (CO, SO)
• SO (C) is analogous 7. If a CC or SC (CO or SO) is ∞, that node is uncontrollable
(unobservable)
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Sequential Example Initialization After 1 Iteration

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After 2 Iterations After 3 Iterations

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 Stable Sequential Measures Final Sequential Observabilities

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Test Vector Length Prediction Number Test Vectors vs. Testability Index

• First compute testabilities for stuck-at

faults
• T (f s-a-0) = CC1 (f) + CO (f)
• T (f s-a-1) = CC0 (f) + CO (f)
• Testability index = log S T (f i)

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Summary High Level Testability

• Testability approximately measures:
– Difficulty of setting circuit lines to 0 or 1 • Build data path control graph (DPCG) for
– Difficulty of observing internal circuit lines
– Examples for computing these values
circuit
• Uses: • Compute sequential depth - # arcs along path
– Analysis of difficulty of testing internal circuit parts
• Redesign circuit hardware or add special test hardware between PIs, registers, and POs
where measures show bad controllability or observability
– Guidance for algorithms computing test patterns/vectors
• Improve Register Transfer Level Testability with
– Estimation of fault coverage (FC) - 3-5 % error redesign
– Estimation of test vector length

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Improved RTL Design

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