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DLC Final Term OBE Assignment Fall 24-25

The document outlines an assignment for the Digital Logic Circuits course at AIUB, focusing on developing a digital parking control system. Students are required to design a block diagram, counter circuit, timer circuits, and a seven-segment display using CMOS technology, while also analyzing system limitations and performance. The assignment includes specific marking rubrics for evaluating the outlined tasks.

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34 views2 pages

DLC Final Term OBE Assignment Fall 24-25

The document outlines an assignment for the Digital Logic Circuits course at AIUB, focusing on developing a digital parking control system. Students are required to design a block diagram, counter circuit, timer circuits, and a seven-segment display using CMOS technology, while also analyzing system limitations and performance. The assignment includes specific marking rubrics for evaluating the outlined tasks.

Uploaded by

ohshakibkhan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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American International University- Bangladesh (AIUB)

Faculty of Engineering (EEE)


Course Name: Digital Logic Circuits Course Code: EEE 3101
Semester: Fall 24-25 Section:
Faculty: Term: Final
Marks: 20 Assignment Name: OBE Assignment
Student Name: Student ID:
Submission Date: Department:

Assessed
COs/
Program BNQF Teaching-
CLOs COs/CLOs Statements K P A
Outcome Indicato Learning Strategy
Number
Indicator r
Develop a system in context of Digital logic circuits P1,P2, OBE Assignment
CO2 with 555 timer and transistors for conflicting 3 - P.a.3.C3 FS.1
requirements of complex engineering problem. P6 (Final Term)

Instructions Related to Use Variables:


Note that this problem uses the variables a, b, c, d, e, f, g and h, which are a b - c d e f g - h
the digits of your student ID (ab-cdefg-h).
Any value in student ID comes ‘0’ will be replaced by ‘(a+b+h)’
Marking Rubrics (to be filled by Faculty):
Complex Task Assessment Evaluation Criteria Marks
Problem Criteria
P1, P2, Outline the Excellent Good Average Poor
P6 necessary (2.5) (2-1.5) (1-.5) (0)
steps of block All the steps have Not All the steps Few steps have All the steps have
diagram been identified and in have been identified been identified been found in
the correct sequences and in the correct and in the correct wrong sequences
sequences sequences
I. Design counter Excellent Good Average Poor
with necessary (2.5) (2-1.5) (1-.5) (0)
diagram All the designs were Not All the designs Few designs were All the design
accurate and working were accurate and accurate and were wrong and
working working not working
Design of Excellent Good Average Poor
timer circuits 1 (7) (6-5) (4-2) (1-0)
II. &2 Timer circuit design Timer circuit is Timer circuit is Timer circuit is
is correct and comply correct but not incorrect and does wrong and not
with the problem comply with the not comply with comply with the
problem the problem problem
Limitations of Excellent Good Average Poor
the developed (3) (2.5-2) (1.5-1) (0)
system Provides limitations Provides limitation Provides improper Provides no
and analyzes the only limitation and limitation and
performance performance gives no
analyze performance
analysis
III. CMOS logic Excellent Good Average Poor
design (5-4) (3-2) (1.5-1) (0)
The CMOS logic The CMOS logic The CMOS logic The CMOS logic
design is fully design is mostly design has design is not
correct. correct, with minor significant errors, attempted.
errors. with multiple
incorrect or
missing segments.
Marks Obtained:
Digital Parking Control System:

The problem is to monitor available spaces in a (a+g+h)-space parking garage and provide an indication
of a “FULL” by illuminating a display sign in seven seven-segment display along with driving a “Gate
control” motor. From the Figure below, two sensors from the entrance and exit will be connected to the
counter circuit to count. (i.e. the clock is synchronized with the sensors) and it will be placed into the
register according to the binary bit value. Now, Keypad is used to provide your maximum available space,
when the spaces are all filled up and the count is full then the display in seven segment display will show
the “Full” Indication until the space is empty, and at the same time, the entrance gate control will turn on
the “Gate Control” motor.

Your task is to:


i. Outline the essential steps in the correct sequence to develop a block diagram for designing an
automated parking control system. This system should include an actuated gate mechanism, a "FULL"
indication using a seven-segment display, and a counter circuit. In addition, Design the counter circuit
which is capable of simultaneous UP/DOWN counting. Include additional sequential and combinational
logic components, if required, to ensure smooth control and operation, providing appropriate reasoning for
selecting these components.

ii. Design the timer circuit 1 and the timer circuit 2 with a suitable frequency based on your requirement,
in which the capacitor value will be C = (c*g+20) µF. Identify the limitations of the designed system and
analyze the impact of increasing the number of parking spaces on its performance.

iii. Design the functions of your seven-segment display using CMOS technology to represent one of the
letters in the word “FULL”.

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