Unit IV

CPU Organization

For reading refer to following points from

William Stallings, “Computer Organization
and Architecture”, 8e
1.1,1.2, 3.1, 3.2, 12.1, 12.2, 15.2 (pg. 570 – 575)
and 16.1
Architecture & Organization 1
• Architecture is those attributes visible to
the programmer
—Instruction set, number of bits used for data
representation, I/O mechanisms, addressing
techniques.
 —e.g. Is there a multiply instruction?
• Organization is how features are
implemented
—Control signals, interfaces, memory
technology.
—e.g. Is there a hardware multiply unit or is it
done by repeated addition?
Architecture & Organization 2
• All Intel x86 family share the same basic
architecture
• The IBM System/370 family share the
same basic architecture

• This gives code compatibility

 —At least backwards
• Organization differs between different
versions
Structure & Function
• Structure is the way in which components
relate to each other
• Function is the operation of individual
components as part of the structure
Function
• All computer functions
are: —Data processing
—Data storage
—Data movement
—Control
Functional View
Operations (a) Data movement
Operations (b) Storage
Operation (c) Processing from/to storage
Operation (d)
Processing from storage to I/O
Structure - Top Level
 Computer

Main

Peripherals

Central
Memory

Computer
Processing Unit Systems
 n lines
Interconnection

Input
Output

Communicatio
Structure - The CPU

CPU

Computer Arithmetic
Registers and
I/O
Login Unit
System
CPU

Memory
Bus
Internal CPU Interconnection
 Unit

Control
CPU Structure
• CPU must:
—Fetch instructions
—Interpret
instructions —Fetch
data
—Process data
—Write data
CPU With Systems Bus
CPU Internal Structure
Registers
• CPU must have some working space
(temporary storage)
• Called registers
• Number and function vary between
processor designs
• One of the major design
decisions • Top level of memory
hierarchy
User Visible Registers •
General Purpose • Data
• Address
• Condition Codes
General Purpose Registers (1)
• May be true general purpose
• May be restricted
• May be used for data or addressing
• Data
—Accumulator
• Addressing
—Segment
General Purpose Registers (2)
• Make them general purpose
—Increase flexibility and programmer
options —Increase instruction size & complexity
• Make them specialized
—Smaller (faster) instructions
 —Less flexibility
How Many GP Registers?
• Between 8 - 32
• Fewer = more memory references • More
does not reduce memory references and
takes up processor real estate • See also
RISC
How big?
• Large enough to hold full address •
Large enough to hold full word •
Often possible to combine two data
registers
—C programming
 —double int a;
—long int a;
Condition Code Registers
• Sets of individual bits
—e.g. result of last operation was zero •
Can be read (implicitly) by programs
—e.g. Jump if zero
• Can not (usually) be set by programs
Control & Status Registers •
Program Counter
• Instruction Decoding Register
• Memory Address Register •
Memory Buffer Register
• Revision: what do these all do?
Program Status Word • A
set of bits
• Includes Condition
Codes • Sign of last result
• Zero
• Carry
• Equal
• Overflow
• Interrupt
enable/disable •
Supervisor
Supervisor Mode Registers
• Intel ring zero
• Kernel mode
• Allows privileged instructions to execute
• Used by operating system
• Not available to user programs
Other Registers
• May have registers pointing to:
—Process control blocks (see O/S)
—Interrupt Vectors (see O/S)

• N.B. CPU design and operating system

 design are closely linked
Example Register Organizations
Structure - The CPU

CPU

Computer Arithmetic
Registers and
I/O
Login Unit
System
CPU

Bus

Memory Control
Unit
Internal CPU Interconnection
Structure - The Control Unit Control Unit
CPU
Sequencing Login
ALU

Internal
Bus Control Unit Registers
and Decoders Control
Registers
Control Unit Memory

A Control Unit is
⮚Finite State Machine
▪ I/P – machine instructions and datapath
conditions
▪ O/P – register transfer control signals,
ALU operation codes
▪ Instruction Interpretation – instruction
fetch, decode, execute
Model of Control Unit
Data Paths and Control Signals
Internal Organization
 • Usually a single internal bus
• Gates control movement of data onto and
off the bus
• Control signals control data transfer to
and from external systems bus
• Temporary registers needed for proper
operation of ALU
CPU with
Internal
Bus
Intel 8085
CPU Block
Diagram
Intel 8085 Pin
Configuration
Intel 8085 OUT Instruction
Timing Diagram
Hardwired Implementation (1) •
Control unit inputs
• Flags and control bus
—Each bit means something
• Instruction register
—Op-code causes different control signals for
each different instruction
—Unique logic for each op-code
—Decoder takes encoded input and produces
single output
—n binary inputs and 2n outputs
Hardwired Implementation (2) •
Clock
—Repetitive sequence of pulses
—Useful for measuring duration of
micro-ops —Must be long enough to allow
signal propagation
—Different control signals at different times
within instruction cycle
—Need a counter with different control signals
for t1, t2 etc.
Control Unit with Decoded Inputs
Problems With Hard Wired Designs
 • Complex sequencing & micro-operation
logic
• Difficult to design and test
• Inflexible design
• Difficult to add new instructions
Micro-programmed Control Unit
Micro-programmed Control
• Use sequences of instructions (see earlier
 notes) to control complex operations •
Called micro-programming or firmware
Implementation (1)
• All the control unit does is generate a set
of control signals
• Each control signal is on or off
• Represent each control signal by a bit
• Have a control word for each micro
operation
• Have a sequence of control words for each
machine code instruction
• Add an address to specify the next micro
instruction, depending on conditions
Implementation (2)
• Today’s large microprocessor
—Many instructions and associated register-level
hardware
—Many control points to be manipulated •
This results in control memory that
—Contains a large number of words
– co-responding to the number of instructions to be
executed
—Has a wide word width
– Due to the large number of control points to be
manipulated
Micro-program Word Length
• Based on 3 factors
—Maximum number of simultaneous micro
operations supported
 —The way control information is represented or
encoded
—The way in which the next micro-instruction
address is specified
Branch Control Logic:
Two Address Fields
Branch Control
Logic: Single
Address Field
Branch Control
Logic: Variable
Format
A Taxonomy of
Microinstructions
• Vertical/horizontal
• Packed/unpacked
• Hard/soft microprogramming
• Direct/indirect encoding