Hall Ticket No Question Paper Code: AECD04

INSTITUTE OF AERONAUTICAL ENGINEERING

(Autonomous)
Dundigal, Hyderabad - 500 043
MODEL QUESTION PAPER-II
B.Tech III Semester End Examinations, December–2024
Regulations: IARE - BT23
COMPUTER SYSTEM ARCHITECTURE
COMPUTER SCIENCE AND ENGINEERING

Time: 3 hour Maximum Marks: 60

Answer ONE Question from each MODULE
All Questions Carry Equal Marks
All parts of the question must be answered in one place only
MODULE-I

1. (a) What is memory address register (MAR) and memory data register (MDR) and Describe
the IEEE standard for floating point numbers for single precisionnumber?[BL:Understand
|CO:1|6M]
(b) Catagorize instruction formats for various types of computer organizations as single accu-
mulator, general register andstack? [BL:Understand |CO:1|6M]

2. (a) Write short notes on the following iii. Floating point arithmetic (addition andmulti-
plication). i. CPU-IOPcommunication ii. Micro programsequencer iii. Floating point
arithmetic (addition andmultiplication). [BL:Understand |CO:1|6M]
(b) Explain Booth’s multiplication algorithm for signed 2’s complement numbers in details,
with a suitable example and give the hard ware requirement [BL:Understand |CO:1|6M]
MODULE-II

3. (a) Describe a scenario where data transfer and data manipulation instructions might be used
together.. [BL:Understand |CO:2|6M]
(b) How does the choice of addressing mode affect instruction execution and program effi-
ciency?. [BL:Evaluate |CO:2|6M]

4. (a) What are the primary characteristics of a RISC (Reduced Instruction Set Computer)
architecture? [BL:Understand |CO:2|6M]
(b) How are instruction codes typically represented in a computer’s instruction set architec-
ture? [BL:Evaluate |CO:2|6M]
MODULE-III

5. (a) Compare and contrast microprogrammed control with hardwired control in terms of im-
plementation and performance.
[BL:Understand |CO:3|6M]
 (b) Describe the role of an I/O interface in managing data transfer between peripheral devices
and the CPU.
[BL:Remember |CO:3|6M]

6. (a) What are the primary considerations when designing a control unit for a microprogrammed
control system? [BL:Remember |CO:3|6M]
(b) How does the daisy chaining method ensure that higher-priority interrupts are serviced
before lower-priority ones? [BL:Understand |CO:3|6M]
MODULE-IV

7. (a) How does the memory hierarchy impact system performance and efficiency?
[BL:Understand |CO:6|6M]
(b) Compare and contrast main memory with cache memory and auxiliary memory in terms
of speed and capacity.
[BL:Apply |CO:6|6M]

8. (a) What is associative memory (or content-addressable memory), and how does it differ from
traditional memory systems? [BL:Remember |CO:3|6M]
(b) What are the different types of cache memory (e.g., L1, L2, L3), and how do they impact
system performance? [BL:Understand |CO:3|6M]
MODULE-V

9. (a) Describe the different types of parallelism that can be exploited in computer systems.
[BL:Apply |CO:6|6M]
(b) What is pipelining in computer architecture, and how does it improve performance?
[BL:Remember |CO:6|6M]

10. (a) How does instruction pipelining affect the throughput and latency of instruction execution?
[BL:Remember |CO:6|6M]
(b) What are the key components of a vector processor, and how do they contribute to its
performance? [BL:Remember |CO:6|6M]

**END OF EXAMINATION**

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COURSE OBJECTIVES:
The course should enable the students to:

I The concepts of register transfer logic and arithmetic operations, instruction

format, and instruction cycle.
II The basic components of computer sysytems, functionality, and interactions with
the components.
III Memory hierarchy, memory management and I/O management.
IV Pipelining and Multiprocessor techniques for the improvement of efficiency

COURSE OUTCOMES:
After successful completion of the course, students should be able to:
CO 1 Demonstrate a thorough understanding of the basic concepts Understand
and principles of computer sysytem architecture.
CO 2 Analyze different types of instruction sets and addressing modes. Analyze
CO 3 Evaluate memeory management techniques such as paging, Evaluate
segmentation and virtual memeory.
CO 4 Compare different I/O techniques, including programmed I/O, Understand
interrupt driven I/O,and direct memory access (DMA) .
CO 5 Explore the implications of parallel processing and apply concepts Analyze
of pipelining and parallelism to enhance sysytem performance.
CO 6 Summarize the concepts of pipelining and interprocess Understand
communication for advanced processor design.

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QUESTION PAPER 1: MAPPING OF SEMESTER END EXAMINATION
QUESTIONS TO COURSE OUTCOMES

Q.No All Questions carry equal marks Taxonomy CO’s PO’s

a What is memory address register (MAR) and Understand CO 1 PO 1
1
memory data register (MDR) and Describe the IEEE
standard for floating point numbers for single
precisionnumber?
b Catagorize instruction formats for various types of Understand CO 1 PO 1
computer organizations as single accu- mulator,
general register andstack?
a Write short notes on the following iii. Floating point Apply CO 1 PO 1
2
arithmetic (addition andmultiplication). i.
CPU-IOPcommunication ii. Micro programsequencer
iii. Floating point arithmetic (addition
andmultiplication).
b Explain Booth’s multiplication algorithm for signed Understand CO 1 PO 1
2’s complement numbers in details, with a suitable
example and give the hard ware requirement
a Describe a scenario where data transfer and data Understand CO 2 PO 1
3
manipulation instructions might be used together..
b EHow does the choice of addressing mode affect Evaluate CO 2 PO 1
instruction execution and program efficiency?
a What are the primary characteristics of a RISC Understand CO 2 PO 1
4
(Reduced Instruction Set Computer) architecture?
b How does the daisy chaining method ensure that Evaluate CO 2 PO 1
higher-priority interrupts are serviced before
lower-priority ones?
a Compare and contrast microprogrammed control Understand CO 3 PO 1
5
with hardwired control in terms of implementation
and performance.
b Describe the role of an I/O interface in managing Remember CO 3 PO 1
data transfer between peripheral devices and the
CPU.
a What are the primary considerations when designing Remember CO 3 PO 1
6
a control unit for a microprogrammed control
system?
b How does the daisy chaining method ensure that Understand CO 3 PO 1
higher-priority interrupts are serviced before
lower-priority ones?
a How does the memory hierarchy impact system Understand CO 6 PO 1
7
performance and efficiency?

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 b Compare and contrast main memory with cache Apply CO 6 PO 1
memory and auxiliary memory in terms of speed and
capacity.
a What is associative memory (or content-addressable Remember CO 3 PO 1
8
memory), and how does it differ from traditional
memory systems?
b What are the different types of cache memory (e.g., Understand CO 3 PO 1
L1, L2, L3), and how do they impact system
performance?
a Describe the different types of parallelism that can Apply CO 6 PO 1
9
be exploited in computer systems.
b What is pipelining in computer architecture, and Remember CO 6 PO 1
how does it improve performance?
a How does instruction pipelining affect the Apply CO 6 PO 1
10
throughput and latency of instruction execution?
b What are the key components of a vector processor, Remember CO 6 PO 1
and how do they contribute to its performance?

KNOWLEDGE COMPETENCY LEVELS OF MODEL QUESTION PAPER

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BLOOMS TAXONOMY

Signature of Course Coordinator HOD,CSE

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