Electronics and Communications Dept.

Electronics and Communications Lab

Fourth Year Experiment Number :(7)

M-ary Orthogonal FSK Modulation (MFSK)

Objective:-
To study and implement the multiple frequency-shift keying (MFSK) modulation.

Equipment:-
- Oscilloscope.
- Function generator with VCO input.
- Pulse generator.
- DC power supply.
- 741 Op-Amp
- LM324 Quad Op-amp
- 74LS00 quad NAND gate
- 74LS93 Binary Counter IC
- PN diode, resistors and capacitors

Theory:-
An M-ary FSK is a type of digital modulation where instead of transmitting
one bit at a time, two or more bits are transmitted simultaneously. This type of
modulation is usually operated as an orthogonal modulation scheme and is
therefore power efficient. Accordingly, it is useful in power-limited channels to
conserve transmitted power at the expense of added bandwidth and receiver
equipment complexity. This technique is illustrated in Fig. 1, which shows how
multilevel signals can be generated from a serial binary input stream by using a
digital-to-analog converter (DAC).

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Electronics and Communications Lab. Experiment No. (7)
Fourth Year M-ary Frequency Shift Keying

Figure 1. Multi-level digital modulation system.

The modulator takes blocks of ℓ successive binary digits and assigns one of M
possible waveform, S1(t), S2(t)… SM(t) to each block (𝑀 = 2ℓ ) which is
transmitted during a signaling interval of duration 𝑇𝑆 = 𝑇𝑏 𝑙𝑜𝑔2 𝑀 where 𝑇𝑏 is the
bit interval. These signals are generated by changing the frequency of the carrier in
M discrete steps. A block diagram of a practical circuit for the modulator is shown
in fig. (2). The block of ℓ bits during a signaling interval of duration 𝑇𝑆 are input
to a DAC producing one of 𝑀 = 2ℓ analog output level which is converted
through the VCO to one of the M signaling frequencies.

Figure 2. M–ary FSK modulator.

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 Electronics and Communications Lab. Experiment No. (7)
Fourth Year M-ary Frequency Shift Keying

The orthogonal signals have the following properties:

Acosωi t o ≤ t ≤ TS
Si(t) = (1)
0 else where

𝑇𝑠 𝐴2 𝑇𝑠 ⁄2 = 𝐸, i = j
∫0 𝑆𝑖 (𝑡) 𝑆𝑗 (𝑡) 𝑑𝑡 = { (2)
0, i ≠ j

where E is the average energy per symbol interval.

Equations (1) and (2) imply that the signals are of duration 𝑇𝑆 , have equal energy
and are orthogonal to each other over the interval (0, 𝑇𝑆 ). The orthogonal
conditions enable us to uniquely identify each signal at the receiver.

To minimize the overall bandwidth of the transmitted M-ary FSK signal we

required a minimum frequency separation between the orthogonal signals of

1
𝑓𝑚 − 𝑓𝑛 = (3)
2𝑇𝑆

Since it may be easily shown that the minimum frequency separation is one half
cycles per signaling interval between two signals in order for them to be
orthogonal over (0, 𝑇𝑆 ). Therefore, the minimum net bandwidth required in
signaling is:

𝑀
𝐵𝑚𝑖𝑛 = (4)
2𝑇𝑆

Procedure:-
PART ONE: MFSK MODULATION
In the experiment, we shall build a quaternary orthogonal FSK modulator (ℓ = 2).
For the purpose of demonstration, we may dispense with the serial- to- parallel
converter (shown in Fig.2) and use a two stage binary ripple counter as shown in
Fig.(3). The two output of the ripple counter are assumed to be P1 and P2, thereby
providing the four possible combinations 00,01,10,11 in succession.

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Electronics and Communications Lab. Experiment No. (7)
Fourth Year M-ary Frequency Shift Keying

1. Build the counter shown in Fig. (3) using two stages of the 74LS93 binary
counter as shown in Fig. (4). The input of the counter is a square wave of
frequency 2KHz. Sketch to scale the waveform P1 and P2. Also calculate
the symbol duration (signaling interval 𝑇𝑆 ).

2. Build a 2-bit DAC as shown in Fig. (5). The output is a staircase waveform
whose step size depends on the values of the resistances used. Fix 𝑅3 and
use decade boxes for 𝑅1 and 𝑅2 . Adjust their values so that the step size is
uniform to ensure signal orthogonality. Measure the analog output voltage
for each possible binary input and draw the staircase waveform.

3. Apply the output of the DAC to a VCO with a free running frequency of 10
KHz. Measure and sketch all output frequencies corresponding to the
staircase waveform from run 2.

Figure 3. 74LS93 binary ripple counter.

Figure 4. 74LS93 pin diagram.

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Electronics and Communications Lab. Experiment No. (7)
Fourth Year M-ary Frequency Shift Keying

Figure 5. 2-bit DAC.

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Electronics and Communications Lab. Experiment No. (7)
Fourth Year M-ary Frequency Shift Keying

PART TWO: MFSK DEMODULATION

In the part, we shall build a circuit to recover the message from the MFSK signal
obtained in part 1.

Refer to figure 6, the proposed demodulator uses a similar idea that has been used
previously in FSK detection (i.e. slope detection method). Despite that a HPF is
used here instead of BPF but it is also operated in the transition region of the filter
characteristics. In other words, the HPF is designated with 𝑓𝐶 ≥ 𝑓3 (where f3 is the
highest frequency of the MFSK signal). The output of the filter still represents an
MFSK signal but each frequency range is attenuated differently (f0 has the lowest
amplitude whereas f3 has the greatest amplitude) as shown in figure 6.

An envelope detector is used to smooth the signal to appear like a staircase signal
(similar to the analog output of DAC in figure 2). Lastly, this analog –staircase-
signal is applied to an analog-to-digital converter to produce the same binary
message (00,01,10,11 in succession) used in the modulation.

Figure 6. M–ary FSK demodulator.

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Electronics and Communications Lab. Experiment No. (7)
Fourth Year M-ary Frequency Shift Keying

4. Design a passive RC HPF with 𝑓𝐶 ≥ 𝑓3 (where f3 represents the highest

possible frequency of the MFSK signal).

5. Choose proper values for R and C to build an envelope detector that

produces a smooth (or least ripple) staircase signal.

6. Build a parallel flash ADC circuit as shown in figure 7. Set Vref to +5V
while Vin represents the analog staircase signal from the envelope detector.
Note that the practical ADC circuit uses only NAND gates instead of AND,
OR, and NOT gates shown in figure 7 because it is more convenient in lab
(however it requires to convert the expressions of D0 and D1 into NAND
operations only).

Figure 7. 2-bit flash ADC.

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 Electronics and Communications Lab. Experiment No. (7)
Fourth Year M-ary Frequency Shift Keying

Report:-
1. Discuss the result of run (3).

2. Draw a block diagram for the optimum receiver for M-ary orthogonal
signaling. Describe its operation.

3. In your own words, explain briefly the operation of each block of figure 6.

4. For the flash ADC, use Karnaugh map to derive an expression for D0 in
terms of NAND gates only and draw the resulting logic circuit.

5. Based on figure 7, fill the following operation table of the ADC

𝑉𝑖𝑛 𝑇2 (𝑉 ) 𝑇1 (𝑉) 𝑇0 (𝑉) 𝐷1 𝐷0

𝑉𝑖𝑛 < 𝑉𝑟𝑒𝑓 /4

𝑉𝑟𝑒𝑓 /4 < 𝑉𝑖𝑛 < 𝑉𝑟𝑒𝑓 /2

𝑉𝑟𝑒𝑓 /2 < 𝑉𝑖𝑛 < 3𝑉𝑟𝑒𝑓 /4

𝑉𝑖𝑛 > 3𝑉𝑟𝑒𝑓 /4

References:-
1. “Modern digital and analog communication systems” by F.G.
Stremler, 2nd edition, 1982.

2. “Digital and analog communication systems” by L.W. Couch, 7th

edition, 2007.
3. “Digital communications” by I. Glover, 3rd edition, 2010.

4. “Microelectronics” by Jacob Millman, 2nd edition, 1987.

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