ECSE-325

Digital Systems

Lab #2 – Simulation with QuestaSim Winter 2024

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 Introduction .
In this lab you will learn the basics of digital simulation using the QuestaSim
simulation program.

In this lab and subsequent labs, you will work towards creating a circuit to
implement the SHA256 hashing function used in Bitcoin mining. This function
takes in a long message and compresses (hashes) it to a 256-bit message digest.
The hashing function is such that the original message is not easy (i.e. practically
impossible) to derive from the message digest.

More details will be given on the SHA256 function in later labs. But if you want
to get a head start you can read:
https://nvlpubs.nist.gov/nistpubs/FIPS/NIST.FIPS.180-4.pdf

In this lab you will just describe and simulate some building blocks for the circuit.

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One of the main building blocks of the SHA256 system is the Hash Core Logic.
In this lab you will just describe and simulate the ∑0 , ∑1 Maj and Ch blocks.

Source: opencores.org ECSE 325 W2021 3

 The Maj function is the “Majority” operation, which outputs the bit value (0 or 1) that
is most common in the 3 inputs.

The Ch function is merely a 2-input multiplexer.

B_o A_o

MAJ
C_o E_o

F_o
CH

G_o

Each of the inputs and outputs of these blocks is a 32-bit word.

The AND and XOR operations are bit-wise operations.
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Each of the inputs and outputs of these blocks is a 32-bit word.
The XOR operations are bit-wise operations.

A_o

SIG0

E_o

SIG1

Each of the rectangles indicate “Rotate Right by N” operations. For example, Rotate
right by 25 means to shift the bits rightward (towards the LSB) by 25 places, and the
bits that are shifted beyond bit 0 (LSB) get shifted back into the higher bits.
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Hint: to implement Rotation operations you do not need any Boolean logic. You
just need to remap the bits.

For example, suppose we had an 8-bit vector X(7 downto 0) and wanted to
perform a Rotate Right by 5 operation. We can do this with the following VHDL
statements:

Y(2 downto 0) <= X(7 downto 5);

Y(7 downto 3) <= X(4 downto 0);

This can be condensed into one statement using the concatenation operator:

Y <= X(4 downto 0) & X(7 downto 5);

There is also a builtin VHDL function to do the Rotate Right operation called ror:

Y <= X ror 5;

Finally, you could use a VHDL function defined for UNSIGNED numbers:

Y <= std_logic_vector(rotate_right(unsigned(X), 5));

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VHDL Description of the SIG, CH, MAJ circuit.

Using the following form for the entity declaration (replace the values in the header with
your own information), write the complete VHDL entity description for a circuit that
implements the SIG0, SIG1, CH, and MAJ operations (you did this in assignment 3).

--
-- entity name: gNN_SIG_CH_MAJ (replace “NN” by your group’s number)
--
-- Version 1.0
-- Authors: (list the group member names here)
-- Date: February ??, 2024 (enter the date of the latest edit to the file)

library ieee; -- allows use of the std_logic_vector type

use ieee.std_logic_1164.all;
use ieee.numeric_std.all; -- needed if you are using unsigned rotate operations

entity gNN_SIG_CH_MAJ is
port ( A_o, B_o, C_o, E_o, F_o, G_o : in std_logic_vector(31 downto 0);
SIG0, SIG1, CH, MAJ : out std_logic_vector(31 downto 0);
);
end gNN_SIG_CH_MAJ;

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 Simulation of the gNN_SIG_CH_MAJ circuit using QuestaSim
In this course, we will be using the QuestaSim simulation software, created by the
company Mentor Graphics (we will use a version of it specific to Quartus, called
QuestaSim-Altera).

The QuestaSim software operates on a Hardware Description Language (HDL)

description of the circuit to be simulated, written either in VHDL, Verilog, or System-
Verilog. You will use VHDL.

Run the Quartus program and create a new project called gNN_SIG_CH_MAJ (where
“NN” is your group number). Set the device to Cyclone V 5CSEMA5F31C6

Create a new VHD file, named gNN_SIG_CH_MAJ.vhd, and enter your design entity
description. Run “Processing/Start/Start Analysis and Elaboration” on the VHDL file
(we don’t need to do the synthesis/fitting steps) and correct any errors you might have.

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Next, select the QuestaSim program from the Windows Start menu.
A window like the one shown below will appear.

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Select FILE/New/Project and, in the window that pops up, give the project the
name “gNN_SIG_CH_MAJ”

Click OK.

Another dialog box will appear, allowing you to add files to the project. Click
on “Add Existing File” and select the VHDL file that was generated earlier
(gNN_SIG_CH_MAJ.vhd). You can also add files later.

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The QuestaSim window will now show this vhdl file in the Project pane.

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In order to simulate the design, QuestaSim must analyze the VHDL files, a
process known as compilation.

The compiled files are stored in a library. By default, this is named “work”. You
can see this library in the “library” pane of the QuestaSim window.

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The question marks in the Status column in the Project tab indicate that either
the files haven’t been compiled into the project or the source file has changed
since the last compilation. To compile the files, select Compile > Compile All
or right click in the Project window and select Compile > Compile All.

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If the compilation is successful, the question marks in the Status column will
turn to check marks, and a success message will appear in the Transcript pane.

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The compiled vhdl files will now appear in the library “work”.

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In the library window, double-click on gNN_SIG_CH_MAJ. This will open some
windows, which will be used in doing the simulation of the circuit.

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You are not quite ready to start the simulation yet!
In the “Objects” window, the signals may have the value “UUUUUU”. This means that all
the inputs are undefined. If you ran the simulation now, the outputs would also be
undefined.

So, you need to have a means of setting the inputs to certain patterns, and of observing the
outputs' responses to these inputs.

In QuestaSim, this is done by using a special VHDL entity called a Testbench.

A testbench is some VHDL code that generates different inputs that will be applied to your
circuit so that you can automate the simulation of your circuit and see how its outputs
respond to different inputs.

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It is important to realize that the testbench is only used in QuestaSim for the
purposes of simulating your circuit. You will NOT synthesize the testbench into
real hardware.

Because of its special purpose (and that it will not be synthesized), the testbench
entity is unique in that it has NO inputs or outputs and uses some special
statements that are only used in test benches. These special statements are not
used when describing circuits that you will later synthesize to a FPGA.

The testbench contains a single component instantiation statement that inserts

the module to be tested (in this case the gNN_SIG_CH_MAJ module), as well as
some statements that describe how the test inputs are generated.

After you gain more experience, you will be able to write VHDL testbenches from scratch.
However, Quartus has a convenient built-in process, called the Test Bench Writer, which
produces a VHDL template from your design that will get you started.

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Go back to the Quartus program, making sure that you have the
gNN_SIG_CH_MAJ project loaded.

Then, in the Processing toolbar item, select Start/Start Test Bench

Template Writer

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This will generate a VHDL file named gNN_SIG_CH_MAJ.vht and place it in the
simulation/QuestaSim directory. Open it up in Quartus. It will look something like this:

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Note that the template already includes the instantiation of the
gNN_SIG_CH_MAJ component.

It also includes the skeletons of two “process” blocks, one labeled “init” and
the other labeled “always”.

The init process block can be left blank for this lab but is usually used to
specify initial signal values and other initial conditions for the simulation.

You should edit the “always” process block to suit your needs, so in this case
it will be used to generate the input signal waveforms.

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 As a first test, enter the following code into the testbench file:
-- delete the init process block

always : PROCESS
-- optional sensitivity list
-- ( )
-- variable declarations
BEGIN
-- code executes for every event on sensitivity list
A_o <= x"FF000000";
B_o <= x"00FF0000";
C_o <= x"0000FF00";
E_o <= x"000000FF";
F_o <= x"AA000000";
G_o <= x"00000099";

WAIT FOR 10 ns;

A_o <= x"37000000";

B_o <= x"00432100";
C_o <= x"00007780";
E_o <= x"00000321";
F_o <= x"AA000000";
G_o <= x"0500D032";

WAIT FOR 5 ns;

A_o <= x“006c0000";

B_o <= x"09912100";
C_o <= x"00000000";
E_o <= x"00000642";
F_o <= x"AA000000";
G_o <= x“80000001";

WAIT;
END PROCESS always;
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Once you have finished editing the testbench file, you need to add it to the
project in QuestaSim (make sure you are in the “Project” pane):

Once the testbench file has been added to the project, you should select the
testbench file in the Project pane and click on Compile Selected from the
Compile toolbar item. This will compile the testbench file.
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Now everything is ready for you to actually run a simulation!

Select “Start Simulation” from the Simulate toolbar item in the QuestaSim program.
The following window will popup:

Select the
gNN_sig_ch_maj_tst entity
(expand the “work” item to
find this) and click on OK

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The QuestaSim window should now look like this. Enter a value of 20ns into
the simulation length window.

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To display waveforms, open the wave window by selecting it in the View menu.

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At first, the “Wave” window will not have any signals in it. You can drag signals from
the “Objects” window by clicking on a signal, holding down the mouse button, and
dragging the signal over to the Wave window. Do this for all the signals.

The Wave window will now look like this:

Now, to actually run the simulation, click on the

“Run” icon in the toolbar (or press the F9 key). 27
Since we are working with 32-bit vector signals, it is inconvenient to view their values
as binary vectors. Instead, set the “Runtime Options” from the Simulate menu and set
the “Default Radix” to Hexadecimal.

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Here is the output you should get (you can right-click in the right-hand pane
and select “Zoom Full” to see the entire time range).

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To see the individual bits in a vector, click on the “+” next to the signal name
in the left-hand column. There are a lot of bits so usually you wouldn’t want to
do this unless you are trying to locate a glitch.

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If you get an incorrect output waveform, you will have to go back and look at
your design. If you make a correction to either of your schematic diagrams, you
will have to re-run the conversion to VHDL (using the File/Create/Update/Create
HDL Design File from Current File… command).

Then you will have to re-run the compilation of the changed files in QuestaSim.

Finally, to rerun the simulation, first click on the “Restart” button, then click on
the “Run” button.

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 Further Testing of the Project using QuestaSim

The simulation you ran in the previous part of the lab just had a couple of input signal
transitions and did not test all possible input patterns.

There are 2^192 or 6.28x10^57 possible input patterns, and complete testing of the circuit
will require you to simulate all these patterns. This is clearly impractical. The best we can do
is random test pattern generation and testing of corner conditions (e.g. all zeros or all ones).

Modify the testbench file to add in 25 more test patterns.

These test patterns should be generated by using a FOR LOOP, with a WAIT of 5 nsec per
loop, and a total of 25 loops.

On each loop, feed the SIG0 output to the A_o input, the SIG1 output to the C_o input, the
MAJ output to the E_o input and the CH output to the G_o input.

This will produce a somewhat varied (not random) set of test patterns.

Rerun the simulation with this amended testbench. You will have to change the run time of
the simulation, since you have more transitions.
Capture a screenshot of the resulting wave display for your report. Make sure that
hexadecimal values are shown for the signal vector values.
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Writeup the Lab Report .

Write up a short report describing the gNN_SIG_CH_MAJ circuit that you

designed and simulated in this lab. This report should be submitted in pdf format.

The report must include the following items:

• A header listing the group number, the names and student numbers of each group
member.
• A title, giving the name (e.g. gNN_SIG_CH_MAJ ) of the circuit.
• A description of the circuit's function, listing the inputs and outputs.
• The VHDL description of the circuit.
• The final version of the testbed file.
• A screenshot of the simulation results for the final simulation run. This should
show clearly the hexadecimal values of the signals over the simulation time
interval.

The report is due two weeks after the end of the lab period (i.e. on March 15),
at 11:59 PM (an extra week is due to the reading break).

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 Submit the Lab Report to myCourses .

The lab report, and all associated design files (by design files, I mean the vhdl and
testbench (.vhd and .vht) files) must be submitted, as an assignment to the
myCourses site. Only one submission need be made per group (both students will
receive the same grade).

Combine all of the files that you are submitting into one zip file and name the
zip file gNN_LAB_2.zip (where NN is your group number).

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