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Ece 325 Midterm

ece325Midterm

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30 views9 pages

Ece 325 Midterm

ece325Midterm

Uploaded by

Junbo Wang
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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McGILL UNIVERSITY

Department of Electrical and Computer Engineering

ECSE-325 Digital Systems Winter 2024

MIDTERM EXAMINATION
(take-home exam, due midnight Thursday February 22)

Question Part a) mark Part b) mark Total

ALL /14 /26 /40


(Knowledge Base) (Design)

Name: _____________________________________________________________

Student Number: ____________________________________________________

Instructions/Please read carefully!


This is an open book exam. You are expected to work by yourself, with no
assistance. No time extensions will be allowed.

You should submit your answers on myCourses in the same way that you did
for the assignments.
Read the questions carefully. If something appears ambiguous, write down
your assumptions.
COURSE: ECSE – 325 MIDTERM EXAM WINTER 2024 2
YOUR NAME:
________________________________________________________________________
Question 1: CMOS Circuits (10 points)

(3 points) a) Write down the Boolean function implemented by the


CMOS circuit shown. Be careful to trace out which transistor is
connected to which.
Express the function Q(A,B,C) in SOP form.

ANSWER: Q(A,B,C) =
COURSE: ECSE – 325 MIDTERM EXAM WINTER 2024 3
YOUR NAME:
________________________________________________________________________
(7 points) b) Draw a CMOS circuit that implements the 2-bit less-than
operation given by the Boolean expression below.
Assume that the inverse inputs are also available (you do not need to
explicitly generate the inverted values for the inputs A0,A1,B0,B1).

L(A1,A0,B1,B0) = (A1’A0’B0+A0’B1B0+A1’B1)

( ’ indicates the logical complement )


COURSE: ECSE – 325 MIDTERM EXAM WINTER 2024 4
YOUR NAME:
________________________________________________________________________
Question 2: Programmable Logic Devices (10 points)

(5 points) a) Write the Boolean functions O0,O1, O2, O3(I0,I1,I2,I3,I4)


implemented by the following PLA:

ANSWER: O1 =
ANSWER: O2 =
ANSWER: O3 =
ANSWER: O4 =
COURSE: ECSE – 325 MIDTERM EXAM WINTER 2024 5
YOUR NAME:
________________________________________________________________________

(5 marks) b) Using the PAL diagram shown below, draw the connections
that will program the PAL to implement the 2-bit comparison functions
(where A=(A1,A0) and B=(B1,B0) are interpreted as numbers):
L(A,B) = A < B (see question 1b), G(A,B) = (A > B), and E(A,B) = (A = B).

L(A1,A0,B1,B0)

G(A1,A0,B1,B0)

E(A1,A0,B1,B0)

A1 A0 B1 B0
COURSE: ECSE – 325 MIDTERM EXAM WINTER 2024 6
YOUR NAME:
________________________________________________________________________
Question 3: Memory Circuits (10 points)
(3 points) a) Write down the 5-bit values (B4,B3,B2,B1,B0) stored in each
of the four memory locations in this NOR ROM circuit, as addressed by the
four word line bits (W0,W1,W2,W3.

ANSWER: [W0]:________
[W1]:________
[W2]:________
[W3]:________
COURSE: ECSE – 325 MIDTERM EXAM WINTER 2024 7
YOUR NAME:
________________________________________________________________________
(7 points) b) Draw a NAND ROM circuit that implements the same
functions as the PAL circuit you designed in question 2b (i.e. the L, G and E
signals as a function of the four inputs (A1, A0, B1, B0)).
You do not need to design the address decoder, just include it as a block
symbol.
COURSE: ECSE – 325 MIDTERM EXAM WINTER 2024 8
YOUR NAME:
________________________________________________________________________

Question 4: VHDL (10 points)

(3 marks) a) Write down the count sequence generated by the counter


described in the following VHDL design entity, after being reset.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Q4B is
port (clock_25MHz : in std_logic;
reset : in std_logic;
count : out std_logic_vector(4 downto 0)
);
end Q4B;

architecture a of Q4B is
signal counti : integer range 0 to 25;
begin
count <= std_logic_vector(to_unsigned(counti,5));

process(clock_25MHz)
begin
if (reset = ‘1’) then
counti <= 12;
elsif rising_edge(clock_25MHz) then
counti <= counti + 2;
if (counti = 24) then
counti <= 13;
elsif (counti = 25) then
counti <= 12;
end if;
end if;
end process;

end a;
COURSE: ECSE – 325 MIDTERM EXAM WINTER 2024 9
YOUR NAME:
________________________________________________________________________
(7 marks) b) Write a complete VHDL design entity describing the Cyclic-
Redundancy-Code (CRC) circuit shown below. The flipflops have
complementary clock inputs, but for the purposes of this question, assume
that the flipflops trigger on the rising edge of the C input. The RB input of
the flipflops is an asynchronous clear (sets the output Q of the flipflop to 0
when RB is high).

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