Digital Circuits

ECE 212

Lecture 10
Data Sequencing
Mohamed Dessouky
Integrated Circuits Laboratory
Ain Shams University
Cairo, Egypt
[email protected]

Digital Circuits – ECE212 – S24

Outline

• Clock Non-Idealities
– Clock Skew
– Clock Jitter

• Digital Constraints throughout the Design Cycle

M. Dessouky Digital Circuits – ECE212 – S24

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 Sequencing Timing: Design Problem

Given:
• Pre-defined Flip-Flops
• Clock speed (Tc)
• Clock non-idealities: this lecture
Design variables are:
• CL delay: tpd and tcd

M. Dessouky Digital Circuits – ECE212 – S24

Chip-Level Clock Distribution

FF FF FF FF FF FF

FF FF FF FF FF FF

Clock
FF FF FF FF FF FF

FF FF FF FF FF FF

Representation of clock distribution

• On all digital chips, registers are used to synchronize all operations.
• Clock signals are essential for synchronization.
• Clock signals are:
– loaded with the largest fanout.
– travel over the greatest distance.
– operate at the highest speeds

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 Clock Skew

• Spatial variation in arrival time of clock edges.

• Results in a constant clock phase shift.
• tskew can be +ve or –ve.

M. Dessouky Digital Circuits – ECE212 – S24

Design Variable: tpd vs. FF Setup Time

clk clk

Q1 D2
F1

F2

Combinational Logic

Tc

tsetup
clk
tpcq

Q1 tpd

D2

CL: tpd
CL is changing

• Operation: data produced by F1 must be processed by the CL

and be ready at F2 input before the next clk edge

Tc  t pcq  t pd  t setup t pd  Tc  t setup  t pcq 

toverhead
M. Dessouky Digital Circuits – ECE212 – S24

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 Skew Impact: tpd
clk clk

Q1 D2

F1

F2
Combinational Logic

Tc

clk
tpcq
tskew

Q1 tpdq tsetup
negative
clock skew
D2

t pd  Tc  t skew  t setup  t pcq 

• Negative skew (tskew < 0)
– Lower effective cycle time. Limits speed performance.
• Positive skew (tskew > 0)
– Higher effective cycle time. Enhances speed performance

M. Dessouky Digital Circuits – ECE212 – S24

Design Variable: tcd vs. FF Hold Time

clk
• If CL delay is too short,
Q1
data from Q1 can reach
F1

CL
F2 at the same clk
edge (race through). clk
• At F2, the fast data D2
F2

violates the hold time of

the previous state and
distorts stored data clk
• In order to prevent hold
tcd
time violation: Q1 tccq

thold  tccq  tcd D2 thold

or
Previous state Next state
tcd  thold  tccq
CL: tpd

M. Dessouky Digital Circuits – ECE212 – S24

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 Skew Impact: tcd
tcd  thold  t skew  tccq clk

Q1

F1
CL
• Positive skew (tskew > 0)
– Higher effective hold time
clk
– More risk of race through
D2

F2
positive
• Negative skew (tskew < 0) clock skew
– Lower effective hold time. tskew
– Relaxes race through clk
thold

Q1 tccq

D2 tcd

M. Dessouky Digital Circuits – ECE212 – S24

Positive and Negative Skew Design

R1 R2 R3
In Combinational Combinational
D Q D Q D Q •••
Logic Logic

CLK tCLK1 tCLK2 tCLK3

delay delay
Clk is routed in the same Increases throughput (speed)
direction of data flow (a) Positive skew but beware of racing

R1 R2 R3
In Combinational Combinational
D Q D Q D Q •••
Logic Logic

tCLK1 tCLK2 tCLK3

delay delay CLK

Clk is routed in the opposite Avoids racing but limit
direction of data flow (b) Negative skew system performace

M. Dessouky Digital Circuits – ECE212 – S24

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Positive and Negative Skew Design (2)

• Most often, datapaths have feedback.

• Data flows in both directions causing both +ve and –ve skews.
• Design of a low skew clock network is essential.

M. Dessouky Digital Circuits – ECE212 – S24

Clock Jitter

• Temporal variations in clock edges at a given point on the chip.

• Results in continuous clock period variation.
• In general, each clock period has a different jitter.
• tjitter is the maximum absolute jitter.

M. Dessouky Digital Circuits – ECE212 – S24

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 Jitter Impact: tpd
clk clk

Q1 D2

F1

F2
Combinational Logic

Tc

clk
tjitter tpcq
tjitter

Q1 tpdq tsetup

D2

• Since jitter is variable, we’ll consider the worst case.

• Worst case: F1 has a +ve jitter, while F2 has a –ve jitter
t pd  Tc  2t jitter  t setup  t pcq 

• Similar to –ve skew

M. Dessouky Digital Circuits – ECE212 – S24

Jitter Impact: tcd

clk
• Worst case:
Q1
F1 has a –ve jitter, while
F1

CL

F2 has a +ve jitter

tcd  thold  2t jitter  tccq clk

D2
F2

• Similar to +ve skew

2tjitter

clk
thold

Q1 tccq

D2 tcd

M. Dessouky Digital Circuits – ECE212 – S24

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 Combined Skew and Jitter Effect

• In general, we have both skew and jitter.

• Therefore
t pd  Tc  t skew  2t jitter  t setup  t pcq 

tcd  thold  t skew  2t jitter  tccq

• Note that:
– The sign of tskew might be +ve or –ve, while
– The sign of tjitter does not change since it was derived based
on worst-case conditions.

M. Dessouky Digital Circuits – ECE212 – S24

Outline

• Clock Non-Idealities

• Digital Constraints throughout the Design Cycle

M. Dessouky Digital Circuits – ECE212 – S24

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 Standard-Cell ASIC Design Flow
Simulation

Behavioral View - RTL Functional Verification Stimuli

(VHDL/Verilog/SystemVerilog)

Logic Logic/Timing
Automated
Synthesis
Gate-level Netlist Pre-characterized
(Spice/VHDL/Verilog) Standard Cell Library
(Verilog/Spice/GDSII)
Automated Placement
& Routing Layout/Timing
Layout
CIF or GDSII

M. Dessouky Digital Circuits – ECE212 – S24

Slack

• Slack is defined as the difference between the required arrival

time of a signal and it's actual arrival time.
slack  Tc  t skew  2t jitter  t setup   t pd  t pcq 
• For proper operation, the slack should always be positive.
• Defined per Flip-Flop. The larger, the better.
• Indicates how much the design complies to maximum frequency
timing constraints.
• Important design parameter used to judge CAD tool results.
M. Dessouky Digital Circuits – ECE212 – S24

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 Design Corners
• The cell library should be well analyzed, sized, characterized
and have all its views (schematics, HDL, layout, timing, …)
available to be manipulated by the EDA tools.

• During IC fabrication, transistor parameters can vary within a

certain margin.
• During IC operation, both the power supply and temperature can
vary, both affecting circuit speed.
• The standard-cell library is characterized with the typical and
worst case slow and fast conditions. Called corners.
• To take this into account, usually use the worst case delays in
t pd  Tc  t skew  2t jitter  t setup  t pcq  Use slow corner

tcd  thold  t skew  2t jitter  tccq Use fast corner

M. Dessouky Digital Circuits – ECE212 – S24

Digital Constraints

• Constraints: t pd  Tc  t skew  2t jitter  t setup  t pcq 

tcd  thold  t skew  2t jitter  tccq
• During design phase:
– tpd (setup) violations  make the logic faster, redesign
– tcd (hold) violations  insert buffers to increase the delay

• After chip fabrication:

– tpd (setup) violations  lower clock frequency
– tcd (hold) violations  more dangerous, sometimes no solution!!

• To make faster circuits, system clock speed can be improved at:

– Technology level  faster devices (new process technology)
– Circuit level  faster logic gates (different topology)
– Architecture level  pipelining

M. Dessouky Digital Circuits – ECE212 – S24

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 Pipelining

CL
(A+B)

Tc min  t pcq  t pd  tsetup

• Register-to-Register delay: delay path that sets the maximum

clock rate
• Latency: Number of clock cycles between input and output data
• In this case, Latency = 1 CLK cycle
• From a design point of view, can only act on the CL between the
registers
– Need to shorten the maximum combinational delay path
– Setup/Hold time of registers are fixed

M. Dessouky Digital Circuits – ECE212 – S24

Pipelining (2)
F1 F2 F3

Data-in (A) (B) Data-out

Data-in

Data-out

• Break longest delay path by placing a register in the CL

t pd
Tc min  t pcq   t setup
2
• Latency = 2 CLK cycles

M. Dessouky Digital Circuits – ECE212 – S24

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 Pipelining (3)
F1 F2 F3

Data-in (A) (B) Data-out

• While B is processing, a new data wave enters A

• Adding pipeline stages always increases latency, but increases
throughput of entire workload (clock speed).
• Can break logic indefinitly?
• At some point, adding more pipeline stages does not increase
clock frequency because tpcq and tsetup dominate delay.
t pd
Tc min  t pcq   t setup
2
• Increased area due to added registers

M. Dessouky Digital Circuits – ECE212 – S24

References

• Rabaey sections 10.3.1, 7.5

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