COA Numerical

1. A computer uses RAM chips of 1024*1 capacity.

a. How many chips are needed & how should their address lines be
connected to provide a memory capacity of 1024*8.
b. How many chips are needed to provide a memory capacity of 16 KB?
Solution:

A computer uses RAM chips of 1024*1 capacity.

How many chips are needed & how should their address lines be connected to provide a memory
capacity of 1024*8?

To determine how many RAM chips are needed and how their address lines should be connected
to provide a memory capacity of 1024 × 8 bits, we need to break down the problem based on the
given and required configurations.
Given:
Each RAM chip has a capacity of 1024 × 1 bits (1024 memory locations, each storing 1 bit).
The required memory capacity is 1024 × 8 bits (1024 memory locations, each storing 8 bits).
Step 1: Number of Chips Required
Each RAM chip provides 1024 × 1 bits, and we need a total of 1024 × 8 bits. So, to determine
how many chips are required, we divide the total required memory by the memory capacity per
chip:
Number of chips=Required memoryMemory per chip=1024×8

Step 2: Address Lines for the RAM Chips

Each chip has 1024 memory locations, so to address these locations, we need enough address
lines to uniquely address 1024 locations. The number of address lines required is determined by
the following equation:

Thus, each chip requires 10 address lines to access its 1024 memory locations.
Step 3: Address Line Organization
Total address space: Since you need to address 1024 × 8 bits (which is 1024 memory locations,
each 8 bits wide), the total number of address lines for the entire memory system must be able to
address 1024 memory locations. To do this, you need 10 address lines for the 1024 locations (as
determined above).
Chip selection: Since you need 8 chips to provide the 8 bits per memory location, you need
additional address lines to select which of the 8 chips to access. The number of chip select lines
required is determined by the number of chips:

Thus, 3 additional address lines are required for chip selection.

Final Address Line Breakdown
Address lines for the memory locations: 10 lines (to address the 1024 locations).
Chip select lines: 3 lines (to select which chip to use).
Conclusion
To provide a memory capacity of 1024 × 8 bits, you need:
8 RAM chips, each of 1024 × 1 bits capacity.
10 address lines to address the 1024 memory locations.
3 additional chip select lines to select between the 8 chips.
So, the total number of address lines required will be 10 + 3 = 13 address lines.
How many chips are needed to provide a memory capacity of 16 KB?
 A) To determine the number of bits in the tag, index, block, and word fields of the
address format, we need to consider the given information.
B) The memory unit has a capacity of 64K * 16, which means it can store 64K words,
and each word is 16 bits long.
C) The cache memory has a capacity of 1K words and uses direct mapping with a block
size of four words.
To calculate the number of bits in each field:
 The word field is determined by the size of each word, which is 16 bits.
 The block field is determined by the block size, which is four words. Since each word is 16 bits,
the block field will be log2(4) = 2 bits.
 The index field is determined by the number of blocks in the cache. Since the cache has a
capacity of 1K words and each block contains four words, the number of blocks in the cache is
1K/4 = 256. Therefore, the index field will be log2(256) = 8 bits.
 The tag field is determined by the remaining bits in the address format after accounting for the
word, block, and index fields. In this case, the address format is 16 bits, and we have already
accounted for 16 (word) + 2 (block) + 8 (index) = 26 bits. Therefore, the tag field will be 16 - 26
= -10 bits. However, since a negative number of bits is not possible, we can conclude that there is
no tag field in this address format.
b. Each word in the cache is 16 bits long, as determined by the memory unit's word size. The bits in each
word can be divided into different functions, including:
 Data: The actual data stored in the cache, which is typically the main purpose of the cache.
 Valid bit: A flag that indicates whether the data in the cache is valid or not. This bit is used to
determine if the cache contains the requested data or if it needs to be fetched from the main
memory.
c. To calculate the number of blocks the cache can accommodate, we need to divide the cache's capacity
by the block size. The cache has a capacity of 1K words, and each block contains four words. Therefore,
the number of blocks the cache can accommodate is 1K/4 = 256 blocks.

The logical address space in a computer system consists of 128 segments. Each segment can
have up to 32 pages of 4K words each. Physical memory consists of 4K blocks of 4K words
each. Formulate the logical and physical address formats.

To formulate the logical and physical address formats, we need to consider the given
information:
 The logical address space consists of 128 segments.
 Each segment can have up to 32 pages of 4K words each.
 Physical memory consists of 4K blocks of 4K words each.
Based on this information, we can formulate the logical and physical address formats as
follows:
Logical Address Format
The logical address format consists of two parts: the segment number and the page number.

 The segment number is represented by 7 bits, allowing for a maximum of 128 segments
(2^7).
 The page number is represented by 5 bits, allowing for a maximum of 32 pages (2^5).
 The word offset is represented by 12 bits, allowing for a maximum of 4K words (2^12).
Physical Address Format
The physical address format consists of three parts: the block number, the word number within
the block, and the word offset within the word.

 by 12 bits, allowing for a maximum of 4K blocks (2^12).

 The word number within the block is represented by 12 bits, allowing for a maximum of
4K words (2^12).
 The word offset within the word is represented by 12 bits, allowing for a maximum of
4K words (2^12).
By using these address formats, the computer system can efficiently map logical addresses to
physical addresses and access the corresponding data in memory.
A computer has a 256 K Byte, 4-way set associative, write-back data cache with a block
size of 32 Bytes. The processor sends 32-bit addresses to the cache controller. Each
cache tag directory entry contains, in addition to the address tag, 2 valid bits, 1
modified bit, and 1 replacement bit. Solve for the number of bits in the tag field of
an address. Explain each step of the calculation.

1. Understand the Cache Structure

Cache Size: 256 KB= 256×1024 =262,144 Bytes
Block Size: 32 Bytes32
Associativity: 4 ways
Address Size: 32 bits

2. Calculate the Number of Cache Blocks

The total number of cache blocks is:

2. Determine the Number of Sets

4. Bits Required for Set Index

The number of sets determines the number of bits needed for the set index. The formula for the
number of bits is:
Set Index Bits= log2(Number of Sets)= log2(2,048)=11 bits.

5. Bits Required for Block Offset

The block offset is determined by the block size. The number of bits required is:

Block Offset Bits = log2(Block Size) = log2(32) = 5 bits.

6. Calculate the Number of Tag Bits

The total address size is 32 bits. The remaining bits after accounting for the set index and
block offset are used for the tag field:
Tag Bits=Total Address Bits− (Set Index Bits + Block Offset Bits)
Tag Bits=32−(11+5) =16 bits.

Final Answer
The number of bits in the tag field is 16 bits.
There is an instruction pipeline with four stages. The stage delays for each stage is 5 nsec,
6 nsec, 11 nsec, and 8 nsec respectively. Consider the delay of an inter-stage register in
the pipeline is 1 nsec. Determine the approximate speedup of the pipeline in the steady
state under ideal conditions as compared to the corresponding non-pipelined
implementation.

Given Data:
1. Pipeline stages: 4
2. Stage delays: 5 nsec,6 nsec,11 nsec,8 nsec
3. Inter-stage register delay: 1 nsec

1. Time for Non-Pipelined Execution

The non-pipelined execution time for each instruction is the sum of the delays of all stages:

Non-Pipelined Time per Instruction=5+6+11+8=30 nsec

2. Time for Pipelined Execution

In a pipelined system, the slowest stage determines the clock cycle time.
The slowest stage delay is 11 nsec
Clock Cycle Time = Slowest Stage Delay + Inter-Stage Register Delay =11+1=12 nsec

The pipeline completes one instruction every clock cycle after the pipeline is filled.

3. Pipeline Speedup
Speedup is defined as
Given Data:

 M1 (Cache):

o Size: 16 K words

o Access Time: 50 ns

 M2 (Main Memory):

o Size: 1 M words

o Access Time: 400 ns

 Block Size: 8 words

 Set Size: 256 words

 Mapping: Set associative

 Cache Hit Ratio: 0.95

(i) Mapping Between M2 and M1

In a set-associative cache:

 Each block of main memory is mapped to one specific set in the cache, but within the set, it can
be stored in any way (associativity).

Step 1: Number of Cache Blocks

The total number of blocks in cache is:

Step 2: Number of Sets

Step 3: Mapping

 Main memory is divided into blocks of 8 words each.

 Each block maps to a specific set using the set index:

Set Index= (Block Number) mod (Number of Sets).

For example:

 Block 0, Block 8, Block 16, etc., will map to Set 0.

 Block 1, Block 9, Block 17, etc., will map to Set 1.

(ii) Effective Memory Access Time (EMAT)

 We need to solve the following for a system with:

 Memory Size: 64 K×16=1,048,576 words

 Cache Size: 1 K words=1024 words

 Block Size: 4 words

 Mapping: Direct Mapping.

(i) How many bits are there in the tag, block, and word fields?

Step 1: Address Breakdown

The address for accessing memory can be divided into:

1. Word Field: Identifies a word within a block.

2. Block Field: Identifies the block within the cache.

3. Tag Field: Uniquely identifies a block in memory that maps to the same cache block.

Step 2: Word Field

Each block contains 4words. The number of bits required to address a word within a block is: