EDC Project Report
EDC Project Report
Semester Project
Audio Amplifier with Variable Gain
Name Roll No.
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Table of Contents
Introduction: .................................................................................................................................... 3
Designed Circuit: ............................................................................................................................ 3
Explanation of a designed circuit: ........................................................................................... 4
Calculations: .............................................................................................................................. 5
Simulation of designed circuit: ....................................................................................................... 7
Software: .................................................................................................................................... 7
Components: .............................................................................................................................. 7
Procedure for simulation of designed circuit: ........................................................................ 7
Frequency gain: ..................................................................................................................... 8
Designed circuit: ........................................................................................................................ 8
Output waveform: ..................................................................................................................... 9
Hardware of the designed circuit: ................................................................................................. 11
Components for circuit:.......................................................................................................... 11
Procedure of implementing the circuit: ................................................................................ 11
Designed hardware circuit: .................................................................................................... 12
Analysis of the designed circuit: ................................................................................................... 12
Limitations of the designed circuit: .............................................................................................. 13
Conclusion: ................................................................................................................................... 13
Table of figures:
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Introduction:
Designed Circuit:
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Explanation of a designed circuit:
The two BJT topologies was used in this design . Common emitter
topology was used because the gain of this topology is higher than other
as its gain is;
𝐴𝑣 = −𝑔𝑚 𝑅𝑐
We have to design the audio amplifier with variable gain , thus we used
two types of transistors, different type of resistors , assumed values of the
capacitors and 1 DC source of 12V and one audio signal from the phone
or etc. the design was basically depend upon the gain of the circuit . thus
we have used the two stage amplification for the amplification for higher
gain. One darlington pair was used in the designed circuit for higher
amplification. Thus the speaker was of 8ohm . when we attach the speaker
in first stage it does’nt give the gain as much required thus we have used
the second stage for amplification. We have used the potentio meter as
variable resistor for the variable gain on the 𝑹𝒄 of the first transistor.
As it was audio signal thus it depends upon the frequency response of the
circuit, thus frequency of the circuit can be controlled by using
capacitors.the resistors values has been calculated . Bypass capaciotors
And coupling capacitors was used in the circuit. The hardware and
software design is explained below.
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Calculations:
Let suppose,
𝑉
Gain = 𝐴𝑣 = -175
𝑉
𝑨𝒗 = - 𝐠 𝐦 𝑹𝒄
put value of gain,
-175 = - g m R c
As,
𝑰𝑪
𝐠𝐦 =
𝑽𝑻
𝑰𝑪 𝑹𝒄
175 =
𝑽𝑻
𝑽𝑻 = 26mV
(175)(26mV)= 𝑰𝑪 𝑹𝒄
4.55V = 𝑰𝑪 𝑹𝒄
Let,
𝑰𝑪 = mA
4.55
𝑅𝑐 =
10−3
𝑹𝒄 =4550 Ω
𝑽𝒄𝒄 = 12V
𝑽𝒄 = 𝑽𝒄𝒄 - 𝑰𝑪 𝑹𝒄
𝑉𝑐 = 12 – 4.55
𝑉𝑐 = 7.45V
𝑽𝑹𝑬 ≈ 𝑰𝑪 𝑹𝑬
𝑽
𝑹𝑬 = 𝑹𝑬⁄𝑰
𝑪
As given 𝐼𝐶 = 1𝑚𝐴
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𝑅𝐸 = 1.2⁄ −3 =1200Ω
10
𝑅𝐸 = 1200Ω
𝑰𝑪
𝑽𝑩𝑬 = 𝑽𝑻 𝒍𝒏 ⁄𝑰
𝑺
𝑉𝑇 = 26𝑚𝑉
−3
10−3
𝑉𝐵𝐸 = 26𝑥10 ln[ ]
1.434𝑥10−14
𝑉𝐵𝐸 = 0.64916𝑉
𝑅1 (0.154097) = 𝑅2 (1-0.154097)
𝑅1 (0.154097) = 𝑅2 0.84590
0.84590
𝑅1 = 𝑅
0.154097 2
𝑅1 = 5.48939𝑅2
Let, 𝑅2 = 10𝑘Ω
𝑅1 = 54893.9Ω
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Simulation of designed circuit:
Software:
CIS (pspice) is the software used for the simulation of the designed circuit.
Components:
In the simulation of design of audio amplifier with variable gain, we have perform
it on the CIS(pspice) . in this simulation we have first selected all the components
of the circuit from the place part as according to the designed circuit. Then we
connected all the parts through wires. The we add the voltage the probe to the input
and output. Then we simulate the graph in time domain and AC sweep analysis .
In time domain analysis , we have set the run to time (10ms) and maximaum step
size was 0.1ms then we simulate graph as the below fig.(time domain analysis)
shows the output waveform of the time domain analysis.
In AC domain analysis was frequency bases because the audio signal is basically
depend upon the frequency. Thus in simulation we have set the simulation
properties as start frequency (0.1Hz) and end frequency (1GHz) with decade 10.
Then we simulate the graph and the fig (AC domain analysis) shows the output
waveform of the designed circuit.
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Frequency gain:
Midband Gain:84.96V/V
Lower cut of frequency= 900Hz
Higher cut off frequency= 80MHz
Designed circuit:
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Output waveform:
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AC sweep analysis:
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Hardware of the designed circuit:
In the whole designing process, firstly we have placed all the required
components that we needed in order to complete the desired circuit.
Firstly, we have tested the all transistors, capacitors and the resistor with
DMM, in order to check whether the components are working properly or not.
All components was selected according to the designed circuit. This is a good
practice to check components before implementing the circuit as it doesn’t
create problems after the completion of circuit and also there’s less chances of
errors in the circuit.
According to the designed circuit, we have placed the four diodes on the
breadboard in such a way that one diode is antiparallel with its respective one.
Then we place taken three resistors.
According to the design procedure, we place the all components on
breadboard. There is some changing in the hardware as we have used the
higher power resistor of 5k parallel to the speaker because due to high power
the resistor burn. And also we have taken the high power transistors for
Darlington pair because it was burning in 2 mints due to high power. The 12V
DC source through power supply is given to the circuit as according to the
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circuit. An audio signal through phone is given to the circuit and for the
variable gain a potentio meter of 5K was used in the circuit. By changing the
value of the potentio meter we can change the gain of the circuit,Thus the
whole circuit is connected through the wires, when we connect all the
components according to the designed circuit the output obtained from the
speaker attached to the circuit instead of 8ohm resistor.
In this designed circuit of audio amplifier, we have analyze that we can use AC
source in the simulation instead of the audio signal with value of specific
frequency but in hardware we can give the audio signal. The high power
resistor and transistor is used in the hardware circuit but these have no effect in
simulation it is working according to the designed circuit.
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Limitations of the designed circuit:
The limitation of the circuit was it we want the lower cut-off frequency at
20Hz and higher cut off frequency at 20kHz and we did’nt achieve it due to
the values of capacitors.
As we have noise in the output of the hardware circuit that is due to the
connections of the the components of the circuits but this noise can be
removed by using filters.
The gain which is obtained from the circuit is very low we can obtain higher
gain by using different topologies.
Conclusion:
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