86

✗
Family ☆ the contents of the code segment ④ Instruction

pointer registers a re
generally summed
up
The 16 bit Processors in order to of the
get the address instruction
-

80-86 8028£
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8086 Buses
Address lines Address Hines
-

20
•
24

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z
- 16 MA
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2.5 MIPS ◦ 4 MIPS
( million ist perky Aig bus

(I n intel family ,
size of
resist reflect size of up ) Do

8086 Dis Data

bus
the 32 -

bit processors

]
→ MEMR
80486 control MEMW
80381
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signals
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Internal cache Memory Address Space

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coprocessor)
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50 MIPS had
poor
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outside
Alq - - - - - -
Ao

0 O -
✗ 86 00000h
of family
- - - - -

Characterists the
↓
1 I - FFF Ff
CISC n
- - - - -

-
Instructions -
broken up into
Mops (Micro operations )

#
0000h
-

Complex Instruction Decoder

8086 -

Programmer's Model
memos
Adam
space
} →
i.
:

pffffn
|
Architecture of 8086 resist
an
" ☆ Fetches Instruction - BIV

L %÷
☆ Executes Instruction Eu
part
→

regions ~

BIU
of
men
Code
*Ñ addrefat.tn
segment
get
segmwe.fm

g g
bits
part
resisters ushers
EU
of terror
of
on
register gouge
to
kind of result obtained
indicating
ALU
f) n o m
I
 ☆ It has program
8088
Variation of 8086 ( )
-

set of instructions
most 1=10 devices
Code Segment
☆ External Data Bus -
8 bits [ Because *
-

⑨ ⁿʰ% W"
☆ Data available in
☆ Instruction Queue 4 bytes
organised ]
-

Data segment it
-

☆ Extra storage of data

Extra segment like in string @ away

8086 -

80486 Programmer 's Model of data

☆kki
stack Segment
☆ fetches Instruction → B IU operations in subroutines

☆ Executes Instruction → Eu
☆ FS ② GS are multipurpose
Memory Addressing ☆ It
may be
possible that
only CS and DS

t wo modes of operation : are present physically

① Real -
Access only IMB of
memory
☆
Segments might oreralapp physically .

Only to Address Lines Regained ☆ ANY segments in a

single area .( orerelappof all)

② Protected
☆ There can also be segments with some set

of memory not used (gaps )

wewillbelookiyatrealmodefamow.ge only
IP with CS
* ☆ combines .

Programmer's Model -

BIV E CS = 2000
µ Base address Csegmatadderss
IP address
p◦iM→i 3000h Offset
=

IP
Extended 16
bit

wo n EIP Mn IP → Another
register ʰ°°°#"ˢ°°°→ CS
Fit

,,,µµ,,µ µ
Cs Code segment

]
of them
-
a re

sent (all #
ret
DS
16 bit
-

Data -

Es -

Extra -

resists ] SS

,
SS -
stack _

MM f- S MM -
F segment
am as mm -
a segment while you code
segment is going to start

wrt Stan
Wwe this particular instruction is present adams
( 0000N )

☆ In Real mode , only IP considered ( FS.GS

considered
in real trash) physical address

=
20000h +
☆ CS ② IP combined to make 20 bit

address

of intel
.
We do this because

to be
memory

segmented
z}%°÷→ Instruction

location
from this

processors a re
going .

memory is fetched
by BIU

CS IP Zoff
E① 2100
: :

Zoff F
=) 21000 1- =
23 of

② : 5200 IP zfff
(S
:

=) 52000 +
ZFFF = SYFFF
 58Fffn
③ f- Fff IP : 0000 ,
(S :

Extra
FO FFFFO €5
f- f- f-
=
+0000
yq ◦ ◦ on
←

pygmy
☆ When reset @ start MP CS 43ffFn
you your by
Stack
,

value ffff
default will hone
swoon -3000 SS
oz z y
☆ first address generated by Mp . Instruction at zffffn

by Code
f- FFFO is first instruction executed any < ◦ ◦ ◦
on
←2 Cs

Intel lffffn
member
of Up Data
← ⑤ DS
10000h
2000 → ← ⑤ ggg
Base valve
00000h
at
points ">
do c-
( Wwe it is going
begin
sort gg present wit

te -0000 ) ☆ 8086 Real Mode (No protected Mode )

wwete is
works
only in

( segment 216
µÑ FF⑤ Every segment size of
bits
☆ can have maximum
c-

=
64 KB

Advantages of segmentation
☆ Relocation High Memory

→ we
specify only offset ☆ When 05 loads
,
NIMEM.SN is also loaded

have at location
for example
→
,
we a
program ☆ It enables on e m o re address line in Real mode : Azo

f- 0000h .

☆ this allows ZMB of memory

→
hift this program to another Mp .

FF
☆
f Segment Address -
FF n

foooon another
Different
at at
→ segment Mp .
Offset Address
-

4000h
for another Up might
be
CS
10000h
→ since we have offsets ,
we can use some
_
103 Ffon ( IMB )

Ffon ( IMB ) ( If
program ( same offset )
03 NIMEM - Sts is not

loaded )
resisters
needs to change from f- 000ns
→ Only segment,

1000N
Programmer's Model -
F- U ( 16 -

bit Mp )

÷:*
}
Example Segment Addresses
Base Index (@ resists
Starting Ending Count
Segment
Adam Address Data 16 bits
register

]
"

20000h 2 FF FF
2000h n

200in 20010h 300 of -

DI
-

!
Source Index

na ,
Registers

3 Off f- n
21 ◦
◦
On
2100m

ABO on AB 000h BAFFF n ☆ Accumulator _

Generally stores an
operand duris
A- ②L

stores )
Operation ( Not
always
1234h 12340h 2233 Fn
☆ Base Index -

It holds pointer value whenever

you
want to do data transfer
Base value
TIE
-

Address in two pants -

_
in Ds Rey
could be
Pointer value
( Also which
)
store
preset
in B. ✗ resister -
operands
☆ Count -

Used in loops ⑨ strings / of bytes) Default 16 bit segment and offset address combinations

☆ Stack Pointer -

Offset for stack segment

☆ Base Pointer
-

① Either with Data segment @ segment offset special purpose

stack segment '

Cs Ip Instruction
Address
data
② Also used to hold

SS sP(a) BP stack Address

temporary
☆ Source Index Pointer register associated with DS B- ×
DI.SI Address
Data
( you can also
-

number
an 8-bit directly give
⑧ Destination either DS @ f- 5 16 -

bit number
offset )
F- S DI for string string destination
Instructions address

☆ These registers can be used for temporary

storage of data .

F- FLAGS FLAGS

/\
Multipurpose Registers status control
flees flag
AX BX CX , DX BP DI SI ( storing operands for
controlling
, , , ,

( gives he status ( used •

values
)
,

@ pointer the result ) certain functions )

of
✗ 86 processor
in BIO
resisters
accessible
special Purpose ones as pointer Mister
→ and

FLAGS
SP
( IP Flog register
Instruction
IP
, , only for programmer 's Model : Eu -

and not
SS f- S
Point for CS
CS , DS
, ,

any
other purpose )
( Segment Registers ) to add IP
( can't say Flags : Two
types
with BX )
Coutts
kind of
☆
Status : indicates the result we obtain

as a result of A ② L operation .

16 bit Perish
AX An AL AY ☆ o : used
for controlling certain operations
bit ) ( 8 bit) be broken
of
can
meany the
bit
Mp .

into 2 8

Bn BL
BX registers
flag Register
( Bae Resist)

*
111111 11111¥47 171*144*44 # Hk
ex en et
sp.BP.SI/Di-
( Used as
a county cannot be broken

up into 8 bit
DX Dn DL Ba -
Available 8086 onwards

[ Used to
• Available 80286 Onwards
date
-

to
point 80386 onwards
i n -40 operations) § -

Available
B- Available 80486

underlined States flags

Model ( for 80386,80486 )
-

's MPR
Programmer
-

others . -
Control flags
so
A- ✗ becomes EA× and on
not used
☆ the ones with no bit indication are _

in Real
EAX An Al ( Een a 32
we a re not
supposed to change these bits @ ac tors

mode ,

F- BX BN BL
can
perform them .

operations)
bit 8086
F- ( ✗ Ch
ch
status flags after :

F- DX Dh DL g, g ;+
doing Arithmetic operation
①
can
flag
when you
F- BP BP Carry : ,

addition
f- SI SI
get carry a .

This flag indicate

F- DI resulted Cams @
@ substation
DE in

F- SP SP is 1 else °
If carry bit .

borrow
reset
,

⑨
.
 the Is the control flags after 8086 :

② Parity Flag : It
gives no .

of present in

result .

If no .

of 1s is e ve n
, parity is
① trap flag
:
It'll cause the
processor to have after
parity ) for
be used
( Else It
set for odd instruction can
I @ eve n .
, every .

If set (1) then it 'll hanlt

debugging
( odd parity )
.

parity is reset D @ instruction

.

after every .

to enable
③ Auxiliary carry ! It is similar to
Carry flag .

② Interrupt flag :
It is used
@
I t indicates interrupt If set interrupts
-

whether you had a

carny disable .

when you were adding data Nibble by anenenablld and

viceversa .

Nibble If stop sequential flow

to we can
.
☆ we want ,

call subprograms
E Ofn
.

to In =
Ion

☆ OR an interrupt can be raised to the Mp .

F and in lower nibble

,
when
adding I
carry
Interrupt c a n be raised to the Mp
.

set (1)
.

Aux Carry to be indicates intend

It causes .

external signal @ internal error @

added lower nibble
q
you
had a carry when you instruction that caused interrupt .

of data .
( only makes sense in 8 bit

operations ) It stops up
whatever it is doing currently
☆
address called
and branching to different
will its in BCD operations address )
"
use
we see
n

Interrupt service routine address ( ISR

( resumes execution from ISR )

④ Zero flag :
If result is
zero , flag is set (1) .

with string operations

③ It used
flag is
.

:
Direction
A ⑧ cops)
Else , red (D) .
( used win

☆ whenever we talk of string @ Array of data ,

reflects Do
⑤ Sign flag :
It the MSB of data ¥ In Dis can
parse this string from firsttolast_
-

you
- -
-

is MSB
Condition of Dis is condition of ig-bby.RS .

orvicerersa .

1
E: 8000 ( Afth A operation ) Dis bit is ☆ Direction blog determines direction of parsing .

µ
,
,

sign flag is '

☆ If set ,
born last± .

7 Fffin ( -7 D bit is °
'
, later
①
,

Output Privilege Level

, : understand in

sign flag is o Input

☆ all data mode of operation
Mp looks ism sign -
magnitude fan . protected
is
☆ Tf sign flag is 1 ,
it negative according to µ

☆ ③ Nested Tasking : Sense in

Multitasking environment
-
0
,
-

positive _

⑧ in
protected mode of operation .

indicate 's
⑥ whether
used to 2
Overflow flag : It is

occurred
④ Resume :
It is used with
debugging operations .

Complement overflow
has .

end with whether

☆ Once you debugging ,

the processor should from previous

EI .
7 Fn t 01h =
80h resume

¥
address @ whether it should be reseated

¥ ¥ ( b/c NSB is 1 in
and started all over is indicated by it
result ) again .

1 's arithmetic
Cannot be supported in complement will from whatever
.

☆ If Sef ,
it resume

so , overflow flag is set in Such case .

address the
processor stopped after debugging .

① Virtual Mode :
If set ,
80386 behaves exactly as

① Alignment Check : used to indicate whether the 4-

byte 8086 .
It is called virtual 86 mode

of operation
bounding is maimed by the
Mp
.

whence

tenses net
it is storing
.

E First 32 bit is from 00 to 03 ( 00,0 1,0-2,03 ) .

Next born 04

boundary is maintained
If It ,
tnen .
 80×86 Summary
-

BIV ( Bus Interface Unit )

provides hardware funcns for generation of the memory

and I/O addresses for the transfer of data b/w

itself and the outside world .

Unit )
f- U ( Execution

receives instruction codes and data from

program
the BIU executes these instructions and stores the
,

general purpose resisters @ ( memory

in
results in -

too )