Module: CMOS VLSI and aspect of ASIC design.

1. Polysilicon is used to make transistor

a. Source
b. Gate
c. Drain
d. substrate

2. In a simple nMOS transistor model, the region where Ids (drain-source current) is
almost constant
a. Saturation
b. Cutoff
c. Linear
d. None of above

3. Threshold voltage is a function of

a. Gate insulation material
b. Gate material
c. Voltage between source and substrate
d. All of the above

4. In an Enhancement mode transistor

a. Conductive channel is present at zero gate bias
b. Symbol represents a dark channel between source and drain
c. No conductive channel at zero gate bias
d. None of the above

5. Design Rule Check (DRC) on layout

a. Checks if layout matches with original schematics
b. Perform technology related checks on layers
c. Checks if maximum power is consumed by a circuit
d. None of the above

6. In a n-well process
 a. P-type transistor is created on a substrate
b. N-type transistor is created in n-well
c. P-type transistor is created in n-well
d. None of the above

7. Find the correct equation for the given Circuit?

a. Z = (( A’+ C’ ) + D’ ) + B’
b. Z = (( A+ B’ ).* D’ ) + C’
c. Z = ((A’ +B’ ) * C’ ) + D’
d. None of the above

8. Logic ‘0’ and logic ‘1’ , both are passed in an acceptable fashion by
a. nmos pass transistor
b. Poly gate
c. Transmission gate
d. All of the above
9. In the IC fabrication process, sio2 is used as transistor
 a. Source
b. Gate
c. Drain
d. None of the above

10. Memory cell that stores the content as charge on a capacitor

a. SRAM
b. ROM
c. DRAM
d. All of the above

11. In the ASIC design flow, breaking a large system into sub-system or modules
a. Floor planning
b. Partitioning
c. Placement
d. None of the above

12. In CMOS NAND gate, n-type transistors are connected in

A. Parallel
B. Series
C. Cascade
D. Random

13. SPICE control statement

a. .tran 20ps 1ns
b. C1 out gnd 100F
c. * control stepper
d. None of the above

14. Wiring within the chip refers to

a. Global routing
b. Detailed routing
c. Special routing (power & clock)
d. All of the above
15. Clock buffer insertion allows
a. Equalizing delay to leaf nodes
b. Smooth routing of power nets
c. Minimize area within core module
d. All of the above

16. Which CMOS memory cell of the following is made of the least number of
transistors
a. SRAM
b. DRAM
c. Both options ‘a’ and ‘b’
d. None of the above

17. In CMOS circuits, which type of power dissipation occurs due to subthreshold,
gate, and junction leakage current ?
A. Static dissipation
B. Dynamic dissipation
C. Both a and b
D. None of the above

18. Latch-up in CMOS can be reduced by introducing

A. SOI process
B. Guard rings
C. Both a and b
D. None of the above

19. Transistor with improved gate structure that provides better control of current
by placing gate at multiple sides of the channel
A. PolyFET
B. FinFET
C. MEM-FET
D. None of the above
20. Contacts and vias have resistance. In order to reduce resistance in the layout
 a. Use single large contact
b. Use multiple small contacts
c. Use contacts made from insulator
d. None of the above

21. Which of the following step takes input from detailed placemt ?

A. Initial Synthesis
B. Initial floorplan
C. Routing
D. None of the above

22. Typical size of a wafer (diameter) used these days

a. 300 mm (12 inch)
b. 900 mm (36 inch)
c. 1200 mm (48 inch)
d. None of the above

23. To drive large loads (off-chip)

a. Pad memory is used
b. Pad multiplexers are used
c. Pad drivers are used
d. None of the above

24. In modern VLSI processes, wires are very close to each other. When one wire
switches, it affect its neighbor through capacitive coupling; this effect is called
a. Crosstalk
b. Noise margin
c. Metal migration
d. None of the above

25. BIST refers to

a. Built-In Self Test
b. Binary Inserted Self Test
c. Bit Inserted Self Test
 d. None of the above

26. Design For Testability (DFT) refers to designing circuits that are testable
a. One of the important approach for DFT is scan based
b. Ability to set and reset every node of circuit and ability to read state of
any node are the key feature of DFT
c. DFT provides high fault coverage with few test vectors
d. All of the above

27. Antenna effect refers to

a. Migration of metal ions from one place to other
b. Addition of delay due to multiple metal layers
c. Addition of power due to increased frequency
d. None of the above

28. Standard exchange format for Layout description

a. SDK
b. PICO
c. EDIF
d. None of the above

29. In a layout design of a cell, typically

a. Poly runs vertical and diffusion runs horizontal
b. Poly runs vertical and diffusion runs vertical
c. Poly runs horizontal and diffusion runs horizontal
d. None of the above

30. ASIC type for which all logic cells are predesigned and none of the mask
layers are customized
a. Standard cell based ASICs
b. Full custom ASICs
c. Field Programmable Gate Arrays
d. None of the above
31. Parasitic extraction program when run for a layout, collects information related
to
a. C and R values
b. Heat flow
c. Surface inversion
d. None of the above

32. The last statement of a SPICE deck must be

a. LAST
b. ,LAST
c. END
d. None of the above

33. While drawing a complex layout, higher level metal layers are used for
a. Power and Ground routing
b. Signal routing
c. only clock routing
d. None of the above

34. Static Timing Analysis (STA) is one of the technique to verify the timings of a
digital design
a. It is static as the analysis of the design is carried out statically and does
not depend upon the data values being applied at the input pins of the
design
b. It is complete and exhaustive verification of all the timing checks of a
design
c. It is faster and simpler way of checking and analyzing all timing paths
in the design for any timing violations
d. All of the above

35. CMOS Inverter with equal W for both pmos and nmos as well as equal L.for
both nmos and pmos will have
A. More resistance of n channel than p channel
 B. More resistance of p channel than n channel
C. Equal resistance of n channel and p channel
D. All of the above

36. When condition is off for pull-down (nMOS) and on for pull-up (pMOS)
transistors of CMOS logic design, what will be the output:

A. 0 or ground or LOW state

B. High impedance or floating(Z)
C. 1 or Vdd or HIGH state
D. None of the mentioned

37. Typical number of wiring levels available these days

A. 100
B. 15
C. 150
D. All of the above

38. Layout design rule that popular in foundries these days

a. Scalable rules (Lambda based)
b. Micron rules
c. Exponential rules
d. all of the above

39. Diffusion has both high capacitance and high resistance, it is generally made
A. As small as possible in the layout
B. As large as possible in the layout
C. As oxidation layer
D. None of the above

40. In a layout, a transistor is formed when

A. Diffusion crosses metal
B. Metal crosses diffusion
C. Poly crosses diffusion
D. All of the above

AnswerKey

1. B
2. A
3. D
4. C
5. B
6. C
7. C
8. C
9. D
10. C
11. B
12. B
13. A
14. D
15. A
16. B
17. A
18. C
19. B
20. B
21. C
22. A
23. C
24. A
25. A
26. D
27. D
28. C
29. B
30. C
31. A
32. C
33. A
34. D
35. B
36. C
37. B
38. B
39. A
40. C