1.

without sensitivity list, always block is an infinite loop

2. without sensitivity list, tool will show warning and there will be a simulation synthesis
mismatch
3. With missing 'else', unintentional latches will be formed
4. It is recommended not to use nested if-else because it infers a priority logic with cascaded
stages. You can use nested if-else if you want to design a priority based logic.
5. Nested if-else infers priority logic whereas case statement infers parallel logic
6. Unary operators have highest precedence in verilog, followed by arithmetic operators and
relational operators.
7. Equality operators have lower precedence compared to relational operators
8. For logical equality and logical inequality, if either of operand is x or z, the result will be x
9. Flip flop is 2 latches cascaded together
10. Gate is level sensitive and not edge triggered
11. Blocking assignment are not used for sequential ckts because it will infer only 1 flip flop
when the intention of the designer was to make different FFs for different functionalities
12. $display executes only once and it will display the values at the instance it is placed
13. $monitor is used to automatically print out variables or expression values, whenever a
expression argument list changes.
14. $write is also used to display the argument values but will not append new line character
15. 'timescale (time unit)/(time precision) = 'timescale 1ns/1ps
16. Study reset recovery time and reset removal time (mujhe bhi pata nahi ye kya hai, padhne
ke baat batati hun)
17. Types of code coverage- statement, branch, toggle, expression, fsm coverage
18. Loops in verilog - for, while, repeat and forever
19. Forever loop is the only loop that does not run for a particular condition time. Forever loop is
like a infinite loop
20. Begin - end executes in a sequential manner whereas fork-join executes in a concurrent
manner
21. Delay assignments - Inter delay and intra delay
22. Inter delay- LHS of assignment [#5 y= (a & b | c) ]
23. Intra delay - RHS of assignment [y = #5 (a & b | c) ]
24. Delay modeling - distributed delay, lumped delay, pin to pin delay (path delay)
25. Distributed delay - delay of each component or gate placed in a circuit path.
26. Lumped delay - Overall/ cumulative delay of a module. Usually specified as a single delay
value on output gate
27. Pin to pin (path delay)- here delays are assigned individually to paths from each ip to the op.
28. Setup time tsu- minimum amount of time for which data ip should be stable before arrival of
active edge of clock
29. Hold time th- minimum amount of time for which data should be stable after arrival of the
active edge of clock.
30. Clock to q delay or propagation delay of ff- amount of time required for the FF to get an op
after active edge of clock .
31. Setup slack = Required time - Arrival time
32. Specify block can be used to give various delays. Specparam is used to specify various
delays or timing parameters.
33. Most of the times the pin to pin delay may change depending on the state of signals and
these delays can be assigned conditionally, based on the value of the signals in the ckt. Hence
they are called STATE DEPENDENT PATH DELAYS or SDPD.
34. $setup (d_in, posedge clk, tsu)
35. $hold (posedge clk, d_in, th)
36. Note - positive clock skew is better for circuits
37. $setuphold (ref event, data event, tsu, th)
(posedge clk, d_in, tsu, th)
38. $width (posedge d_in, tw) checks the width of the data signal
39. $nochange (posedge clk, d_in, start edge offset, end edge offset).... This checks whether
data is stable in the interval of start edge of state and end edge of state. If data is not stable
then it reports timing violation
40. $period (posedge clk, tperiod)... Used to check the period of signal is sufficiently long or not.
41. $recovery (posedge clk, d_in, trecovery)... Timing violation occurs if time interval between
edge triggered reference event and data event exceeds the limit.
42. $skew (posedge clk1, posedge clk2, tskew)... Used to check maximum permissible skew
limit with two different clocks. If different clocks are used in a design and are synchronised then
$skew is used to report timing violation.
43. Funtions - cannot contain any time control statements using #,@, posedge, negedge, wait.
Functions cannot have any nba assignments. Functions should have at least one input
argument. But it cannot have inout or output arguments. Functions cannot call a task but can
call other functions. Functions have a return type, generally void.
44. Tasks- Tasks can consist of time controlling statements and delays. It can have zero or more
arguments of any type. Task allows input, output and inout ports. Using task we can call another
task or function. Task do not have a return type.
45. Global task - a task that is declared outside all modules are called global tasks and they can
be called within any module as they have global scope
46. Static task - need to be declared inside a module.
47. Automatic task - it is re entered
48. Fsm with data paths (FSMD) - in practical scenarios , in any design we should have clean
data path which should be controlled by using some control logic. In such cases we need to
develop fsm control unit to enable the data path or provide timing signals to the data path . Here
we use FSMDs
49. Generate block - cannot consist of ports, parameters , specparam or specify blocks but
module instances and generate blocks are allowed.
50. Generate block is used for multiple instantiations of a module and are of three types-
generate for , generate if and generate case.
51. Conditional compilation - it can be achieved using `ifdef. This compiler directive
communicates to the compiler that include a piece of code until the next `else or `endif. If a
given macro called by some name, is defined using `define directive, this allows conditional
compilation. (Confuse na ho isiliye easy words mein batati hun, ifdef tab use karte hai jab koi
ip/op port add karna ho ek existing code mein. Like suppose full adder banana hai and mere
pass half adder ka code pada hua hai to main full adder banane ke liye half adder ke ports ko
ifdef karke include kar dungi so that 2 hald adder milke ek full adder ban jaye)
52. And `ifndef tab use karte hai jab ek existing code mein se mujhe koi ip/op port exclude karna
ho nikalna ho.. okay baby?
53. UDP (user defined primitives) - UDPs are used to model combinational and sequential ckts.
UDPs are written under primitive.. endprimitive
54. UDPs can have multiple inputs but only one output port. Inouts are not allowed. All port
signals must be of scalar type (1 bit wide)
55. UDPs are written in table.. endtable under primitive.. endprimitive
56. UDPs can have exactly one output which can be 0,1 or X but never Z. Z is not supported by
UDP. Any input value z will be treated as x.
57. We can also use ? Along with 0,1 and x in table.. endtable, but only for inputs. Because
output can only be 0,1 and ?
58. UDPs are non synthesizable
59. For sequential UDP, op should be of reg type.
60. In sequential UDP , we can use minus (-) for no change operation in the output side but
never on the input side
61. * Or ?? In sequential UDP indicates that for any change in input, output will be no change
62. Memory is a storage element and we can have various memories like SDR, DDR, HBM
(high bandwidth memory) but mainly semiconductor memories are of RAM and ROM type.
63. Switch level modeling - using switch level primitives we can have switch level modeling
64. Nmos and pmos in switch level modeling are represented as - nmos u1 (y_out, vss, a_in).....
pmos u1 (y_out, vdd, a_in)
With supply1 vdd
supply0 vss
65. Programming language interface (PLI)- it is used to provide the set of interface routines to
read and write to internal data representations. Pli interacts and extracts information about the
simulation environment. So this needs the used defined system tasks and functions with pli
routines.
66. 3 generations of pli - 1. Task/functions (tf_), 2. Access (access_ or acc_), 3. Verilog
procedural interface (VPI)
67. PLI interface allows to - 1. Read internal data structures, 2. Modify internal data structures,
3. Access simulation environment
68. Application of pli - used to define additional system tasks and functions, extraction of design
information such as hierarchy, connectivity fanout, logic elements etc , used to write the output
display routines , useful to have the routines that are used to provide stimulus
69. system task in pli - $verilog_design_verification
70. C routine in pli- verilog_design_verification
71. Pli library routine - io_printf
72. At the end of linking of pli tasks, the binary executable file is created which includes the new
$verilog_design_verification that is "hverilog"
73. Pli library routines - A. Access routine (used to provide the access to internal data
representation and used to extract information of the design), B. Utility routine (used to pass the
information across the verilog/programming language boundary)
74. $strobe will print the updated values at the end of simulation
75. Race condition - if same variable is assigned in 2 different procedural blocks in the
testbench, then we will have race condition.
76. Deterministic race condition - consider a clock generator where we can determine actual
clock generation, although clock is assigned in 2 different procedural blocks.....
always #5 clk = clk;
Initial
begin
Clk = 0;
end

77. Non deterministic race condition - consider "a" is a 4 bit reg variable, assigned in two
different procedural blocks...
always @(posedge clk)
a_in = 4'b0000;
always @(posedge clk)
a_in = 4' b1001;

78. "#" "defparam" are used to overwrite dut parameters in testbench instantiations.