word code.

e has
rror occurredineach
thatatmost a single
ii)1110110iv)0011011
i)1001001i) 0111001
code for
Example 10.4.13 : The message below has been coded

a noisy channel.
in Hamming
Decode the message
BCD and

assumingthat
through
transmitted in
occurred each
has been code
atmost a singleerror word.

100011011.
1001001011100111101
the informationcharacter
01101110101
accordingtothe
Example 10.4.14:
Encode 15-bit

Hamming code.

10.5Read Only Memory (ROM)

1,15,
AU : May-03, 05,06,07,08,09,10,1 Dec..-03,06,07,
,08,09,10,15

memory ie.itcan
We can't write data in read only memories. It isnon-volatile hold
ROM is used to storethe binary
data even ifpower isturned off. Generally, codesfor
you want the computer tocarryout and datasuch as lot
the sequence of instructions
does not change.
Thisisbecause thistype of information
up tables.
Itisimportantto note
Bitline Vcc
that although we give
the name RAM to static R

and dynamic read/write

Word line
memory devices, that
does not mean that the
ROMs that we are using
are also not random Open: Data stored (logic
1)
P Close :Datastored (logic
0)
access devices.In fact,
most ROMs are accessed

randomly with unique

Fig.10.5.1
ROM cell
addresses.

The Fig. 10.5.1shows the typicalconfiguration of a ROM cell.Itconsists of a

transistorT and switch P. The transistorT is drivenby the word line. The contents of
cell
can be read from the cellwhen word lineis logic
1.A logicvalue 0 isread ifthe
transistor
is connected to ground through switchP. Ifswitch P
read.The bit lineisconnected through a
is open,a logic
value ls
resistorto the power supply.A sense circuit
a
the end of the bit linegeneratesthe proper output value.Data
when itis manufactured.
is storedinto a ko
There are four types of ROM : Masked ROM, PROM, EPROM and EEPROM
E'PROM. O
 Memory and
(Programmable ProgrammableLogic
Read Only Devices
PROM
051 Memory)
are programmed by
PROMS provide the
To Voo
tacility each Addressselect
line
oTammin8
select
and data line
ddress has its own fused
intersection
or transistor.When
MOSFET
MOSFET
is intact,the
switch
memory
fuse
the

isconfigured
as a logic 1 Dataline
ell fuse isblown
when
and
the memory
circuit), cell
(open
Logical Os are
* logical0. Fuse
selectingthe
by
programmed
selectlineand then Output bit
4ppropriate
driving
the vertical data line
with a high current.
pulse of Fig.10.5.2Single
fused PROM cel
The Fig.10.5.2shows a PROM
fusedMOSFET memory cell.
Fig.10.5.3shows fourbyte PROM. Ithas diodesin
everybitposition;therefore,
the
Outout is initially
allOs. Each diode,however has a fusible
linkinserieswith it.By
addressing bit and applyingpropercurrentpulse
at the correspondingoutput,we can
blow out the fuse,storinglogic
1 at that bit position.The fuse uses materiallike
+Vcc

Fuse link

Ao

2:4
Decoder
A

Output enable
Do D4 D2 Dg D4 Dg D6 D7
Fig.10.5.3Fourbyte PROM
 and Programmable Logic
10-26 Memory Devices
Digital
Principles
& System Design

to pass around 20.

nichrome and polycrystalline. For blowing the fuse itisnecessary
us. The blowing of
fuses accordingto the truth
50 mA of current
for period 5 to 20
with special
tableis calledprogramming of ROM. The user can program PROMs PROM
selectivelyburns the fuses accordingto the
programmer. The PROM programmer PROMs
known as burning of PROM. The
pattern to be stored.This process is also
the informationstored ispermanent.
one time programmable.Once programmed,

Programmable
EPROM (Erasable Read Only Memory)
10.5.2
Erasableprogrammable ROMs use MOS Quartzwindow
They store l's
circuitry. and O's as a packet Ultraviolet
light

of chargein a buried layerof the IC chip.

EPROMs can be programmed by the user
with a specialEPROM programmer. The
importantpoint isthat we can erase the
stored data in the EPROMs by exposing
the chip to ultravioletlightthrough its
quartz window for 15 to 20 minutes, as
Fig.10.5.4
EPROM
shown in the Fig. 10.5.4.
when erased the entireinformationis
Itis not possibleto erase selectiveinformation,
lost. Thechip can be reprogrammed. This memory is ideally suitablefor product
since this chip can be
development, experimentalprojectsand college laboratories,
reused many times,over.

EPROM programming :

When erased each cellin the EPROM contains1.Data is introducedby selectively

programming 0's into the desiredbitlocations. Although only 0's willbe programmed,
both 1'sand 0's can be presented in the data.

During programming address.

and data are appliedto addressand data pinsof the
EPROM. When the address and program pulseisappliedto the program
dataarestable,
input of the EPROM. The program pulse duration is around 50 ms and itsamplitude
depends on EPROM 5.5V to 25 V. In EPROM, it is possibleto
IC. It is typically
at any time - eitherindividually,
program any location sequentially,
or atrandom.

10.5.3
EEPROM (Electrically
ErasableProgrammableRead Only Memory)

erasableprogrammable ROMs alsouse MOS circuitry

Electrically very similarto that
of EPROM. Data isstored as charge or no chargeon an insulated
layeror an insulated
floating
gate in the device. The insulating layerismade very thin(< 200 A).Therefore,d
voltageas low as 20 to 25 V can be used to move chargesacrossthe thinbarrierineither

TECHNICAL PUBLICATIONS An up thrustforknowledge

 10-27
System Design Memory and Programmable Logic Devíces

or erasing.EEPROM allowsselectiveerasingat
forprogramming
the register
all
the informationsincetheinformation
ton than erasing can be
changed by
The EEPROM
memory also has a special
rather signals, chíp erase mode by
electrical can be erased
chip
in
10 ms. This time is quitesmall
as comparedto time
EPROM and it can be erased and
hentire reprogrammed with device rightin
toerase EEPROMs are most expensive and the least
dense ROMs.
However,
ccit.
EPROM
PROM and
Merentiate
PROM EPROM
Parameter
Programmablereadonly memory Erasableprogrammableread only
for memory
Stands

Only once multiple

times
Programmed Absent Present
window
Quartz
Can be erasedby exposingto UV
method
Erazing light.

data
Not possible erasingof data isnot
Selective
Erazing possible.

time Large : 15 to 20 minutes

Eraze
Low High
Cost

Widelyused inmicrocontrollers, Used as static

memory storesinlarge
Application
mobilephones, RadioFrequency They were widelyused as the
circuits.
Identification
cards (RFIDs),
High BIOS chipsincomputer
Definition (HDMI)
Media Interfaces motherboards.
and videogame controllers.

Differentiate EPROM and EEPROM

Parameter EPROM EEPROM

Stands for Electrically
erasableprogrammable
Erasableprogrammable read only
memory. read onlymemory.

ErazingData erasing
Selective of data isnot of data ispossible.
erasing
Selective
possible.

Erazing Can be erasedusingelectrical

signals.
method
Can be erasedby exposingto UV
light.
Erazetimne
Large:15 to 20 minutes Small:10 ms
Speed
Low High
Cost
Low High

TECHNICAL PUBLICATIONS An up thrustforknowledge

 Application Used as staticmemory storesin large EPROMs aresuperseded EEPROM e

They were widelyused as the

circuits. they are cheaper,smallerand faster
BIOS chipsincomputer motherboards

PROM and EEPROM

Differentiate AU: May-15, Marks 2

Parameter PROM EEPROM

Stands for Programmable readonly memory. Electrically

erasableprogrammable
readonly memory.

Programmed Only once times

Multiple

Erazingmethod Selective
erasingof data ispossible.

Erazingdata Not possible Can be erasedusing electrical

signals.

Eraze time Small: 10ms

Application Widely used inmicrocontrollers, Used as staticmemory storesin

mobile phones,RadioFrequency They were widelyused
largecircuits.
cards(RFIDS),
Identification High as the BIOS chipsincomputer
DefinitionMedia Interfaces
(HDMI), motherboards.
and video game controllers.

10.5.4Internal
Logicof ROM

The Fig.10.5.5shows the block diagram of

ROM. It consists of n-input lines and Ao
m-output lines.Each bit combination of the n
A1
Ag 2 xm
input variablesis calledan address.Each bit address m data
lines ROM
combination that comes out of the output lines

An-t
linesiscalleda word.The number of bitsper -Dm

word is equal to the number of output lines,

m. The address specifiedin binarynumber Fig.10.5.5
denotes one of the minterms of n variables.
The number of distinct addressespossiblewith n-inputvariablesis2".An output word
can be selectedby a unique address and sincethere are 2" distinctaddresses in ROM,
there are 2" distinct
words in the ROM. The word available on the outputlinesat any
giventime depends on the address valueapplied to the inputlines.
Let us consider64 X 4 ROM. The ROM consistsof 64 words of 4-bits each. This
means that there are four output linesand particular word from 64 words presently
availableon the output linesisdetermined from the sixinputlines. There are onlysix
inputsin a 64 x 4 ROM because 2 = 64 and with six variables, we carn specify 6t
addresses or minterms.For each address input,thereisa unique selectedword. Thus,if

TECHNICAL PUBLICATIONS- An up
thrust
forknowledge
 10-29 Memory and Programmable LogicDevices
& System Design
Principles
Digial

000000, word number 0 is selectedand appliedto the output lines.

address is
theinput word number 63 is selected and appliedto the output
address is111111,
the
If input
lines.

Ao
1
A
2
Az 6:64
Decoder
Ag

A4

63
A

64 x 4 = 256 Fuses

F
F; F F4

PROM
Logicconstructionof 64x4
10.5.6
Fig.
six input
logicconstructionof a 64 x 4 ROM. The
shows the internal Each
The Fig.10.5.6 gates and 6 inverters.
decoded in 64 linesby means of 64 AND The
variablesare of sixvariables.
one of the minterms of a function
represents
output of the decoder
Address input

A Ao

Mintermns

001

01!
AND 10
matrix! 1

11i

8 Fuses
OR
matrix

D F2

Fig.10.5.7(a)4x2 ROM with AND-OR gates

TECHNICAL PUBLICATIONS"- An up thrustforknowledge

 Digital
Principles
& System Design 10-30 Memory and Programmable LogicDevices

00
01
AND 10
matrix

11

OR
matrix

F1 F2

Fig.10.5.7(b)4x2 ROM with AND-OR-INVERTER gates

64 outputs of the decoder are connected through fuses to each OR gate. Only four of
these fuses are shown in the diagram,but actuallyeach OR gate has 64 inputs and each
inputgoes through fuse that can
a be blown as desired.

The ROM is a two levelimplementationin sum of minterns form. Let us see

AND-OR and AND-OR-INVERTER

implementationof ROM. Fig.10.5.7
shows the 4 x 2 ROM with AND-OR
and
implementations.
AND-OR-INVERTER
I
lo

10.5.4.1
AND Matrix

The Fig. 10.5.8 shows the h

simplified representation of AND

Po
matrix with input buffer.The AND
matrix isused to form productterms.
Before programming, all
fuse links
in
AND matrix are intact and the x indicates
fuse link
product term for each AND gate is
givenby

P = l,
l,-lolJh-n-l Fig.10.5.8Simplified
representation
ofAND matri
with input buffer

TECHNICAL PUBLICATIONS - An up thrust

forknowledge
 Principles System Design
&

Dgta 10-31
Mernory and ProgrammableLogic
Devices
Matrix
105.4.2OR
The
OR matrix is provided to Po P Pm-2 Pm-t

the logicalSum of the

produce
term outputs of the AND
product D
Before programming, allfuse
matrix.
OR matrix are alsointact
linkin and
O

x indicates
the sum termn for each OR gate is fuselink

givenby,
S = Po +Pt...+
Pm-2 tPm-1

TheFig.10.5.9shows the simplifiedFig.10.5.9Simplified

representation
of OR matrix
of OR matrix.
representation

10.5.4.3nvert/ Non-invert
Matrix

Invert/Non-invert matrix providesoutput in the complement or uncomplemented

form.The user can program the output ineithercomplement or uncomplement form as
per designrequirements.The typicalcircuits matrix isas shown in
for invert/non-invert

Inboth the cases iffuseisintactthe output isinitsuncomplemented form;

Fig. 10.5.10
otherwiseoutput isinthe complemented form.

So -SorS So osors

(a) (b)
circuits
and non-inverting
Fig.10.5.10Inverting

Logic Implementation using ROM

10.5.5Combinational
thateach output provides
Looking at the logicdiagram of the ROM, we can realize
We know that any Boolean function
the minterms of n-inputvariables.
the sumn of all
By breakingthe linksof those minterms not
can be expressed insum of minterms form.
the Boolean
includedin the function, each ROM output can be made to represent
the combinational For an n-input.
circuit.
functionof one of the output variablesin
we need a 2"xm ROM.
circuit,
m-output combinational

Examples for Understanding

the following
Using ROM realize
10.5.1 expressions.
Example

F(a,
b, )
c)

Fz(4,b,c) -
=

) m(0,

m (1,
1, 3,5, 7)
2, 5, 6)
 10-32 Memory and Programmable LogicDevices
& System Design
Principles
Digital
= 8 minterms and
generate 2
three inputs.They
Solution: The given functionshave The functions can
be
realized
as
there are two outputs.
sincethere aretwo functions,
shown in Fig. 10.5.11. a b C

Productterms

mo

m.

m
ma

m6

m7

Sum
terms

F,

Fig.10.5.11
shows the block diagramand truthtableof ROM.
The Fig.10.5.12

Ag Aj Ap
0 0
C Ap 0 1 1
8x 2 F1 0 0 1
b A
ROM 0 1 1
Az F2 1 0 0
1 1 1
1 0
1
(a) Blockdiagram
(b)ROM truthtable
Fig.10.5.12

TECHNICAL PUBLICATIONS-An up thrust

forknowledge
 & System Design
10-33 Memory and ProgrammableLogicDevices
PPrinciples
Digtal

10.5.2 Design a combinational using a ROM. The circuitaccepts 3-bitbinary

Example
Excess-3code.
number and generatesitsequivalent

Solution
: Let us
Table 10.5.1
derivethe truthtableforthe given combination circuit.

shows the
truthtable.

Inputs Outputs

B2 B, B Es Ez E Eo

0 0
1 1

0 1 1 0

1
0 1 0 0 1

1 0 1 1
0 1
1 1 1
0
1 0
0 0
0 1 1
1 1 0 1
1 1

excess-3converter
Truthtablefor 3-bitbinaryto
Table 10.5.1 not
combinational circuitswith ROM, itis
designing
Inpracticewhen we are of fuses insidethe unit,
as shown inthe
gate
internal connections
necessary toshow the has to only
fordemonstration purpose only.The designer
This was shown
Fig.10.5.13. as shown in 10.5.14.
the Fig.
and itstruthtable,
specify the ROM (inputsand outputs)
on next page)
(See Fig.10.5.13
A, Aj Ap E E, E Eo

0 1 1
0

1
Oof E 0 1 1 1
Bo Ap
1 1
Binary
Inputs
B,A18x4
BAz
ROM O, E
Excess-3
code
1

1
1

0
1

1
0

1
1 11 0

1 1 0 1 0 0 1

1 1 1 1 0 1
(a)Blockdiagram (b)ROM truthtable
Fig.10.5.14
 Ao A, A, A, A, ,

Ao

A,

Ag
Productterrms
mo

m4

m2

m5

Sum
terms

B3 B2 B Bo

Fig.10.5.13
Exampleswith Solutions

Example 10.5.3Design a combinational

circuit using ROM. The circuitaccepts 3-bitnumber
and generates an output binarynumber equaltosquareofinput number.
AU: 15,May-10,
Dec.-09, 11,
Marks 16
Solution:

Binaryinput Square of number on data

on address lines
lines

B2 B B Fs F4 F, F; F Fo
0 0 0 0

0 1 0 0 1

TECHNICAL PUBLICATIONS - An up thrustforknowledge

 Design 10- 35 Memory and ProgrammableLogicDevices
& System
Princjples
Dital
0 1 0 0 0 0 1 0 0
Oo Fo

F1
0 1 1 0 0 1 0 1

Bo Ao 1 0 0 0 1 0 0 0
8x6 -F2 Square
Binary B A1 ROM outputs 1 1 1 0 0 1
numbers
F3 1 0
B2 Ag F4 1 1 0 1 0 0 1 0 0
Fs
1 1 1 1 1 0 0 1

(b)ROM truthtable
(a)Block diagram 10.5.15
Fig.

Example 10.5.4 Design ROM fr the functions

following

;F,=
F,=)1,2,3) S(0,2) AU: May-11,Marks 7
four minterms and two
The given have 4 minterms.To generate
functions
Solution: address inputsand two data
4 x 2 ROM. For 4 x 2 ROM, thereare two
outputswe need

outputs.
Address Data outputs
inputs

F1
b F,
Ao
4 x2 0 1
ROM
b Fz
Ay 1 1

1 1 1

(b)ROM truthtable
(a)Blockdiagram
Fig.10.5.16

code converterusing
ROM.
binaryto excess 3 AU :May-06, Marks8
Example 10.5.5Implement

Solution
:

Digit 0
Bo Ao
Excess-3code output
A 16x8
Binary B, ROM
input B2
Digit 1
B ffff D
D,
OE

3H
Fig.10.5.17
 10-36 Memory and ProgrammableLogicDevicen
Digital
Principles
& SystemDesign

Address Memory contents

Ds D4 D3 D2 D4 Do
A3 A2 A1 Ao D7 D6
1 1 1
0 0 0 0

0 1 0 1 0

0 1 1
1 0 1
1
0
0
1
1 1
0 1 1 1 1 0

0 0 1 1 1 1 1
1 1 0 1 1 1 0

1 0 1
1
1 1 0 0 1 0
1
1 0 1 1
1 1

1 1 1 0 0 1 1

1 1 1 0 1 1 1
1 1 1 1 1 1 0 0

Table 10.5.2ROM contents

usingROM. AU :Dec.-10,Marks 2
Implement a 2-bitmultiplier
Example 10.5.6

Solution:

Ao Ap Do Po
2-bitinput
Ay A 16x4 D, .P1 4-bitproduct
Do
Ag ROM D P2
inputS
2-bit
B Ag D3 P3

Fig.10.5.18
ROM Truth Table

B Bo A1 Ao P3 P P, Po

1 0 0 0
0 1 0 0 0

0 1 1
0 1 0
0 1 0 1 0 0 0 1
0 1 1 0 0 1 0
1 1 1
 10-37 Memory and ProgrammableLogicDøvices
& System Design
Princijples
Dgtal
0 0 0
0
1 0 1 0
0 0
1
1 0 0 1 0 0

1 1 1 0
1 1 0
1 0 0
0 0
0
1 0
1
1 0
1 1
1 1
1 1 0

1 1 1 0 0
1
1 1 1

AU :May-1 1,Marks 2
functionusingROM.
exclusive-or
10.5.7 Implement the
Example

Solution: Implemernt B Y
A

0 1 1
B Ao 4 x1 OoY 1
ROM 1
A A4 1 1

(b)ROM truthtable
(a)Blockdiagram
Fig.10.5.19
intoa 4-bitGray
a 4-bitbinarycode
that converts
circuit 16
a switching
Example 10.5.8Design AU:May-03, Dec.-10,Marks
code usingROM array.

Solution:
Ap D3 D, D, Do
A3 A
A1
0
1
1
0

1 1 1
0
1 0 1
0 1
0 1
0
1 1 1
1
0
1
1
0 1
1 1 1 0 0
1
1
0 1 1
1
0
0

0 1 1 1
1 0 0 1
1 1 1 0 0

Table 10.5.3
ROM truth table
 & System Design 10-39 Memory and ProgrammableLogicDevices
Principles
Dgtal,

Logic Array(PLA)
10.6 Programmable
AU : Dec.-02,03,05,07,08,09,10,12,14,15, 1 0,11,12.13.15.16
16,May-03,07,08,

ROM. PLA and PAL (Programmable Array Logic) are the variousforms of
Logic Devices(PLDS).
PLDs can be easilyconfigurable
by the individual
Programmable
application.
user forspecific
the minterms every time. Occasionally,they
The combinationalcircuitdo not use all
a ROM
have don'tcare conditions. Don't care conditionwhen implemented with
isthatnot all
never occur. The result the bitpatterns
becomes an address input thatwill
a waste of available
availablein the ROM are used, which may be considered

equipment.
conditionsis excessive,it is more
For cases where the number of don't care
Logic Array
economicalto use a second type of LSIcomponent calleda Programmable
itdoes not provide full decoding
(PLA).A PLA issimilar to a ROM in concept;however
minterms as in the ROM. The PLA
of the variables and does not generatesallthe
to generate
by group of AND gates,each of which can be programmed
replaces decoder at
of the input variables.In PLA, both AND and OR gates have fuses
a product term Fig.10.6.1
in PLA both AND and OR gates are programmable.
the inputs, t herefore
It consistsof n-inputs, output buffer with m outputs,
shows the block diagram of PLA.
product terms constitute
terms, m sum terms, input and output buffers.The
m product a group of m OR gates,called
and the sum terms constitute
a group of m AND gates each
between all n-inputs and theircomplement valuesto
matrix. Fuses are inserted
OR of the AND gates and
AND gates. F uses are alsoprovided between the outputs
of the allowsthe
The third set of fuses in the output inverters
inputs of the OR gates.
AND-OR form or in the AND-OR-INVERT
the
to
function be generatedeitherin the
output To get
i s bypassed by link we get AND-OR implementation.
form. When inverter to be disconnected.
inverterlink
has
AND-OR-INVERTER implementation

Po So
S.
P
m
OR Invert
n Input l4AND outputs
matrix matrix non-invert
inputs< buffer
matrix
:

Pm-1 Sm-1
n-1

Blockdiagramof a PLA
10.6.1
Fig.
 10.6.1
Input Buffer olo

Input buffers are provided in the (a)

PLA to limitloadingof the sourcesthat
inputs. They also provide
the
inverted and non-inverted form of
inputs at its output. The Fig. 10.6.2 (b)
shows two ways of representinginput Fig.10.6.2Input buffer forsingleinput line
bufferforsingleinput.

10.6.2Output Buffer oFo

Thedrivingcapacity of PLA is increased by S,o oF
TTL
providingbuffersat the output.They are usually
TTL
compatible.The Fig.10.6.3shows the tri-state, SN-1O oFN
compatible output buffer. The output buffer may
output.
or tri-state
open collector
providetotem-pole, OE

Fig.10.6.3Output buffers

10.6.3Implementationof CombinationLogicCircuitusingPLA
Like ROM, mask-programmable or field-programmable.
PLA can be With a

mask-programmable PLA, the user must submit. a PLA program table to the
manufacturer.Thistableis used by the vendor to produce a user-made PLA that has the
paths between inputs and outputs.A second type of PLA available
requiredinternal is

calleda Field-Programmable LogicArray or FPLA. The FPLA can be programmed by

the user bymeans of certainrecommended procedures.FPLAscan be programmed with
commerciallyavailableprogrammer units.
As mentioned earlier,
userhas to submit PLA program tableto the manufacturers
to

get the user-made PLA. Let us study how to determine PLA program tablewith the
helpof example.

Examples for Understanding

Example 10.6.1 A combinational

circuit
isdefinedby the functions:

E;= m (3,5, 7),F,= m (4,5, 7)

Implement the circuit
with a PLA having 3 inputs,
3 product terms and two outputs.
Solution:
Step 1: Simplifythe givenBooleanfunctions

The Boolean functionsare simplified, as shown in

the Fig.10.6.4.The simplifed
functionsin sum of productsare obtained from the maps are :
 and
nmable LogicDevÍces
Princjples

ForF1
BC ForF,
A 00 01 11 10 4 BC 00 01 11 10
0 1 0
0 0 0

1 0110 10

e
F= AC + BC
F,=AB + AC
Fig.10.6.4

F = AC + BC, F,= AB + AC

Write PLA program table

Sstep
2:
Productterm Inputs Outputs
A B C
AC 1 1 1 1
BC 2 1 1 1
AB 3 1 1
T T T/C
Table10.6.1
PLA program table
Therefore,there are three distinct
product terms AC, BC and AB, and two sum
:

ems. The PLA program tableshown in Table 10.6.1consistsof three columns

pecifyingproduct terms,inputsand outputs.
The first of product
column givesthe lists
termns The second column specifies
numerically. the requiredpaths between inputsand
AND thirdcolumn specifies
gates.The the requiredpaths between the AND gates and
the OR gates.Under each output variable, we writea T (for true)ifthe output inverter
is to be bypassed,and C (for complement) ifthe functionis to be complemented with
the output inverter.The product terms listed column are not the part
on the leftof first
ofPLA
program tablethey are includedforreferenceonly.

Step 3:Implementation(See Fig. 10.6.5on next page)

Example 10.6.2 Draw toimplement the logicfunctions
PLA circuita

ABC + ABC + AC and BC + BC. A AU:Dec.-08,Marks-6

Solution :
Step 1: the Booleanfunctions
Simplify

A BC+ ABC+ AC = ABC+ A (BC C) +

ABC+ A (B + C)
A + AB = A + B
= ABC+ AB + AC
 10-42 Memory andProgrammableLogicDeviee.
Principles
Digital & System Design

A B B cT
A

3 Productterms

AC

BC

AB

2 Sum
terms

F, F2

Fig.10.6.5

Note The second Booleanfunctionisinsimplified

form.

Step 2 : Implementation
A A BB c C

5 Product terms

ABC

AB

AC

ABC

BC

2 Sum
terms

f,
Fig.10.6.6
TECHNICAL PUBLICATIONSs- An up thrust
forknowledge
 &
Principles System Design 10- 43 Memory and Programmable LogicDevices
Digial

Cample 10.6.3Implement the following using 3x4x2

function
multiboolean PLAPLD.
f(a2,a1 40) = m (0, 1,3, 5) and f2 a0)=
(a2.a1, mn (3,5, 7)

:
Solution f,-map f-map
Step 1: Simplify the Boolean a,a a,ao
functions. 00 01 11 10 00 01 11 10

f = a2 ajta ag +aj a o1.11 :1:

f, = ag ag+ aja0 1
To implement functionsf;and f, Fig.10.6.7K-map simplification
we require 3 x 5x 2 PLA and we
i,-map i,map
have to them using
implemernt a,a
we have to a,
Therefore, 00 01 11 10 00 01 11 10
3x 4 x 2 PLA.

examine product terms by grouping O0 0

Os insteadof 1.That isproductterms

1|0 00 10
for complement of a function.
Fig.10.6.8

= a2 ag+ a1agta2 a1
f = an a1ta1
agtag ao

Step 2:Implementation
a, a, a a0

3 Inputs

4 Productterms

a ao

an a

a, a

000
2 Sum
terms

Programmable
fuse links

Fig.10.6.9Logicdiagram
 10-44 Memory and ProgrammableLogicDevices
Digital
Principles
& System Design

Lookingat functionoutputs we can realize that productterms a2 ag and a a are

common in
both functions. Therefore,we need only 4 product terms and functionscan
10.6.2and Fig.10.6.9.
be implemented using a 3 x 4 x 2 PLA as shown in Table
PLA program table
Productterms Inputs Outputs
a2 a ao f1 f2

1 1 1

afao
1 1
1 1 1
0 1
aza
C
Table10.6.2
gate is programmed to invertthe function
As shown in the Fig.10.6.9exclusive-OR
to get the desiredfunction
outputs.
isdefinedby the functions,
circuit
Example 10.6.4A combinational

;=) m (1,3, 5) = )m (5,6, 7)

witha PLA having 3 inputs,3 productterms and two oukputs.
Inplement the circuit
AU: May-08, Marks 8

Solution: K-map simplification

ForF1 ForF2
BC BC
00 01 11 10 A 00 01 11 10

0 0

1 1

F,= BC+ ÃC F2 =AB +AC

Fig.10.6.10

To implement functionsF; ForF For F

and F we require3x4x2 PLA BC BC
and we have to implement them A 00 01 11 10 00 01 11 10

using 3x3x2 PLA. There we 0 0 0 0 00)

have to examine product terms .
1 0
by grouping Os instead of 1.
That is product terms for
, =C+A B F,=+B0
complement of a function.
Fig.10.6.11
Looking at functionoutputs,
functions and Fi F have one common product term. Thus they have total3 produe
termsand can be implemented using 3x3x2 PLA.
 m table

Productterms Inputs Outputs

A B C F Fz
C 1
AB 1 1 1
AC 1 1 1
T
Table10.6.3

ntation

A A B BC

uts

3 Productterms

AB

AC

2 Sum
terms

Link open
Linkclose
to get
to get
complemented uncomplemented
output
output

2Outputs

Fig.10.6.12

An up thrustforknowtedoe
PUBLICATIONS
TECHNICAL
 Digital
Principles
& System Design 10-46 Momory and Programmable Logic
Devices

Example 10.6.5Designa BCD to Excess-3code converterand implement usingsuitablePL

AU Dec,09,14, Marks lO :
Solution:
Step 1: Derivethe truthtableof BCD to Excess-3 converter

Decimal BCD code Excess-3 code

B, B, B, B E, E, E E
0 0 0 0 0 1 1
1 0 0 0 1 1

2 1 1 0 1

3 1 1 1 1
4 1 1 1 1
5 1 1 1 0

6 0 1 1 1 0 1
7 1 1 1 0 1

8 1 0 0 0 1 1

1 0 1 1 1 0

Table10.6.4TruthtableforBCD to Excess-3code converter

forExcess-3code
Step 2 : Simplifythe Booleanfunctions

For E3 For E2
B,Bo B,Bo
B,B 00 01 11 10 B,B 00 01 11 10

00 0 00 0 1
01 1 01 0

11 X 11 XX X X

10 1 1 X

Eg = B,+ B,Bo + B,B

10 01
E, = B,B,,+ B,B,+ B,B,
X

B,Bo
For E B,Bo
For Eo
B,B 00 01 11 10 B,B, 0 01 11 10
00 1 1 00

01 1 0 1 0 01 1 0 0 1
11 X X xX 11X X X X

10|1 0 xX 101 xX
E, -B,B,
+ B,B, E, = B,B,+ B,,
Flg.10.6.13
 Design 10-47 Memory and ProgrammableLogic Devices
& System
Pncjpes.
program table
WritePLA

Productterms Inputs Outputs

B, B B B Es E E E
1 1
B3
HN
1 1 1
B,B 3 1 1 1
B, B 4 1 0 0 1

B, B Bo 5
1
1 1
B, Bo 6
1 1
B,B1 7
0

1
B, Bo 8
1 1
1
B, Bo 1
9 T/C
T
B Bo

PLA program table

Table 10.6.5

Step 4 : Implementation B, B, B
B, B, B, B, B,

B, 9 Productterms

B
Bo

B, Bo

B,B,

B, B, B,

B, Bo

B, B1

B,Bo

B, B
4 Sum

E E E,
-
E
terms

Fig.10.6.14
orknowledge
-An up thrust
 sections.Each section has three
are four programmable AND gates and one fixed OR
output of section1is connected
The
gate. to a buffer-inverter
gate and then fed back
the inputs of the AND
gates,throughfuses. This allowsthe logicdesignerto feed
output functionback as an inputvariable to create å new function.
Such PALs are
to as Programmable I/OPALs.(ReferFig.
referred 10.7.lon next page.)
The commercial PAL deviceshas more
gates than the one shown in Fig.10.7.1A
PAL integratedcircuit may have
typical eightinputs,eight outputs, and eight sections,
each consisting
of an eight wide AND-OR array.

10.7.1 of CombinationalLogicCircit
Implementation usingPAL

Let usingPAL with the help of

us see the implementationof a combinationalcircuit
examples.

Examples for Understanding

Implement the following

Example 10.7.1 BooleanfunctionsusingPAL.

w (A,B, C, D) = m (0,2, 6, 7,8, 9, 12,13)

=) m (0, 2, 6, 7, 9,12,13,14)
x(A,B, C, D) 8,

y (A, D) =) m (2,3,8, 9,10,12,13)

B, C,

z (A,B, C, D) = m (1,3,4, 6, 9, 12,14)

Solution:

Step 1: Simplifythe fourfunctions

For y
For X CD
For w CD 00 01 11 10
01 11 10 AB
CD 00 01 11 10 ABo0 00
1
AB
1 00 1 i1 00 1

00 1 11 01
01
1
01
1111 i1 1111
1111 10 1 1 101 1 1
101 1
AC+ BCD + BCD + AC
x=BD+ ABC + y=ABC
+ AC
w =ABD+ ABC

TECHNCAL PUBLICATIONS - An up thrust

forknowledge
 Digital
Principles
& System Design 10-60 Memory and Programmable LogicDevices

For z
CD
AB 00 01 11 10
00 1 1
01 1 1
11 1 1
10

z=ABD + BCD + BD
Fig.
10.7.2K-map simplification
A A B B D D W W
Product
terms
1

B
Allfusesintact

7 (always= 0)

10

11.

12

X Fuseintact

Fuseblown
Fig.10.7.1
Arraylogic fortypical
PAL
 10-61 and Programmable LogicDevices
& System Design Memory
Principles
Digital

x has four product terms.Three of them areequal to w. Therefore

latethat function

we writex= W+ BCD.
can

Step 2 : Implementation
The program tablefor PAL
PLA program table.
In the lastsectionwe have seen the
table with product
PLA program table.Table 10.7.1shows PAL
program
is similarto
terms,AND inputsand outputs.

AND inputs Outputs

Product term

A B C D W

BC+ A C
w = A B D+ A
1 0 0

2 0 1 1

3 1
1 X = w + BOD
4

5 1 1 0

AC
7 0 1 y = A BC+ BCD+

0 1 0
8

1 0

0 0 1 z = ABD+ BC D+ BD
10

11 1

12 1
PAL program table
Table 10.7.1
 10-62 Memory and ProgrammableLogicDevices
Digital & System Design
Principles

A A' B B' C C' D D W W

10

11

12

Fig.10.7.3Logic diagram
Design
Example 10.7.2 BCD to Excess-3 converterusing PAL.

Solution:

Step 1: Derivethe truthtableof BCD to Excess-3converter

Decimal BCD code Excess-3code

B3 B B Bo E E, E Eo

0 0 0 0 1 1
1 0 1 1 0

2 1 1 1
3 0 1 1 0 1 1
 10-67
Memory and
ProgrammableLogic
for Practice Devices
mple
10.7.5A combinationallogic
circuit
ample
f.(a,b,c)
(0,1,
6, = is definedby the
7), fala,b,c) following
function.
circuit
with a =X(2,
3,
PAL having three 5,7).
Implement
outputs. inputs,three the
product terms
and two
10.7.6 Design a
Design code converts AU: May-05, Marks 10
circuit which converts
Example PALS. gray code to BCD using

08 Comparison between ROM I

PROM, PLA and PAL
AU :Dec.-03,14,
May-09,17

ROM / PROM
St. PLA
PAL
No.

1. AND arrayisfixedand OR Both AND and OR

arrays OR arrayisfixedand AND
arrayis programmable. areprogrammable. arrayisprogrammable.
2. Cheaper and simpleto use. Costliest
and complex than Cheaperand simpler.
PAL and PROMs.

3 Allminterms are decoded. AND arraycan be AND arraycan be

programmed to get desired programmed to get desired
minterms. mintermns.

4
Only Booleanfunctionsin in
Any Booleanfunctions in
Any Booleanfunctions
standardSOP form can be SOP form can be SOP form can be
implemented usingPROM. implemented usingPLA. implemented usingPLA.

Review Questions

1. How does the architecture from PROM? AU : May-09, Marks 2

offa PLA diferent
a

AU Dec.-03,Marks 2
:
2. Distinguishbetween a PAL and PLA.
AU :Dec.-09,Marks 2
J. What is PAL ? How does it differfromPLA?
AU :Dec.-05,14,May-05,Marks 2
Whether PAL is same as PLA ? Explain.
4.
AU:Dec.-12, Marks 4

). Writea note on PAL.