Serial Communication

RS-232
From Wikipedia, the free encyclopedia
This article is about the RS-232 standard. For RS-232 variants, see serial port .
"V.24" redirects here. For other uses, see V24 (disambiguation).

A DB-25 connector as described in the RS-232 standard

In telecommunications, RS-232 is a standard for serial communication transmission of data. It

formally defines the signals connecting between a DTE (data terminal equipment) such as
a computer terminal, and a DCE (data circuit-terminating equipment, originally defined as data
communication equipment[1]), such as a modem. The RS-232 standard is commonly used
in computer serial ports. The standard defines the electrical characteristics and timing of signals,
the meaning of signals, and the physical size and pinout of connectors. The current version of
the standard is TIA-232-F Interface Between Data Terminal Equipment and Data Circuit-
Terminating Equipment Employing Serial Binary Data Interchange, issued in 1997.
An RS-232 serial port was once a standard feature of a personal computer, used for
connections to modems, printers, mice, data storage, uninterruptible power supplies, and other
peripheral devices. However, RS-232 is hampered by low transmission speed, large voltage
swing, and large standard connectors. In modern personal computers, USBhas displaced RS-
232 from most of its peripheral interface roles. Many computers do not come equipped with RS-
232 ports and must use either an external USB-to-RS-232 converter or an internal expansion
card with one or more serial ports to connect to RS-232 peripherals. Nevertheless, RS-232
devices are still used, especially in industrial machines, networking equipment and scientific
instruments.

Contents

 1 Scope of the standard

 2 History
 3 Limitations of the standard
 4 Role in modern personal computers
 5 Physical interface
o 5.1 Voltage levels
o 5.2 Connectors
o 5.3 Cables
 5.3.1 3-wire and 5-wire RS-232
 6 Data and control signals
o 6.1 Ring indicator
o 6.2 RTS, CTS, and RTR
 7 Seldom used features
o 7.1 Signal rate selection
o 7.2 Loopback testing
o 7.3 Timing signals
o 7.4 Secondary channel
 8 Related standards
 9 Development tools
 10 References
 11 Further reading
 12 External links

Scope of the standard

The Electronic Industries Association (EIA) standard RS-232-C[1] as of 1969 defines:

 Electrical signal characteristics such as voltage levels, signaling rate, timing and slew-rate of
signals, voltage withstand level, short-circuit behavior, and maximum loadcapacitance.
 Interface mechanical characteristics, pluggable connectors and pin identification.
 Functions of each circuit in the interface connector.
 Standard subsets of interface circuits for selected telecom applications.
The standard does not define such elements as the character encoding or the framing of
characters, or error detection protocols. The character format and transmission bit rate are set by
the serial port hardware which may also contain circuits to convert the internal logic levels to RS-
232 compatible signal levels. The standard does not define bit rates for transmission, except that
it says it is intended for bit rates lower than 20,000 bits per second.

History
RS-232 was first introduced in 1962 by the Radio Sector of the EIA.[2][3] The original DTEs were
electromechanical teletypewriters, and the original DCEs were (usually) modems.
When electronic terminals (smart and dumb) began to be used, they were often designed to be
interchangeable with teletypewriters, and so supported RS-232. The C revision of the standard
was issued in 1969 in part to accommodate the electrical characteristics of these devices. [citation
needed]

Since the requirements of devices such as computers, printers, test instruments, POS
terminals and so on were not foreseen by the standard, designers implementing an RS-232
compatible interface on their equipment often interpreted the standard idiosyncratically. The
resulting common problems were non-standard pin assignment of circuits on connectors, and
incorrect or missing control signals. The lack of adherence to the standards produced a thriving
industry of breakout boxes, patch boxes, test equipment, books, and other aids for the
connection of disparate equipment. A common deviation from the standard was to drive the
signals at a reduced voltage. Some manufacturers therefore built transmitters that supplied +5 V
and -5 V and labeled them as "RS-232 compatible".[citation needed]
Later personal computers (and other devices) started to make use of the standard so that they
could connect to existing equipment. For many years, an RS-232-compatible port was a standard
feature for serial communications, such as modem connections, on many computers. It remained
in widespread use into the late 1990s. In personal computer peripherals, it has largely been
supplanted by other interface standards, such as USB. RS-232 is still used to connect older
designs of peripherals, industrial equipment (such asPLCs), console ports and special purpose
equipment.
The standard has been renamed several times during its history as the sponsoring organization
changed its name, and has been variously known as EIA RS-232, EIA 232, and most recently as
TIA 232. The standard continued to be revised and updated by the Electronic Industries
Alliance and since 1988 by the Telecommunications Industry Association (TIA).[4] Revision C was
issued in a document dated August 1969. Revision D was issued in 1986. The current revision
is TIA-232-F Interface Between Data Terminal Equipment and Data Circuit-Terminating
Equipment Employing Serial Binary Data Interchange, issued in 1997. Changes since Revision C
have been in timing and details intended to improve harmonization with the CCITT standard
V.24, but equipment built to the current standard will interoperate with older versions. [citation needed]
Related ITU-T standards include V.24 (circuit identification) and V.28 (signal voltage and timing
characteristics).[citation needed]
In revision D of EIA-232, the D-subminiature connector was formally included as part of the
standard (it was only referenced in the appendix of RS 232 C). The voltage range was extended
to +/- 25 volts, and the circuit capacitance limit was expressly stated as 2500 pF. Revision E of
EIA 232 introduced a new, smaller, standard D-shell 26-pin "Alt A" connector, and made other
changes to improve compatibility with CCITT standards V.24, V.28 and ISO 2110. [5]

Limitations of the standard

Because RS-232 is used beyond the original purpose of interconnecting a terminal with a
modem, successor standards have been developed to address the limitations. Issues with the
RS-232 standard include:[6]

 The large voltage swings and requirement for positive and negative supplies increases
power consumption of the interface and complicates power supply design. The voltage swing
requirement also limits the upper speed of a compatible interface.
 Single-ended signaling referred to a common signal ground limits the noise immunity and
transmission distance.
 Multi-drop connection among more than two devices is not defined. While multi-drop "work-
arounds" have been devised, they have limitations in speed and compatibility.
 The definitions of the two ends of the link are asymmetric. This makes the assignment of the
role of a newly developed device problematic; the designer must decide on either a DTE-like
or DCE-like interface and which connector pin assignments to use.
 The handshaking and control lines of the interface are intended for the setup and takedown
of a dial-up communication circuit; in particular, the use of handshake lines forflow control is
not reliably implemented in many devices.
 No method is specified for sending power to a device. While a small amount of current can
be extracted from the DTR and RTS lines, this is only suitable for low power devices such
as mice.
 The 25-way connector recommended in the standard is large compared to current practice.
 The standard does not address the possibility of connecting a DTE directly to a DTE(can use
null modem cable to connect DTE to DTE), or a DCE to a DCE.

Role in modern personal computers[edit]

PCI Express x1 card with one RS-232 port

Main article: Serial port

In the book PC 97 Hardware Design Guide,[7] Microsoft deprecated support for the RS-232
compatible serial port of the original IBM PC design. Today, RS-232 has mostly been replaced in
personal computers by USB for local communications. Compared with RS-232, USB is faster,
uses lower voltages, and has connectors that are simpler to connect and use. However, USB is
limited by standard to no more than 5 meters of cable, thus favoring RS-232 when longer
distances are needed. Both standards have software support in popular operating systems.
USB is designed to make it easy for device drivers to communicate with hardware. USB is more
complex than the RS-232 standard because it includes a protocol for transferring data to devices.
This requires more software to support the protocol used. There is no direct analog to theterminal
programs used to let users communicate directly with serial ports.
Serial ports of personal computers are also sometimes used to directly control various hardware
devices, such as relays or lamps. Personal computers may use a serial port to interface to
devices such as uninterruptible power supplies. In some cases, serial data is not exchanged, but
the control lines are used to signal conditions such as loss of power or low battery alarms. An
application program can detect or change the state of RS 232 control lines in the registers of the
serial hardware using only a few input/output instructions; by contrast, a USB interface requires
software to decode the serial data.
Devices that convert between USB and RS-232 do not work with all software or on all personal
computers.
In fields such as laboratory automation or surveying, RS 232 devices may continue to be
used. PLCs, VFDs, servo drives, and CNC equipment are programmable via RS-232. Some
manufacturers have responded to this demand: Toshiba re-introduced the DE-9M connector on
the Tecra laptop.
Serial ports with RS-232 are also commonly used to communicate to headless systems such
as servers, where no monitor or keyboard is installed, during boot when operating system is not
running yet and therefore no network connection is possible. An RS-232 serial port can
communicate to some embedded systems such as routers as an alternative to network mode of
monitoring.

Physical interface
In RS-232, user data is sent as a time-series of bits. Both synchronous and asynchronous
transmissions are supported by the standard. In addition to the data circuits, the standard defines
a number of control circuits used to manage the connection between the DTE and DCE. Each
data or control circuit only operates in one direction, that is, signaling from a DTE to the attached
DCE or the reverse. Since transmit data and receive data are separate circuits, the interface can
operate in a full duplex manner, supporting concurrent data flow in both directions. The standard
does not define character framing within the data stream, or character encoding.
Voltage levels[edit]

Diagrammatic oscilloscope trace of voltage levels for an ASCII "K" character (0x4B) with 1 start bit, 8 data
bits, 1 stop bit. This is typical for start-stop communications, but the standard does not dictate a character
format or bit order.
RS-232 data line on the terminals of the receiver side (RxD) probed by an oscilloscope (for an ASCII "K"
character (0x4B) with 1 start bit, 8 data bits, 1 stop bit and no parity bits).

The RS-232 standard defines the voltage levels that correspond to logical one and logical zero
levels for the data transmission and the control signal lines. Valid signals are either in the range
of +3 to +15 volts or the range -3 to -15 volts with respect to the "Common Ground" (GND) pin;
consequently, the range between -3 to +3 volts is not a valid RS-232 level. For data transmission
lines (TxD, RxD and their secondary channel equivalents) logic one is defined as a negative
voltage, the signal condition is called "mark". Logic zero is positive and the signal condition is
termed "space". Control signals have the opposite polarity: the asserted or active state is positive
voltage and the deasserted or inactive state is negative voltage. Examples of control lines
include request to send (RTS), clear to send (CTS), data terminal ready (DTR), and data set
ready (DSR).

RS232 logic and voltage levels

Data
Control circuits Voltage
circuits

0 (space) Asserted +3 to +15 V

1 (mark) Deasserted -15 to -3 V

The standard specifies a maximum open-circuit voltage of 25 volts: signal levels of ±5 V, ±10 V,
±12 V, and ±15 V are all commonly seen depending on the voltages available to the line driver
circuit. Some RS-232 driver chips have inbuilt circuitry to produce the required voltages from a 3
or 5 volt supply. RS-232 drivers and receivers must be able to withstand indefinite short circuit to
ground or to any voltage level up to ±25 volts. The slew rate, or how fast the signal changes
between levels, is also controlled.
Because the voltage levels are higher than logic levels typically used by integrated circuits,
special intervening driver circuits are required to translate logic levels. These also protect the
device's internal circuitry from short circuits or transients that may appear on the RS-232
interface, and provide sufficient current to comply with the slew rate requirements for data
transmission.
Because both ends of the RS-232 circuit depend on the ground pin being zero volts, problems
will occur when connecting machinery and computers where the voltage between the ground pin
on one end, and the ground pin on the other is not zero. This may also cause a
hazardous ground loop. Use of a common ground limits RS-232 to applications with relatively
short cables. If the two devices are far enough apart or on separate power systems, the local
ground connections at either end of the cable will have differing voltages; this difference will
reduce the noise margin of the signals. Balanced, differential, serial connections such as
USB, RS-422 and RS-485 can tolerate larger ground voltage differences because of the
differential signaling.[8]
Unused interface signals terminated to ground will have an undefined logic state. Where it is
necessary to permanently set a control signal to a defined state, it must be connected to a
voltage source that asserts the logic 1 or logic 0 level, for example with a pullup resistor. Some
devices provide test voltages on their interface connectors for this purpose.
Connectors
RS-232 devices may be classified as Data Terminal Equipment (DTE) or Data Communication
Equipment (DCE); this defines at each device which wires will be sending and receiving each
signal. The standard recommended but did not make mandatory the D-subminiature 25-pin
connector. According to the standard, male connectors have DTE pin functions, and female
connectors have DCE pin functions. Other devices may have any combination of connector
gender and pin definitions. Many terminals were manufactured with female connectors but were
sold with a cable with male connectors at each end; the terminal with its cable satisfied the
recommendations in the standard. The standard specifies 20 different signal connections. Since
most devices use only a few signals, smaller connectors can often be used.
Personal computer manufacturers replaced the DB-25M connector by the smaller DE-9M
connector. Different pin numbers were used for the signals (for this see serial port). This
connector, with varying pinouts, became common for personal computers and related devices.
Presence of a 25-pin D-sub connector does not necessarily indicate an RS-232-C compliant
interface. For example, on the original IBM PC, a male D-sub was an RS-232-C DTE port (with a
non-standard current loop interface on reserved pins), but the female D-sub connector on the
same PC model was used for the parallel Centronics printer port. Some personal computers put
non-standard voltages or signals on some pins of their serial ports.
Cables
Main article: Serial cable
The standard does not define a maximum cable length but instead defines the maximum
capacitance that a compliant drive circuit must tolerate. A widely used rule of thumb indicates
that cables more than 50 feet (15 m) long will have too much capacitance, unless special cables
are used. By using low-capacitance cables, full speed[clarification needed]communication can be
maintained over larger distances up to about 1,000 feet (300 m).[9] For longer distances, other
signal standards are better suited to maintain high speed.
Since the standard definitions are not always correctly applied, it is often necessary to consult
documentation, test connections with a breakout box, or use trial and error to find a cable that
works when interconnecting two devices. Connecting a fully standard-compliant DCE device and
DTE device would use a cable that connects identical pin numbers in each connector (a so-
called "straight cable"). "Gender changers" are available to solve gender mismatches between
cables and connectors. Connecting devices with different types of connectors requires a cable
that connects the corresponding pins according to the table above. Cables with 9 pins on one
end and 25 on the other are common. Manufacturers of equipment with 8P8C connectors usually
provide a cable with either a DB-25 or DE-9 connector (or sometimes interchangeable
connectors so they can work with multiple devices). Poor-quality cables can cause false signals
by crosstalk between data and control lines (such as Ring Indicator).
If a given cable will not allow a data connection, especially if a gender changer is in use, a null
modem cable may be necessary. Gender changers and null modem cables are not mentioned in
the standard, so there is no officially sanctioned design for them.
3-wire and 5-wire RS-232
A minimal "3-wire" RS-232 connection consisting only of transmit data, receive data, and ground,
is commonly used when the full facilities of RS-232 are not required. Even a two-wire connection
(data and ground) can be used if the data flow is one way (for example, a digital postal scale that
periodically sends a weight reading, or a GPS receiver that periodically sends position, if no
configuration via RS-232 is necessary). When only hardware flow control is required in addition
to two-way data, the RTS and CTS lines are added in a 5-wire version.
Data and control signals
The following table lists commonly used RS-232 signals (called "circuits" in the specifications)
and pin assignments.[10] See serial port (pinouts) for non-standard variations including the
popular DE-9 connector.

Circuit Origin DB-25

Name Typical purpose Abbreviation DTE DCE pin
Data Terminal DTE is ready to receive, initiate, or continue a
DTR ● 20
Ready call.
Data Carrier DCE is receiving a carrier from a remote
DCD ● 8
Detect DCE.
Data Set Ready DCE is ready to receive commands or data. DSR ● 6
DCE has detected an incoming ring signal on
Ring Indicator RI ● 22
the telephone line.
Request To DTE requests the DCE prepare to transmit
RTS ● 4
Send data.
Ready To DTE is ready to receive data from DCE. If in
RTR ● 4
Receive use, RTS is assumed to be always asserted.
Clear To Send DCE is ready to accept data from the DTE. CTS ● 5
Transmitted
Carries data from DTE to DCE. TxD ● 2
Data
Received Data Carries data from DCE to DTE. RxD ● 3
Common
Zero voltage reference for all of the above. GND common 7
Ground
Protective
Connected to chassis ground. PG common 1
Ground

The signals are named from the standpoint of the DTE. The ground pin is a common return for
the other connections, and establishes the "zero" voltage to which voltages on the other pins are
referenced. The DB-25 connector includes a second "protective ground" on pin 1; this is
connected to equipment frame ground.
Data can be sent over a secondary channel (when implemented by the DTE and DCE devices),
which is equivalent to the primary channel. Pin assignments are described in following table:

Signal Pin
Common Ground 7 (same as primary)
Secondary Transmitted Data (STD) 14
Secondary Received Data (SRD) 16
Secondary Request To Send (SRTS) 19
Secondary Clear To Send (SCTS) 13
Secondary Carrier Detect (SDCD) 12
Ring indicator
Ring Indicator (RI), is a signal sent from the DCE to the DTE device. It indicates to the terminal
device that the phone line is ringing. In many computer serial ports, a hardware interrupt is
generated when the RI signal changes state. Having support for this hardware interrupt means
that a program or operating system can be informed of a change in state of the RI pin, without
requiring the software to constantly "poll" the state of the pin. RI does not correspond to another
signal that carries similar information the opposite way.
On an external modem the status of the Ring Indicator pin is often coupled to the "AA" (auto
answer) light, which flashes if the RI signal has detected a ring. The asserted RI signal follows
the ringing pattern closely, which can permit software to detect distinctive ring patterns.
The Ring Indicator signal is used by some older uninterruptible power supplies (UPS's) to signal
a power failure state to the computer.
Certain personal computers can be configured for wake-on-ring, allowing a computer that is
suspended to answer a phone call.
RTS, CTS, and RTR
Further information: Flow control (data)
The RTS and CTS signals were originally defined for use with half-duplex (one direction at a
time) modems that disable their transmitters when not required, and must transmit a
synchronization preamble to the receiver when they are re-enabled. The DTE asserts RTS to
indicate a desire to transmit to the DCE, and in response the DCE asserts CTS to grant
permission, once synchronization with the DCE at the far end is achieved. Such modems are no
longer in common use. There is no corresponding signal that the DTE could use to temporarily
halt incoming data from the DCE. Thus RS-232's use of the RTS and CTS signals, per the older
versions of the standard, is asymmetric.
This scheme is also employed in present-day RS-232 to RS-485 converters. RS-485 is a
multiple-access bus on which only one device can transmit at a time, a concept that is not
provided for in RS-232. The RS-232 device asserts RTS to tell the converter to take control of
the RS-485 bus so that the converter, and thus the RS-232 device, can send data onto the bus.
Modern communications environments use full-duplex (both directions simultaneously) modems.
In that environment, DTEs have no reason to deassert RTS. However, due to the possibility of
changing line quality, delays in processing of data, etc., there is a need for symmetric,
bidirectional flow control.
A symmetric alternative providing flow control in both directions was developed and marketed in
the late 1980s by various equipment manufacturers. It redefined the RTS signal to mean that the
DTE is ready to receive data from the DCE. This scheme was eventually codified in version RS-
232-E (actually TIA-232-E by that time) by defining a new signal, "RTR (Ready to Receive),"
which is CCITT V.24 circuit 133. TIA-232-E and the corresponding international standards were
updated to show that circuit 133, when implemented, shares the same pin as RTS (Request to
Send), and that when 133 is in use, RTS is assumed by the DCE to be asserted at all times. [11]
In this scheme, commonly called "RTS/CTS flow control" or "RTS/CTS handshaking" (though the
technically correct name would be "RTR/CTS"), the DTE asserts RTR to whenever it is ready to
receive data from the DCE, and the DCE asserts CTS whenever it is ready to receive data from
the DTE. Unlike the original use of RTS and CTS with half-duplex modems, these two signals
operate independently from one another. This is an example of hardware flow control. However,
"hardware flow control" in the description of the options available on an RS-232-equipped device
does not always mean RTS/CTS handshaking.
Note that equipment using this protocol must be prepared to buffer some extra data, since a
transmission may have begun just before the control line state change.

Seldom used features

The EIA-232 standard specifies connections for several features that are not used in most
implementations. Their use requires 25-pin connectors and cables.
Signal rate selection
The DTE or DCE can specify use of a "high" or "low" signaling rate. The rates as well as which
device will select the rate must be configured in both the DTE and DCE. The prearranged device
selects the high rate by setting pin 23 to ON.
Loopback testing
Many DCE devices have a loopback capability used for testing. When enabled, signals are
echoed back to the sender rather than being sent on to the receiver. If supported, the DTE can
signal the local DCE (the one it is connected to) to enter loopback mode by setting pin 18 to ON,
or the remote DCE (the one the local DCE is connected to) to enter loopback mode by setting pin
21 to ON. The latter tests the communications link as well as both DCE's. When the DCE is in
test mode it signals the DTE by setting pin 25 to ON.
A commonly used version of loopback testing does not involve any special capability of either
end. A hardware loopback is simply a wire connecting complementary pins together in the same
connector (see loopback).
Loopback testing is often performed with a specialized DTE called a bit error rate tester (or
BERT).
Timing signals
Some synchronous devices provide a clock signal to synchronize data transmission, especially at
higher data rates. Two timing signals are provided by the DCE on pins 15 and 17. Pin 15 is the
transmitter clock, or send timing (ST); the DTE puts the next bit on the data line (pin 2) when this
clock transitions from OFF to ON (so it is stable during the ON to OFF transition when the DCE
registers the bit). Pin 17 is the receiver clock, or receive timing (RT); the DTE reads the next bit
from the data line (pin 3) when this clock transitions from ON to OFF.
Alternatively, the DTE can provide a clock signal, called transmitter timing (TT), on pin 24 for
transmitted data. Data is changed when the clock transitions from OFF to ON and read during
the ON to OFF transition. TT can be used to overcome the issue where ST must traverse a cable
of unknown length and delay, clock a bit out of the DTE after another unknown delay, and return
it to the DCE over the same unknown cable delay. Since the relation between the transmitted bit
and TT can be fixed in the DTE design, and since both signals traverse the same cable length,
using TT eliminates the issue. TT may be generated by looping ST back with an appropriate
phase change to align it with the transmitted data. ST loop back to TT lets the DTE use the DCE
as the frequency reference, and correct the clock to data timing.
Synchronous clocking is required for such protocols as SDLC, HDLC, and X.25.
Secondary channel
There is a secondary data channel, identical in capability to the first. Five signals (plus the
common ground of the primary channel) comprise the secondary channel: Secondary
Transmitted Data (STD), Secondary Received Data (SRD), Secondary Request To Send
(SRTS), Secondary Clear To Send (SCTS), and Secondary Carrier Detect (SDCD).

Related standards
Other serial signaling standards may not interoperate with standard-compliant RS-232 ports. For
example, using the TTL levels of near +5 and 0 V puts the mark level in the undefined area of the
standard. Such levels are sometimes used with NMEA 0183-compliant GPS receivers and depth
finders.
A 20 mA current loop uses the absence of 20 mA current for high, and the presence of current in
the loop for low; this signaling method is often used for long-distance andoptically isolated links.
Connection of a current-loop device to a compliant RS-232 port requires a level translator.
Current-loop devices can supply voltages in excess of the withstand voltage limits of a compliant
device. The original IBM PC serial port card implemented a 20 mA current-loop interface, which
was never emulated by other suppliers ofplug-compatible equipment.
Other serial interfaces similar to RS-232:

 RS-422 (a high-speed system similar to RS-232 but with differential signaling)

 RS-423 (a high-speed system similar to RS-422 but with unbalanced signaling)
 RS-449 (a functional and mechanical interface that used RS-422 and RS-423 signals - it
never caught on like RS-232 and was withdrawn by the EIA)
 RS-485 (a descendant of RS-422 that can be used as a bus in multidrop configurations)
 MIL-STD-188 (a system like RS-232 but with better impedance and rise time control)
 EIA-530 (a high-speed system using RS-422 or RS-423 electrical properties in an EIA-232
pinout configuration, thus combining the best of both; supersedes RS-449)
 EIA/TIA-561 8 Position Non-Synchronous Interface Between Data Terminal Equipment and
Data Circuit Terminating Equipment Employing Serial Binary Data Interchange
 EIA/TIA-562 Electrical Characteristics for an Unbalanced Digital Interface (low-voltage
version of EIA/TIA-232)
 TIA-574 (standardizes the 9-pin D-subminiature connector pinout for use with EIA-232
electrical signalling, as originated on the IBM PC/AT)

Development tools
When developing or troubleshooting systems using RS-232, close examination of hardware
signals can be important to find problems. A serial line analyzer is a device similar to a logic
analyzer but specialized for RS-232's voltage levels, connectors, and, where used, clock signals.
The serial line analyzer can collect, store, and display the data and control signals, allowing
developers to view them in detail. Some simply display the signals as waveforms; more elaborate
versions include the ability to decode characters inASCII or other common codes and to interpret
common protocols used over RS-232 such as SDLC, HDLC, DDCMP, and X.25. Serial line
analyzers are available as standalone units, as software and interface cables for general-
purpose logic analyzers and oscilloscopes, and as programs that run on common personal
computers and devices.

RS-422

RS-422

Standard TIA/EIA-422

Physical Media Twisted Pair

Network Topology Point-to-point, Multi-dropped

Maximum Devices 10 (1 driver & 10 receivers)

Maximum Distance 1500 metres (4,900 ft)

 Mode of Operation Differential

Maximum Binary Rate 100 kbit/s – 10 Mbit/s

Voltage Levels −6V to +6V (maximum differential Voltage)

Mark (1) Negative Voltages

Space (0) Positive voltages

Available Signals Tx+, Tx-, Rx+, Rx- (Full Duplex)

Connector types Not specified

RS-422, also known as TIA/EIA-422, is a technical standard originated by the Electronic

Industries Alliance that specifies electrical characteristics of a digital signaling circuit. Differential
signaling can transmit data at rates as high as 10 Mbit/s, or may be sent on cables as long as
1500 meters. Some systems directly interconnect using RS-422 signals, or RS-422 converters
may be used to extend the range of RS-232 connections. The standard only defines signal
levels; other properties of a serial interface, such as electrical connectors and pin wiring, are set
by other standards.

Contents

 1 Standard scope
 2 Characteristics
 3 Applications
 4 See also
 5 References
 6 External links

Standard scope
RS-422 is the common short form title of American National Standards Institute (ANSI)
standard ANSI/TIA/EIA-422-B Electrical Characteristics of Balanced Voltage Differential Interface
Circuits and its international equivalent ITU-T Recommendation T-REC-V.11,[1] also known
as X.27. These technical standards specify the electrical characteristics of the balanced voltage
digital interface circuit.[2] RS-422 provides for data transmission, using balanced, or differential,
signaling, with unidirectional/non-reversible, terminated or non-terminated transmission lines,
point to point, or multi-drop. In contrast to EIA-485 (which is multi-point instead of multi-drop),
RS-422/V.11 does not allow multiple drivers but only multiple receivers.
Revision B, published in May 1994 was reaffirmed by the Telecommunications Industry
Association in 2005.
Characteristics

Data Rate / Line Length chart from RS-422 Annex A

Several key advantages offered by this standard include the differential receiver, a differential
driver and data rates as high as 10 Megabits per second at 12 meters (40 ft). The specification is
for circuits with a data rate up to 10 Mbit/s, but since the signal quality degrades with cable
length, the maximum data rate decreases as cable length increases. Figure A.1 in the annex
plotting this stops at 10Mbit/s.
The maximum cable length is not specified in the standard, but guidance is given in its annex.
(This annex is not a formal part of the standard, but is included for information purposes only.)
Limitations on line length and data rate varies with the parameters of the cable length, balance,
and termination, as well as the individual installation. Figure A.1 shows a maximum length of
1200 meters, but this is with a termination and the annex discusses the fact that many
applications can tolerate greater timing and amplitude distortion, and that experience has shown
that the cable length may be extended to several kilometers. Conservative maximum data rates
with 24AWG UTP (POTS) cable are 10 Mbit/s at 12 m to 90 kbit/s at 1200 m as shown in the
figure A.1. This figure is a conservative guide based on empirical data, not a limit imposed by the
standard.
RS-422 specifies the electrical characteristics of a single balanced signal. The standard was
written to be referenced by other standards that specify the complete DTE/DCE interface for
applications which require a balanced voltage circuit to transmit data. These other standards
would define protocols, connectors, pin assignments and functions. Standards such as EIA-
530 (DB-25 connector) and EIA-449 (DC-37 connector) use RS-422 electrical signals. Some RS-
422 devices have 4 screw terminals for pairs of wire, with one pair used for data in one direction.
RS-422 cannot implement a true multi-point communications network such as with EIA-485 since
there can be only one driver on each pair of wires, however one driver can be connected to up to
ten receivers.
RS-422 can interoperate with interfaces designed to MIL-STD-188-114B, but they are not
identical. RS-422 uses a nominal 0 to 5 volt signal while MIL-STD-188-114B uses a signal
symmetric about 0 V. However the tolerance for common mode voltage in both specifications
allows them to interoperate. Care must be taken with the termination network.
EIA-423 is a similar specification for unbalanced signaling (RS-423).

Applications
A common use of RS-422 is for RS-232 extenders.
An RS-232-compatible variant of RS-422 using a mini-DIN-8 connector was widely used
on Macintosh hardware until it (and ADB) were replaced by Universal Serial Bus on theiMac in
1998.
Broadcast automation systems and post-production linear editing facilities use RS-422A to
remotely control the players/recorders located in the central apparatus room. In most cases
the Sony 9-pin connection is used, which makes use of a standard DE-9 connector. This is a de
facto industry standard connector for RS-422 used by many manufacturers.
When used in relation to communications wiring, RS-422 wiring refers to cable made of 2 sets
of twisted pair, often with each pair being shielded, and a ground wire. While a double pair cable
may be practical for many RS-422 applications, the RS-422 specification only defines one signal
path and does not assign any function to it. Any complete cable assembly with connectors should
be labeled with the specification that defined the signal function and mechanical layout of the
connector, such as RS-449.

RS-485
a

TIA-485-A (Revision of EIA-485)

Standard ANSI/TIA/EIA-485-A-1998
Approved: March 3, 1998
Reaffirmed: March 28, 2003

Physical media Balanced Interconnecting Cable

Network topology Point-to-point, Multi-dropped, Multi-point

Maximum devices At least 32 unit loads

Maximum distance Not specified

Mode of operation Different Receiver levels:

Binary 1 (OFF)
(Voa-Vob < -200 mV)
Binary 0 (ON)
(Voa-Vob > +200 mV)

Available signals A, B, C

Connector types Not specified

TIA-485-A, also known as ANSI/TIA/EIA-485, TIA/EIA-485, EIA-485 or RS-485, is a standard

defining the electrical characteristics of drivers and receivers for use
in balanced digital multipoint systems. The standard is published by the Telecommunications
Industry Association/Electronic Industries Alliance (TIA/EIA). Digital communications networks
implementing the EIA-485 standard can be used effectively over long distances and in electrically
noisy environments. Multiple receivers may be connected to such a network in a linear, multi-
 drop configuration. These characteristics make such networks useful in industrial environments
and similar applications.
The EIA once labeled all its standards with the prefix "RS" (Recommended Standard), but the
EIA-TIA officially replaced "RS" with "EIA/TIA" to help identify the origin of its standards. [1] The
EIA has officially disbanded and the standard is now maintained by the TIA. The RS-485
standard is superseded by TIA-485, but often engineers and applications guides continue to use
the RS designation.

Contents

 1 Overview
 2 Standard scope and definition
 3 Master-slave arrangement
 4 Three-wire connection
 5 Full duplex operation
 6 Applications
 7 Connectors
o 7.1 Pin labeling
 8 Waveform example
 9 See also
 10 References
 11 External links

Overview
RS-485 enables the configuration of inexpensive local networks and multidrop communications
links. It offers data transmission speeds of 35 Mbit/s up to 10 m and 100 kbit/s at 1200 m. Since
it uses a differential balanced line over twisted pair (like RS-422), it can span relatively large
distances (up to 4,000 feet (1,200 m)). A rule of thumb is that the speed in bit/s multiplied by the
length in meters should not exceed 108. Thus a 50 meter cable should not signal faster than 2
Mbit/s.[2]
In contrast to RS-422, which has a single driver circuit which cannot be switched off, RS-485
drivers need to be put in transmit mode explicitly by asserting a signal to the driver. This allows
RS-485 to implement linear bus topologies using only two wires. The equipment located along a
set of RS-485 wires are interchangeably called nodes, stations or devices. [3]
The recommended arrangement of the wires is as a connected series of point-to-point
(multidropped) nodes, i.e. a line or bus, not a star, ring, or multiply connected network. Ideally,
the two ends of the cable will have a termination resistor connected across the two wires.
Without termination resistors, reflections of fast driver edges can cause multiple data edges that
can cause data corruption. Termination resistors also reduce electrical noise sensitivity due to
the lower impedance, and bias resistors (see below) are required. The value of each termination
resistor should be equal to the cable characteristic impedance (typically, 120 ohms for twisted
pairs).
Star and ring topologies are not recommended because of signal reflections or excessively low
or high termination impedance. If a star configuration is unavoidable, special RS-485 star/hub
repeaters are available which bidirectionally listen for data on each span and then retransmit the
data onto all other spans.
Typical bias network together with termination. Biasing and termination values are not specified in the RS-
485 standard.

Somewhere along the set of wires, pull up or pull down resistors are established to fail-safe bias
each data wire when the lines are not being driven by any device. This way, the lines will be
biased to known voltages and nodes will not interpret the noise from undriven lines as actual
data; without biasing resistors, the data lines float in such a way that electrical noise sensitivity is
greatest when all device stations are silent or unpowered. [4]

Standard scope and definition

RS-485 only specifies electrical characteristics of the generator and the receiver. It does not
specify or recommend any communications protocol, only the physical layer. Other standards
define the protocols for communication over an RS-485 link. The foreword to the standard
recommends The Telecommunications Systems Bulletin TSB-89 which contains application
guidelines, including data signaling rate vs. cable length, stub length, and configurations.
Section 4 defines the electrical characteristics of the generator (transmitter or driver), receiver,
transceiver, and system. These characteristics include: definition of a unit load, voltage ranges,
open circuit voltages, thresholds, and transient tolerance. It also defines three generator interface
points (signal lines); "A", "B" and "C". The data is transmitted on "A" and "B". "C" is a ground
reference. This section also defines the logic states 1 (off) and 0 (on), by the polarity between A
and B terminals. If A is negative with respect to B, the state is binary 1. The reversed polarity
(A +, B −) is binary 0. The standard does not assign any logic function to the two states.

Master-slave arrangement
Often in a master-slave arrangement when one device dubbed "the master" initiates all
communication activity, the master device itself provides the bias and not the slave devices. In
this configuration, the master device is typically centrally located along the set of RS-485 wires,
so it would be two slave devices located at the physical end of the wires that would provide
the termination. The master device itself would provide termination if it were located at a physical
end of the wires, but that is often a bad design [5] as the master would be better located at a
halfway point between the slave devices, to maximize signal strength and therefore line distance
and speed. Applying the bias at multiple node locations could possibly cause a violation of the
RS-485 specification and cause communications to malfunction.
Three-wire connection

RS-485 3 wire connection

Connection of a third wire between the source and receiver may be done to limit the common
mode voltage that can be impressed on the receiver inputs.

Full duplex operation

RS-485, like RS-422, can be made full-duplex by using four wires. Since RS-485 is a multi-point
specification, however, this is not necessary in many cases. RS-485 and RS-422 can
interoperate with certain restrictions.
Converters between RS-485 and other formats are available to allow a personal computer to
communicate with remote devices. By using "Repeaters" and "Multi-Repeaters" very large RS-
485 networks can be formed. TSB-89A, The Application Guidelines for TIA/EIA-485-A has one
diagram called "Star Configuration. Not recommended." Using an RS-485 "Multi-Repeater" can
allow for "Star Configurations" with "Home Runs" (or multi-drop) connections similar to Ethernet
Hub/Star implementations (with greater distances). Hub/Star systems (with "Multi-Repeaters")
allow for very maintainable systems, without violating any of the RS-485 specifications.
Repeaters can also be used to extend the distance or number of nodes on a network.

Applications
RS-485 signals are used in a wide range of computer and automation systems. In a computer
system, SCSI-2 and SCSI-3 may use this specification to implement the physical layer for data
transmission between a controller and a disk drive. RS-485 is used for low-speed data
communications in commercial aircraft cabins vehicle bus. It requires minimal wiring, and can
share the wiring among several seats, reducing weight.
RS-485 is used as the physical layer underlying many standard and proprietary automation
protocols used to implement Industrial Control Systems, including the most common versions
of Modbus and Profibus. These are used in programmable logic controllers and on factory floors.
Since it is differential, it resists electromagnetic interference from motors and welding equipment.
In theatre and performance venues RS-485 networks are used to control lighting and other
systems using the DMX512 protocol.
RS-485 is also used in building automation as the simple bus wiring and long cable length is
ideal for joining remote devices. It may be used to control video surveillance systems or to
interconnect security control panels and devices such as access control card readers.
It's also used in model railway: the layout is controlled by a command station using DCC. The
external interface to the DCC command station is often RS-485 used by hand-held
controllers[6] or for controlling the layout in a network/PC environment. [7] Connectors in this case
are 8P8C / RJ45.
Although many applications use RS-485 signal levels; the speed, format, and protocol of the data
transmission is not specified by RS-485. Interoperability of even similar devices from different
manufacturers is not assured by compliance with the signal levels alone.
Connectors
RS-485 does not specify any connector or pinout. Circuits may be terminated on screw
terminals, D-subminiature connectors, or other types of connectors.
Pin labeling
The RS-485 differential line consists of two pins:

 A aka '+' aka TxD+/RxD+ aka non-inverting pin

 B aka '−' aka TxD−/RxD− aka inverting pin
 SC aka G aka reference pin.
The SC line is the optional voltage reference connection. This is the reference potential used by
the transceiver to measure the A and B voltages.
The B line is positive (compared to A) when the line is idle (i.e., data is 1).
In addition to the A and B connections, the EIA standard also specifies a third interconnection
point called C, which is the common signal reference ground.
These names are all in use on various equipment, but the actual standard released by EIA only
uses the names A and B. However, despite the unambiguous standard, there is much confusion
about which is which:
The RS-485 signaling specification shows that signal A is the non-inverting pin and signal B is
the inverting pin.[8]
This is in accordance with the A/B naming used by most differential transceiver manufacturers,
including, among others:

 Texas Instruments, as seen in their application handbook on EIA-422/485 communications

(A=non-inverting, B=inverting)
 Intersil, as seen in their data sheet for the ISL4489 transceiver [9]
 Maxim, as seen in their data sheet for the MAX483 transceiver[10]
 Linear Technology, as seen in their datasheet for the LTC2850, LTC2851, LTC2852 [11]
 Analog Devices, as seen in their datasheet for the ADM3483, ADM3485, ADM3488,
ADM3490, ADM3491[12]
 FTDI, as seen in their datasheet for the USB-RS485-WE-1800-BT [13]
These manufacturers are correct, and their practice is in widespread use, but care must be taken
when using A/B naming.
To avoid these confusions, some equipment manufacturers have created a
third D+ and D− naming convention. D is the input (drive) signal, D− is electrically inverting, and
D+ is electrically non-inverting.
The standard does not discuss cable shielding, but makes some recommendations on preferred
methods of interconnecting the signal reference common and equipment case grounds.

Waveform example
The diagram below shows potentials of the '+' and '−' pins of an RS-485 line during transmission
of one byte (0xD3, least significant bit first) of data using an asynchronous start-stop method.
References
1. Jump up^ "Trim-the-fat-off-RS-485-designs". EE Times. 2000.
2. Jump up^ Soltero, Manny; Zhang, Jing; Cockril, Chris; Zhang, Kevin; Kinnaird, Clark; Kugelstadt,
Thomas (May 2010) [2002]. RS-422 and RS-485 Standards Overview and System Configurations,
Application Report (pdf). Texas Instruments (Technical report). SLLA070D.
3. Jump up^ Electronic Industries Association (1983). Electrical Characteristics of Generators and
Receivers for Use in Balanced Multipoint Systems. EIA Standard RS-485.OCLC 10728525.[page needed]
4. Jump up^ DS3695,DS3695A,DS3695AT,DS3695T,DS96172,
DS96174,DS96F172MQML,DS96F174MQML: Application Note 847 FAILSAFE Biasing of
Differential Buses (Literature Number: SNLA031) (PDF), Texas Instruments, 1998
5. Jump up^ Thomas, George (March–April 2008). "Examining the BACnet MS/TP Physical
Layer" (PDF). the Extension (Contemporary Control Systems, Inc.) 9 (2).
6. Jump up^ "XpressNET FAQ", lenzusa.com, accessed July 26, 2015
7. Jump up^ "BiDiBus, a Highspeed-Bus for model-railways", bidib.org, accessed July 26, 2015.
8. Jump up^ "Polarity conventions" (PDF). Texas Instruments. 2003.
9. Jump up^ Data Sheet FN6074.3: ±15kV ESD Protected, 1/8 Unit Load, 5V, Low Power, High
Speed and Slew Rate Limited, Full Duplex, RS-485/RS-422 Transceivers (PDF), Intersil
Corporation, 28 April 2006
10. Jump up^ Data Sheet 19-0122 – MAX481/MAX483/MAX485/MAX487–MAX491/MAX1487: Low-
Power, Slew-Rate-Limited RS-485/RS-422 Transceivers (PDF), Maxim Integrated, September
2009
11. Jump up^ LTC2850/LTC2851/LTC2852 3.3V 20Mbps RS485/RS422 Transceivers (PDF), Linear
Technology Corporation, 2007
12. Jump up^ ADM3483/ADM3485/ADM3488/ADM3490/ADM3491 (Rev. E) (PDF), Analog Devices,
Inc., 22 November 2011
13. Jump up^ USB to RS485 Serial Converter Cable Datasheet (PDF), Future Technology Devices
International Ltd, 27 May 2010

RS-423

RS423

Standard EIA RS-423

Physical Media Group of copper cables

Network Topology Point-to-point, Multi-dropped

Maximum Devices 10 (1 driver & 10 receivers)

 Maximum Distance 1200 metres (4000 feet)

Mode of Operation Single-ended (unbalanced)

Maximum Baud Rate Up to 100kbit/s

Voltage Levels -6V to +6V (maximum)

Mark(1) -4V to -6V

Space(0) +4V to +6V

Available Signals Tx, Rx, GND

RS/EIA/TIA-423 is a standard for serial communications. It defines an unbalanced (single-ended)

interface (similar to RS-232), with a single, unidirectional sending driver, and allows for up to 10
receivers (similar to RS-422). It is normally implemented in integrated circuit technology and can
also be employed for the interchange of serial binary signals between DTE & DCE. There is no
common pinout for RS-423. The BBC Micro computer used a 5-pin DIN connector. DEC used it
extensively with a Modified Modular Jack connector. This was sometimes called "DEC-423".
Use of a common ground is one weakness of RS-423 (and RS-232): if devices are far enough
apart or on separate power systems, the ground will degrade between them and communications
will fail, resulting in a condition that is difficult to trace. In this respect the balanced serial
connections USB, RS-422 and RS-485 are better,[1] and Ethernet over twisted pair connections
are better yet, because of the galvanic isolation provided by the signal transformers.

References
1. Jump up^ National Semiconductor Application Note AN-1031 "TIA/EIA-422-B Overview", January
2000, National Semiconductor Inc. page 2 - evaluate the combination of cable length and data
rate

It is similar to TIA/EIA-232-F, but features a reduced driver output swing

and higher data rates.
RS-423 is an electrical standard, specifying driver and receiver requirements
only - there is no common pinout for this interface. Unbalanced driver and a
balanced receiver defined. The receivers? requirements are identical to specified
in TIA/ EIA-422-B standard. TIA/EIA-423-B is intended to be referenced by
complete standards, such as TIA/EIA-530-A. TIA/ EIA-423-B specifies a
unidirectional, multidrop (up to ten receivers) interface. Advantages over TIA/EIA-
232-F include: multiple receiver operation, faster data rates, and common power
supplies (typically ?5V).
 SPECIFICATIONS RS423 RS422
SINGLE - DIFFERENTIA
Mode of Operation
ENDED L
Total Number of Drivers and 1 DRIVER 1 DRIVER
Receivers on One Line 10 RECVR 10 RECVR
Maximum Cable Length 4000 FT. 4000 FT.
Maximum Data Rate 100kb/s 10Mb/s
-0.25V to
Maximum Driver Output Voltage +/-6V
+6V
Driver Output Signal Level
Loaded +/-3.6V +/-2.0V
(Loaded Min.)
Driver Output Signal Level Unloade
+/-6V +/-6V
(Unloaded Max) d
Driver Load Impedance (Ohms) >450 100
Max. Driver Current in High Power
N/A N/A
Z State On
Max. Driver Current in High Power
+/-100uA +/-100uA
Z State Off
Slew Rate (Max.) Adjustable N/A
-10V to
Receiver Input Voltage Range +/-12V
+10V
Receiver Input Sensitivity +/-200mV +/-200mV
Receiver Input Resistance (Ohms) 4k min. 4k min.

I²C

I²C
 Type Bus

Production history

Designer Philips Semiconductor, known today as NXP

Semiconductors

Designed 1982; 33 years ago

Data

Data signal Open-Drain

Width 1 bit (SDA) + clock (SCL)

Bitrate 0.1 / 0.4 / 1.0 / 3.4 / 5.0 Mbit/s

(depending on mode)

Protocol Serial, Half Duplex

I²C (Inter-Integrated Circuit), pronounced I-squared-C, is a multi-master, multi-slave, single-

ended, serial computer bus invented by Philips Semiconductor (now NXP Semiconductors). It is
typically used for attaching lower-speed peripheral ICs to processors andmicrocontrollers.
Alternatively I²C is spelled I2C (pronounced I-two-C) or IIC (pronounced I-I-C).
Since October 10, 2006, no licensing fees are required to implement the I²C protocol. However,
fees are still required to obtain I²C slave addresses allocated by NXP. [1]
Several competitors, such as Siemens AG (later Infineon Technologies AG, now Intel mobile
communications), NEC, Texas Instruments, STMicroelectronics (formerly SGS-Thomson),
Motorola (later Freescale), and Intersil, have introduced compatible I²C products to the market
since the mid-1990s.
SMBus, defined by Intel in 1995, is a subset of I²C that defines the protocols more strictly. One
purpose of SMBus is to promote robustness and interoperability. Accordingly, modern I²C
systems incorporate policies and rules from SMBus, sometimes supporting both I²C and SMBus,
requiring only minimal reconfiguration.

Contents

 1 Revisions
 2 Design
o 2.1 Reference design
o 2.2 Message protocols
o 2.3 Messaging example: 24c32 EEPROM
o 2.4 Physical layer
 2.4.1 Clock stretching using SCL
 2.4.2 Arbitration using SDA
  2.4.3 Arbitration in SMBus
o 2.5 Circuit interconnections
o 2.6 Buffering and multiplexing
o 2.7 Timing diagram
o 2.8 Example of bit-banging the I²C Master protocol
 3 Applications
 4 Operating system support
 5 Development tools
o 5.1 I²C host adapters
o 5.2 I²C protocol analyzers
o 5.3 Logic analyzers
 6 Limitations
 7 Derivative technologies
 8 See also
 9 References
 10 Further reading
 11 External links
o 11.1 Official
o 11.2 Other

Revisions
 In 1982, the original 100-kHz I²C system was created as a simple internal bus system for
building control electronics with various Philips chips.
 In 1992, Version 1 added 400-kHz Fast-mode (Fm) and a 10-bit addressing mode to
increase capacity to 1008 nodes. This was the first standardized version.
 In 1998, Version 2 added 3.4-MHz High-speed mode (Hs) with power-saving requirements
for electric voltage and current.
 In 2000, Version 2.1 introduced a minor cleanup of version 2.
 In 2007, Version 3 added 1-MHz Fast-mode plus (Fm+), and a device ID mechanism.
 In 2012, Version 4 added 5-MHz Ultra Fast-mode (UFm) for new USDA and USCL lines
using push-pull logic without pull-up resistors, and added assigned manufacturer ID table.
 In 2012, Version 5 corrected mistakes.
 In 2014, Version 6 corrected two graphs. This is the most recent standard. [2]

Design

A sample schematic with one master (a microcontroller), three slave nodes (an ADC, a DAC, and a
microcontroller), andpull-up resistors Rp

I²C uses only two bidirectional open-drain lines, Serial Data Line (SDA) and Serial Clock Line
(SCL), pulled up withresistors. Typical voltages used are +5 V or +3.3 V although systems with
other voltages are permitted.
The I²C reference design has a 7-bit or a 10-bit (depending on the device used) address space.
[3]
Common I²C bus speeds are the 100 kbit/s standard mode and the 10 kbit/s low-speed mode,
but arbitrarily low clock frequencies are also allowed. Recent revisions of I²C can host more
nodes and run at faster speeds (400 kbit/s Fast mode, 1 Mbit/sFast mode plus or Fm+, and
3.4 Mbit/s High Speed mode). These speeds are more widely used on embedded systems than
on PCs. There are also other features, such as 16-bit addressing.
Note the bit rates are quoted for the transactions between master and slave without clock
stretching or other hardware overhead. Protocol overheads include a slave address and perhaps
a register address within the slave device as well as per-byte ACK/NACK bits. Thus the actual
transfer rate of user data is lower than those peak bit rates alone would imply. For example, if
each interaction with a slave inefficiently allows only 1 byte of data to be transferred, the data
rate will be less than half the peak bit rate.
The maximum number of nodes is limited by the address space, and also by the total
bus capacitance of 400 pF, which restricts practical communication distances to a few meters.
Reference design
The before mentioned reference design is a bus with a clock (SCL) and data (SDA) lines with 7-
bit addressing. The bus has two roles for nodes: master and slave:

 Master node — node that generates the clock and initiates communication with slaves
 Slave node — node that receives the clock and responds when addressed by the master
The bus is a multi-master bus which means any number of master nodes can be present.
Additionally, master and slave roles may be changed between messages (after a STOP is sent).
There may be four potential modes of operation for a given bus device, although most devices
only use a single role and its two modes:

 master transmit — master node is sending data to a slave

 master receive — master node is receiving data from a slave
 slave transmit — slave node is sending data to the master
 slave receive — slave node is receiving data from the master
The master is initially in master transmit mode by sending a start bit followed by the 7-bit address
of the slave it wishes to communicate with, which is finally followed by a single bit representing
whether it wishes to write(0) to or read(1) from the slave.
If the slave exists on the bus then it will respond with an ACK bit (active low for acknowledged)
for that address. The master then continues in either transmit or receive mode (according to the
read/write bit it sent), and the slave continues in its complementary mode (receive or transmit,
respectively).
The address and the data bytes are sent most significant bit first. The start bit is indicated by a
high-to-low transition of SDA with SCL high; the stop bit is indicated by a low-to-high transition of
SDA with SCL high. All other transitions of SDA take place with SCL low.
If the master wishes to write to the slave then it repeatedly sends a byte with the slave sending
an ACK bit. (In this situation, the master is in master transmit mode and the slave is in slave
receive mode.)
If the master wishes to read from the slave then it repeatedly receives a byte from the slave, the
master sending an ACK bit after every byte but the last one. (In this situation, the master is in
master receive mode and the slave is in slave transmit mode.)
The master then either ends transmission with a stop bit, or it may send another START bit if it
wishes to retain control of the bus for another transfer (a "combined message").
Message protocols
I²C defines basic types of messages, each of which begins with a START and ends with a STOP:

 Single message where a master writes data to a slave;

 Single message where a master reads data from a slave;
 Combined messages, where a master issues at least two reads and/or writes to one or more
slaves.
In a combined message, each read or write begins with a START and the slave address. After
the first START in a combined message these are also called repeated STARTbits. Repeated
START bits are not preceded by STOP bits, which is how slaves know the next transfer is part of
the same message.
Any given slave will only respond to certain messages, as specified in its product documentation.
Pure I²C systems support arbitrary message structures. SMBus is restricted to nine of those
structures, such as read word N and write word N, involving a single slave. PMBusextends
SMBus with a Group protocol, allowing multiple such SMBus transactions to be sent in one
combined message. The terminating STOP indicates when those grouped actions should take
effect. For example, one PMBus operation might reconfigure three power supplies (using three
different I2C slave addresses), and their new configurations would take effect at the same time:
when they receive that STOP.
With only a few exceptions, neither I²C nor SMBus define message semantics, such as the
meaning of data bytes in messages. Message semantics are otherwise product-specific. Those
exceptions include messages addressed to the I²C general call address (0x00) or to the
SMBus Alert Response Address; and messages involved in the SMBusAddress Resolution
Protocol (ARP) for dynamic address allocation and management.
In practice, most slaves adopt request/response control models, where one or more bytes
following a write command are treated as a command or address. Those bytes determine how
subsequent written bytes are treated and/or how the slave responds on subsequent reads. Most
SMBus operations involve single byte commands.
Messaging example: 24c32 EEPROM
One specific example is the 24c32 type EEPROM, which uses two request bytes that are called
Address High and Address Low. (Accordingly, these EEPROMs are not usable by pure SMBus
hosts, which only support single byte commands or addresses.) These bytes are used to address
bytes within the 32 kbit (4 kB) supported by that EEPROM; the same two byte addressing is also
used by larger EEPROMs, such as 24c512 ones storing 512 kbits (64 kB). Writing and reading
data to these EEPROMs uses a simple protocol: the address is written, and then data is
transferred until the end of the message. (That data transfer part of the protocol also makes
trouble for SMBus, since the data bytes are not preceded by a count and more than 32 bytes can
be transferred at once. I²C EEPROMs smaller than 32 kbits, such as 2 kbit 24c02 ones, are often
used on SMBus with inefficient single byte data transfers.)
A single message writes to the EEPROM. After the START, the master sends the chip's bus
address with the direction bit clear (write), then sends the two byte address of data within the
EEPROM and then sends data bytes to be written starting at that address, followed by a STOP.
When writing multiple bytes, all the bytes must be in the same 32 byte page. While it is busy
saving those bytes to memory, the EEPROM will not respond to further I²C requests. (That is
another incompatibility with SMBus: SMBus devices must always respond to their bus
addresses.)
To read starting at a particular address in the EEPROM, a combined message is used. After a
START, the master first writes that chip's bus address with the direction bit clear (write) and then
the two bytes of EEPROM data address. It then sends a (repeated) START and the EEPROM's
bus address with the direction bit set (read). The EEPROM will then respond with the data bytes
beginning at the specified EEPROM data address -— a combined message, first a write then a
read. The master issues an ACK after each read byte except the last byte, and then issues a
STOP. The EEPROM increments the address after each data byte transferred; multi-byte reads
can retrieve the entire contents of the EEPROM using one combined message.

Physical layer
At the physical layer, both SCL and SDA lines are of open-drain design, thus, pull-up
resistors are needed. Pulling the line to ground is considered a logical zero while letting the line
float is a logical one. This is used as a channel access method. High speed systems (and some
others) also add a current source pull up, at least on SCL; this accommodates higher bus
capacitance and enables faster rise times.
An important consequence of this is that multiple nodes may be driving the lines simultaneously.
If any node is driving the line low, it will be low. Nodes that are trying to transmit a logical one (i.e.
letting the line float high) can see this, and thereby know that another node is active at the same
time.
When used on SCL, this is called clock stretching and gives slaves a flow control mechanism.
When used on SDA, this is called arbitration and ensures there is only one transmitter at a time.
When idle, both lines are high. To start a transaction, SDA is pulled low while SCL remains high.
Releasing SDA to float high again would be a stop marker, signaling the end of a bus
transaction. Although legal, this is typically pointless immediately after a start, so the next step is
to pull SCL low.
Except for the start and stop signals, the SDA line only changes while the clock is low;
transmitting a data bit consists of pulsing the clock line high while holding the data line steady at
the desired level.
While SCL is low, the transmitter (initially the master) sets SDA to the desired value and (after a
small delay to let the value propagate) lets SCL float high. The master then waits for SCL to
actually go high; this will be delayed by the finite rise-time of the SCL signal (the RC time
constant of the pull-up resistor and the parasitic capacitance of the bus), and may be additionally
delayed by a slave's clock stretching.
Once SCL is high, the master waits a minimum time (4 μs for standard speed I²C) to ensure the
receiver has seen the bit, then pulls it low again. This completes transmission of one bit.
After every 8 data bits in one direction, an "acknowledge" bit is transmitted in the other direction.
The transmitter and receiver switch roles for one bit and the erstwhile receiver transmits a single
0 bit (ACK) back. If the transmitter sees a 1 bit (NACK) instead, it learns that:

 (If master transmitting to slave) The slave is unable to accept the data. No such slave,
command not understood, or unable to accept any more data.
 (If slave transmitting to master) The master wishes the transfer to stop after this data byte.
During the acknowledgment, SCL is always controlled by the master.
After the acknowledge bit, the master may do one of three things:

 Prepare to transfer another byte of data: the transmitter set SDA, and the master pulses SCL
high.
 Send a "Stop": Set SDA low, let SCL go high, then let SDA go high. This releases the I²C
bus.
 Send a "Repeated start": Set SDA high, let SCL go high, and pull SDA low again. This starts
a new I²C bus transaction without releasing the bus.
Clock stretching using SCL
One of the more significant features of the I²C protocol is clock stretching. An addressed slave
device may hold the clock line (SCL) low after receiving (or sending) a byte, indicating that it is
not yet ready to process more data. The master that is communicating with the slave may not
finish the transmission of the current bit, but must wait until the clock line actually goes high. If
the slave is clock stretching, the clock line will still be low (because the connections are open-
drain). The same is true if a second, slower, master tries to drive the clock at the same time. (If
there is more than one master, all but one of them will normally lose arbitration.)
The master must wait until it observes the clock line going high, and an additional minimum time
(4 μs for standard 100 kbit/s I²C) before pulling the clock low again.
Although the master may also hold the SCL line low for as long as it desires, the term "clock
stretching" is normally used only when slaves do it. Although in theory any clock pulse may be
stretched, generally it is the intervals before or after the acknowledgment bit which are used. For
example, if the slave is a microcontroller, its I²C interface could stretch the clock after each byte,
until the software decides whether to send a positive acknowledgment or a NACK.
Clock stretching is the only time in I²C where the slave drives SCL. Many slaves do not need to
clock stretch and thus treat SCL as strictly an input with no circuitry to drive it. Some masters,
such as those found inside custom ASICs may not support clock stretching; often these devices
will be labeled as a "two-wire interface" and not I²C.
To ensure a minimum bus throughput, SMBus places limits on how far clocks may be stretched.
Hosts and slaves adhering to those limits cannot block access to the bus for more than a short
time, which is not a guarantee made by pure I²C systems.
Arbitration using SDA
Every master monitors the bus for start and stop bits, and does not start a message while
another master is keeping the bus busy. However, two masters may start transmission at about
the same time; in this case, arbitration occurs. Slave transmit mode can also be arbitrated, when
a master addresses multiple slaves, but this is less common. In contrast to protocols (such
as Ethernet) that use random back-off delays before issuing a retry, I²C has a deterministic
arbitration policy. Each transmitter checks the level of the data line (SDA) and compares it with
the levels it expects; if they do not match, that transmitter has lost arbitration, and drops out of
this protocol interaction.
If one transmitter sets SDA to 1 (not driving a signal) and a second transmitter sets it to 0 (pull to
ground), the result is that the line is low. The first transmitter then observes that the level of the
line is different from that expected, and concludes that another node is transmitting. The first
node to notice such a difference is the one that loses arbitration: it stops driving SDA. If it's a
master, it also stops driving SCL and waits for a STOP; then it may try to reissue its entire
message. In the meantime, the other node has not noticed any difference between the expected
and actual levels on SDA, and therefore continues transmission. It can do so without problems
because so far the signal has been exactly as it expected; no other transmitter has disturbed its
message.
If the two masters are sending a message to two different slaves, the one sending the lower
slave address always "wins" arbitration in the address stage. Since the two masters may send
messages to the same slave address—and addresses sometimes refer to multiple slaves—
arbitration must continue into the data stages.
Arbitration occurs very rarely, but is necessary for proper multi-master support. As with clock-
stretching, not all devices support arbitration. Those that do generally label themselves as
supporting "multi-master" communication.
In the extremely rare case that two masters simultaneously send identical messages, both will
regard the communication as successful, but the slave will only see one message. Slaves that
can be accessed by multiple masters must have commands that are idempotent for this reason.
Arbitration in SMBus
While I²C only arbitrates between masters, SMBus uses arbitration in three additional contexts,
where multiple slaves respond to the master, and one gets its message through.

 Although conceptually a single-master bus, a slave device that supports the "host notify
protocol" acts as a master to perform the notification. It seizes the bus and writes a 3-byte
message to the reserved "SMBus Host" address (0x08), passing its address and two bytes
of data. When two slaves try to notify the host at the same time, one of them will lose
arbitration and need to retry.
 An alternative slave notification system uses the separate SMBALERT# signal to request
attention. In this case, the host performs a 1-byte read from the reserved "SMBus Alert
Response Address" (0x0c), which is a kind of broadcast address. All alerting slaves respond
 with a data bytes containing their own address. When the slave successfully transmits its
own address (winning arbitration against others) it stops raising that interrupt. In both this
and the preceding case, arbitration ensures that one slave's message will be received, and
the others will know they must retry.
 SMBus also supports an "address resolution protocol", wherein devices return a 16-byte
"universal device ID" (UDID). Multiple devices may respond; the one with the least UDID will
win arbitration and be recognized.
Circuit interconnections
I²C is popular for interfacing peripheral circuits to prototyping systems, such as
the Arduino and Raspberry Pi. I²C does not employ a standardized connector, however, and
board designers have created various wiring schemes for I²C interconnections. To minimize the
possible damage due to plugging 0.1-inch headers in backwards, some developers have
suggested using alternating signal and power connections of the following wiring schemes:
(GND, SCL, VCC, SDA) or (VCC, SDA, GND, SCL).[4]
Buffering and multiplexing
When there are many I²C devices in a system, there can be a need to include
bus buffers or multiplexers to split large bus segments into smaller ones. This can be necessary
to keep the capacitance of a bus segment below the allowable value or to allow multiple devices
with the same address to be separated by a multiplexer. Many types of multiplexers and buffers
exist and all must take into account the fact that I²C lines are specified to be bidirectional.
Multiplexers can be implemented with analog switches which can tie one segment to another.
Analog switches maintain the bidirectional nature of the lines but do not isolate the capacitance
of one segment from another or provide buffering capability.
Buffers can be used to isolate capacitance on one segment from another and/or allow I²C to be
sent over longer cables or traces. Buffers for bi-directional lines such as I²C must use one of
several schemes for preventing latch-up. I²C is open-drain so buffers must drive a low on one
side when they see a low on the other. One method for preventing latch-up is for a buffer to have
carefully selected input and output levels such that the output level of its driver is higher than its
input threshold, preventing it from triggering itself. For example, a buffer may have an input
threshold of 0.4 V for detecting a low, but an output low level of 0.5 V. This method requires that
all other devices on the bus have thresholds which are compatible and often means that multiple
buffers implementing this scheme cannot be put in series with one another.
Alternatively, other types of buffers exist that implement current amplifiers, or keep track of the
state (i.e. which side drove the bus low) to prevent latch-up. The state method typically means
that an unintended pulse is created during a hand-off when one side is driving the bus low, then
the other drives it low, then the first side releases (this is common during an I²C
acknowledgement).
Timing diagram

1. Data Transfer is initiated with a START bit (S) signaled by SDA being pulled low while
SCL stays high.
2. SDA sets the 1st data bit level while keeping SCL low (during blue bar time.)
3. The data is sampled (received) when SCL rises (green) for the first bit (B1).
4. This process repeats, SDA transitioning while SCL is low, and the data being read while
SCL is high (B2, Bn).
5. A STOP bit (P) is signaled when SDA is pulled high while SCL is high.
In order to avoid false marker detection, SDA is changed on the SCL falling edge and is sampled
and captured on the rising edge of SCL.
Example of bit-banging the I²C Master protocol
Below is an example of bit-banging the I²C protocol as an I²C master. The example is written
in pseudo C. It illustrates all of the I²C features described before (clock stretching, arbitration,
start/stop bit, ack/nack)

// Hardware-specific support functions that MUST be customized:

#define I2CSPEED 100
void I2C_delay(void) { volatile int v; int i; for (i=0; i < I2CSPEED/2; i+
+) v; }
bool read_SCL(void); // Set SCL as input and return current level of line,
0 or 1
bool read_SDA(void); // Set SDA as input and return current level of line,
0 or 1
void clear_SCL(void); // Actively drive SCL signal low
void clear_SDA(void); // Actively drive SDA signal low
void arbitration_lost(void);

bool started = false; // global data

void i2c_start_cond(void) {
if (started) { // if started, do a restart cond
// set SDA to 1
read_SDA();
I2C_delay();
while (read_SCL() == 0) { // Clock stretching
// You should add timeout to this loop
}
// Repeated start setup time, minimum 4.7us
I2C_delay();
}
if (read_SDA() == 0) {
arbitration_lost();
}
// SCL is high, set SDA from 1 to 0.
clear_SDA();
I2C_delay();
clear_SCL();
started = true;
}

void i2c_stop_cond(void){
// set SDA to 0
clear_SDA();
 I2C_delay();
// Clock stretching
while (read_SCL() == 0) {
// add timeout to this loop.
}
// Stop bit setup time, minimum 4us
I2C_delay();
// SCL is high, set SDA from 0 to 1
if (read_SDA() == 0) {
arbitration_lost();
}
I2C_delay();
started = false;
}

// Write a bit to I2C bus

void i2c_write_bit(bool bit) {
if (bit) {
read_SDA();
} else {
clear_SDA();
}
I2C_delay();
while (read_SCL() == 0) { // Clock stretching
// You should add timeout to this loop
}
// SCL is high, now data is valid
// If SDA is high, check that nobody else is driving SDA
if (bit && read_SDA() == 0) {
arbitration_lost();
}
I2C_delay();
clear_SCL();
}

// Read a bit from I2C bus

bool i2c_read_bit(void) {
bool bit;
// Let the slave drive data
read_SDA();
I2C_delay();
while (read_SCL() == 0) { // Clock stretching
// You should add timeout to this loop
 }
// SCL is high, now data is valid
bit = read_SDA();
I2C_delay();
clear_SCL();
return bit;
}

// Write a byte to I2C bus. Return 0 if ack by the slave.

bool i2c_write_byte(bool send_start,
bool send_stop,
unsigned char byte) {
unsigned bit;
bool nack;
if (send_start) {
i2c_start_cond();
}
for (bit = 0; bit < 8; bit++) {
i2c_write_bit((byte & 0x80) != 0);
byte <<= 1;
}
nack = i2c_read_bit();
if (send_stop) {
i2c_stop_cond();
}
return nack;
}

// Read a byte from I2C bus

unsigned char i2c_read_byte(bool nack, bool send_stop) {
unsigned char byte = 0;
unsigned bit;
for (bit = 0; bit < 8; bit++) {
byte = (byte << 1) | i2c_read_bit();
}
i2c_write_bit(nack);
if (send_stop) {
i2c_stop_cond();
}
return byte;
}

Applications
I²C is appropriate for peripherals where simplicity and low manufacturing cost are more important
than speed. Common applications of the I²C bus are:

 Reading configuration data from SPD EEPROMs on SDRAM, DDR SDRAM, DDR2
SDRAM memory sticks (DIMM) and other stacked PC boards
 Supporting systems management for PCI cards, through an SMBus 2.0 connection.
 Accessing NVRAM chips that keep user settings.
 Accessing low speed DACs and ADCs.
 Changing contrast, hue, and color balance settings in monitors (Display Data Channel).
 Changing sound volume in intelligent speakers.
 Controlling OLED/LCD displays, like in a cellphone.
 Reading hardware monitors and diagnostic sensors, like a CPU thermistor [citation needed] or fan
speed.[5]
 Reading real-time clocks.
 Turning on and turning off the power supply of system components.
A particular strength of I²C is the capability of a microcontroller to control a network of device
chips with just two general purpose I/O pins and software. Many other bus technologies used in
similar applications, such as Serial Peripheral Interface Bus, require more pins and signals to
connect devices.

Operating system support

 In AmigaOS one can use the i2c.resource component [6] for AmigaOS 4.x or the shared
library i2c.library by Wilhelm Noeker for older systems.
 Arduino developers can use the 'Wire' library.
 Maximite supports I²C communications natively as part of its MMBasic.
 PICAXE uses the i2c and hi2c commands
 eCos supports I²C for several hardware architectures.
 ChibiOS/RT supports I²C for several hardware architectures.
 FreeBSD, NetBSD and OpenBSD also provide an I²C framework, with support for a number
of common master controllers and sensors.
 In Linux, I²C is handled with a device driver for the specific device, and another for the I²C
(or SMBus) adapter to which it is connected. Several hundred such drivers are part of current
releases.
 In Mac OS X, there are about two dozen I²C kernel extensions which communicate with
sensors for reading voltage, current, temperature, motion, and other physical status.
 In Microsoft Windows, I²C is implemented by the respective device drivers of much of the
industry's available hardware.
 Unison OS a POSIX RTOS for IoT supports I²C for several MCU and MPU hardware
architectures.
 In Windows CE, I²C is implemented by the respective device drivers of much of the industry's
available hardware.
 In RISC OS, I²C is provided with a generic I²C interface from the IO-controller and supported
from the OS module system
 In Sinclair QDOS and Minerva QL operating systems I²C is supported via a set of extensions
provided by TF Services.

Development tools
When developing or troubleshooting systems using I²C, visibility at the level of hardware signals
can be important.
I²C host adapters
There are a number of hardware solutions for host computers, running Linux, Mac or Windows,
I²C master and/or slave capabilities. Most of them are based on Universal Serial Bus (USB) to
I²C adapters. Not all of them require proprietary drivers or APIs.
I²C protocol analyzers
I²C Protocol Analyzers are tools which sample an I²C bus and decode the electrical signals to
provide a higher-level view of the data being transmitted on the bus.
Logic analyzers
When developing and/or troubleshooting the I²C bus, examination of hardware signals can be
very important. Logic analyzers are tools which collect, analyze, decode, and store signals so
people can view the high-speed waveforms at their leisure. Logic analyzers display time-stamps
of each signal level change, which can help find protocol problems. Most logic analyzers have
the capability to decode bus signals into high-level protocol data and show ASCII data.

Limitations
The assignment of slave addresses is one weakness of I²C. Seven bits is too few to prevent
address collisions between the many thousands of available devices, and manufacturers rarely
dedicate enough pins to configure the full slave address used on a given board. Three pins is
typical, giving only eight choices of slave address. While some devices can set multiple address
bits per pin,[7][8] e.g., by using a spare internal ADC channel to sense one of eight ranges set by
an external voltage divider, usually each pin controls one address bit. Manufacturers may provide
pins to configure a few low order bits of the address and arbitrarily set the higher order bits to
some value based on the model. This limits the number of devices of that model which may be
present on the same bus to some low number, typically between two and eight. That partially
addresses the issue of address collisions between different vendors. Ten-bit I²C addresses are
not yet widely used, and many host operating systems do not support them. [9] Neither is the
complex SMBus "ARP" scheme for dynamically assigning addresses (other than for PCI cards
with SMBus presence, for which it is required).
Automatic bus configuration is a related issue. A given address may be used by a number of
different protocol-incompatible devices in various systems, and hardly any device types can be
detected at runtime. For example, 0x51 may be used by a 24LC02 or 24C32 EEPROM, with
incompatible addressing; or by a PCF8563 RTC, which cannot reliably be distinguished from
either (without changing device state, which might not be allowed). The only reliable
configuration mechanisms available to hosts involve out-of-band mechanisms such as tables
provided by system firmware which list the available devices. Again, this issue can partially be
addressed by ARP in SMBus systems, especially when vendor and product identifiers are used;
but that has not really caught on. The rev. 03 version of the I²C specification adds a device ID
mechanism.
I²C supports a limited range of speeds. Hosts supporting the multi-megabit speeds are rare.
Support for the Fm+ one-megabit speed is more widespread, since its electronics are simple
variants of what is used at lower speeds. Many devices do not support the 400 kbit/s speed (in
part because SMBus does not yet support it). I²C nodes implemented in software (instead of
dedicated hardware) may not even support the 100 kbit/s speed; so the whole range defined in
the specification is rarely usable. All devices must at least partially support the highest speed
used or they may spuriously detect their device address.
Devices are allowed to stretch clock cycles to suit their particular needs, which can starve
bandwidth needed by faster devices and increase latencies when talking to other device
addresses. Bus capacitance also places a limit on the transfer speed, especially when current
sources are not used to decrease signal rise times.
Because I²C is a shared bus, there is the potential for any device to have a fault and hang the
entire bus. For example, if any device holds the SDA or SCL line low it prevents the master from
sending START or STOP commands to reset the bus. Thus it is common for designs to include a
reset signal that provides an external method of resetting the bus devices. However many
devices do not have a dedicated reset pin forcing the designer to put in circuitry to allow devices
to be power cycled if they need to be reset.
Because of these limits (address management, bus configuration, potential faults, speed), few
I²C bus segments have even a dozen devices. It is common for systems to have several such
segments. One might be dedicated to use with high speed devices, for low latency power
management. Another might be used to control a few devices where latency and throughput are
not important issues; yet another segment might be used only to read EEPROM chips describing
add-on cards (such as the SPD standard used with DRAM sticks).

Derivative technologies
I²C is the basis for the ACCESS.bus, the VESA Display Data Channel (DDC) interface,
the System Management Bus (SMBus), Power Management Bus (PMBus) and the Intelligent
Platform Management Bus (IPMB, one of the protocols of IPMI). These variants have differences
in voltage and clock frequency ranges, and may have interrupt lines.
High availability systems (AdvancedTCA, MicroTCA) use 2-way redundant I²C for shelf
management. Multi-master I²C capability is a requirement in these systems.
TWI (Two Wire Interface) or TWSI (Two-Wire Serial Interface) is essentially the same bus
implemented on various system-on-chip processors from Atmel and other vendors.[10]Vendors use
the name TWI, even though I²C is not a registered trademark. Trademark protection only exists
for the respective logo (See upper right corner) and patents on I²C have now lapsed.
In some cases, use of the term "two-wire interface" indicates incomplete implementation of the
I²C specification. Not supporting arbitration or clock stretching is one common limitation, that is
still useful for a single master communicating with simple slaves that never stretch the clock.

References
1. Jump up^ I²C Licensing Information