Serial Peripheral Interface

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1. Serial Peripheral Interface (SPI) Overview
• SPI is a standard bus for high speed communication over short distances and it is
incorporated into some devices such as some ADC, DAC, and EEPROM
• SPI uses a master-slave architecture, with one master
• Multiple slave devices may be supported through selection with individual chip
select or slave select
• SPI uses four pins:
o Two data transfer pins (data-in and data-out pins instead of eight or more in
traditional buses) reducing package size and power consumption
o A clock-shift pin to synchronise data transfer between two chips
o A chip-enable pin to initiate and terminate the data transfer
• These four pins named: Serial Data Input (SDI) or Master Out Slave In (MOSI);
Serial Data Output (SDO) or Master In Slave Out (MISO); Serial Clock (SCLK) or
(SCK); Chip Enable (CE) or Slave Select (SS – active low)

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• A single master to single slave (basic SPI) connection is shown below:

• MOSI on a master connects to MOSI on a slave and MISO on master connects to

MISO on a slave
• The clock signal is provided by the master to control when data can change and
when it is valid for reading (no data can be transferred unless a clock signal is
present)
• SPI allows bidirectional data exchange (no device can be transmitter only or
receiver only) and data can be clocked into and out of a device at the same time
• Data is output at the rising or falling edge of SCK
• The opposite edge is used to ensure data is valid at the time of reading
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2. SPI Programming in ATmega328P
• The SPI data transfer can be between the ATmega328P and peripheral devices or
between several AVR devices
• The ATmega328P has an SPI module as shown in the next slide or the USART can
be used in SPI mode

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• The interconnection between Master and Slave CPUs with SPI is shown below:

• The SPI Master initiates a communication cycle by pulling low the SS pin of the
desired Slave
• The Master and Slave prepare data to be sent in their respective shift Registers,
and the Master generates the required clock pulses on the SCK line to
interchange data
• Data is always shifted from Master to Slave on MOSI line and from Slave to
Master on MISO line
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• After each data packet, the Master will synchronize the Slave by pulling high the
Slave Select, SS, line
• When configured as a Master, the SPI interface has no automatic control of the
SS line but this is handled by user software before communication can start
• When this is done, writing a byte to the SPI Data Register (SPDR) starts the SPI
clock generator, and the hardware shifts the eight bits into the Slave
• After shifting one byte, the SPI clock generator stops, setting the end of
Transmission Flag (SPIF)
• If the SPI Interrupt Enable bit (SPIE) in the SPI Control Register (SPCR) is set, an
interrupt is requested
• The Master signals the end of packet by pulling high the Slave Select, SS line
• When configured as a Slave, the SPI interface will remain sleeping as long as the
SS pin is driven high
• In this state, software may update the contents of the SPI Data Register, SPDR,
but the data will not be shifted out by incoming clock pulses on the SCK pin until
the SS pin is driven low
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• As one byte has been completely shifted, the end of Transmission Flag, SPIF is set
• If the SPI Interrupt Enable bit, SPIE, in the SPCR Register is set, an interrupt is
requested
• The Slave may continue to place new data to be sent into SPDR before reading
• the incoming data. The last incoming byte will be kept in the Buffer Register for
later use

Data Modes
• There are four combinations of SCK phase and polarity with respect to serial data,
which are determined by control bits Clock Phase (CPHA) and Clock Polarity
(CPOL)
• The SPI data transfer formats are shown in the table in the next slide

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• The data bits are shifted out and latched in on opposite edges of the SCK signal as
shown in the next two slides

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10
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SPI Registers

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16
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 Steps for reading data from an SPI device
• In reading SPI devices, there are two modes: single-byte and multi-byte
Single-byte read
• The following steps are used to get (read) data in single-byte mode from an SPI
device:
1. Make SS = 0 to begin reading
2. The 8-bit address is shifted in one bit at a time with every edge of SCK
3. After all 8-bits of the address are read in, the SPI device sends out data
belonging to that location
4. The 8-bits data is shifted out one bit at a time with every edge of the SCK
5. Make SS = 1 to indicate end of read cycle

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 Multi-byte read
• The burst mode is for bringing out the contents of consecutive locations
• The address of the first location only is provided
• From there on, while SS = 0, consecutive bytes are brought out from consecutive
locations
• The SPI internally increments the address location as long as SS is LOW
• The following steps are used to read multiple bytes of data in burst mode:
1. Make SS = 0 to begin reading
2. The 8-bit address of the first location provided and shifted in one bit at a time
with every edge of SCK
3. The 8-bit data of the first location is shifted out, one bit at a time with every
edge of the SCK and, from there on, consecutive bytes of data from consecutive
locations are obtained as long as SS remains LOW
4. Make SS = 1 to indicate end of reading
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Example 1
Write a program to initialise the SPI for master mode, with SCK frequency of
Fosc/16 and transmit ‘G’ via SPI repeatedly. The received data should be displayed
on PORT D.
Solution:
#include <avr/io.h>
int main()
{
DDRB = (1 << MOSI) | (1 << SCK) | (1 << SS); //MOSI, SCK and SS output
DDRD = 0xFF; //PORTD is output
SPCR = (1 << SPE) | (1 << MSTR) | (1 << SPR0); //enable SPI, set Master, SCK = Fosc/16
while(1)
{
PORTB &= ~(1 << SS); // make SS LOW
SPDR = ‘G’; //transmit ‘G’
while( !(SPSR & (1 << SPIF))); //wait for transfer to finish
PORTD = SPDR; //move received data to PORTD
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 PORTB |= (1 <<SS); //disable slave device
}
return 0;
}

Example 2
Write a program to initialise the SPI for slave mode, with SCK frequency of Fosc/16
and transmit ‘G’ via SPI repeatedly. The received data should be displayed on PORT
D.

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#include <avr/io.h>
int main()
{
DDRB = (1 << MISO); //MISO output
DDRD = 0xFF; //PORTD is output
SPCR = (1 << SPE); //enable SPI
while(1)
{
SPDR = ‘G’; //transmit ‘G’
while( !(SPSR & (1 << SPIF))); //wait for transfer to finish
PORTD = SPDR; //move received data to PORTD
}
return 0;
}

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