FYUGP CURRICULAR FRAMEWORK FOR BACHELORS PROGRAMME WITH

APPLIED COMPUTING AS MINOR-2024

(OPTIONAL FOR STUDENTS WITH COMPUTER APPLICATION / INFORMATION TECHNOLOGY AS MAJOR)

CREDITS
COURSE TYPE OF
SEMESTER TITLE OF COURSE
CODE COURSE THEORY
PRACTICAL
/ TUTORIAL

APPLIED COMPUTING: DIGITAL

I ACP124N CT-1 4 2
ELECTRONICS

APPLIED COMPUTING: WEB

II ACP222N CT-1 4 2
DESIGNING

APPLIED COMPUTING:
III ACP323N CT-1 CRYPTOGRAPHY AND NETWORK 4 2
SECURITY

APPLIED COMPUTING: IOT

IV ACP422N CT-1 3 1
FUNDAMENTALS

APPLIED COMPUTING: THEORY

V ACP522N CT-1 3 1
OF COMPUTATION

APPLIED COMPUTING:
VI ACP622N CT-1 3 1
ARTIFICIAL INTELLIGENCE

APPLIED COMPUTING: DESIGN

VII ACP722N CT-1 3 1
AND ANALYSIS OF ALGORITHMS

APPLIED COMPUTING: CLOUD

VIII ACP822N CT-1 COMPUTING (HONOURS)/ LATEX 3 1
(RESEARCH)

HEAD OF THE DEPARTMENT / CONVENOR BOUGS

 BACHELORS WITH APPLIED COMPUTING AS MINOR
(FOR STUDENTS WITH MAJOR IN COMPUTER APPLICATIONS / INFORMATION TECHNOLOGY)
1st SEMESTER
ACP124N APPLIED COMPUTING _ DIGITAL ELECTRONICS
CREDITS: THEORY: 4; PRACTICAL: 2
COURSE LEARNING OUTCOMES:
• To introduce concepts of number systems and Boolean algebra.
• To familiarize students with the operation and use of basic digital logic gates as well as the design and
minimization of combinational logic circuits.
• To introduce the concept of microprocessors and familiarize them with basic operation of a CPU.
THEORY (4 CREDITS)
UNIT 1:
Introduction to Digital and Analog Quantities, Binary Digits, Logic Levels, Pulse, Waveforms, Clock and Timing
Diagrams (1 Hour)
Number Systems - Decimal, Binary, Octal, Hexadecimal and their Conversions. (4 Hours)
Unsigned Binary Arithmetic, Ones Complement, Twos Complement. Signed Numbers and their arithmetic. Binary Coded
Decimal. Error Codes-Parity Code (4 Hours)
Logic Gates—AND, OR, NOT, NAND, NOR, XOR and XNOR Gates. (2 Hours)
Boolean Algebra: Boolean Operations, Laws and Rules of Boolean Algebra, DeMorgan's Theorems. Constructing a
Boolean Expression for a Logic Circuit, Logic Simplification. (5 Hours)
UNIT 2:
SOP and POS forms, Karnaugh Maps and minimization upto 4 variables, Don't care conditions (4 Hours) Combinational
Logic Circuits: AND-OR, AND-OR-INVERT, XOR and XNOR logic, Converting Boolean Expression or Truth Table to
a Logic Circuit, NAND and NOR as Universal Gates (4 Hours)
Half Adder, Full Adder, 4-bit Parallel Binary Adder, Comparator, Binary Decoder, Encoder, Multiplexer, Demultiplexer
(7 Hours)
UNIT 3:
Latches: SR Latch, D Latch, Gated SR and D Latch (2 Hours) Flip Flops: Difference between Flip Flop and Latch, Level
vs Edge-Triggered. D Flip Flops, JK Flip Flops and their operation (4 Hours)
Characteristics and Applications of Flip Flops (storage, counting), Intro to 555 Timer (2 Hours)
Shift Registers - Serial and Parallel (4-bit) (3 Hours) Counters: Synchronous and Asynchronous (2/3 bit). Decade
Counter, Johnson counter (4 Hours)
UNIT 4:
von Neumann Architecture: Block Diagram, CPU, Memory, I/O Ports and Buses, Bus Master, Bus Contention: Shared
Signal Lines and Tri-State Outputs, Fan-out, Buffers, Device Selection, System Timing.
Microprocessor, ALU, Control/Timing Unit, Decode Unit, Register Set, Instruction Execution Cycle. Memory: Memory
Bus, Read / Write operations and Addressing Modes. I/O: Polling, Interrupts and DMA. Intro to Types of CPU
Instructions.
Microcontrollers: Architecture, Registers, Functional Units and Peripherals. System on Chip (SoC): Block Diagram,
Functional Elements, Difference between Microprocessor, Microcontroller and SoC. (15 Hours)
TEXTBOOK:
1. Thomas Floyd, Digital Fundamentals, 11th Edition (2015), Pearson.
REFERENCES:
1. Morris Mano, Michael Ciletti, Digital Design with an Introduction to the Verilog HDL, VHDL, and
SystemVerilog, 6th Edition, Pearson (2017)
2. Malvino, Principle of Digital Electronics, McGraw-Hill
3. R.P. Jain - Modern Digital Electronics, McGraw-Hill, 4th ed. 2010
4. LaMerez, Quick Start Guide to Verilog, Springer (2019)
5. M. Rafiquzzaman - Digital Logic, with an Introduction to Verilog and FPGA-Based Design, Wiley (2019)
PRACTICALS (2 CREDITS)

User a Verilog/System Verilog simulator like ModelSim or Icarus Verilog to simulate the following digital circuits:

1. Implement the following logic gates in Verilog:

a. A 2-input AND Gate
b. A 3-input OR Gate
2. Implement the following logic gates in Verilog and simulate them using a test bench:
a. A 2-input NAND Gate
b. A 2-input NOR Gate
3. Design and simulate 3-input XOR gate in Verilog.
4. Design and simulate a module in verilog that implements the following boolean logic: a.
5. Design and simulate a half adder in Verilog
6. Design and simulate a full adder in Verilog
7. Design and simulate a 4-bit binary adder in Verilog
8. Design and simulate a 2-to-1 multiplexer in Verilog
9. Design and simulate a 4-to-1 multiplexer assembled from three 2-to-1 multiplexers in Verilog
10. Design and simulate a 3-to-8 decoder in Verilog
11. Design and simulate a clocked D Flip Flop with reset input in Verilog
12. Design and simulate a simple 4-bit ALU in Verilog that performs addition, subtraction, AND, and OR
operations