Digital Logic Design

Chapter-4 & 5
 Combinational Circuits

 Output is function of input only

i.e. no feedback

Combinational
n inputs • • m outputs
•
• Circuits •
•


When input changes, output may change (after a delay)
 Combinational Circuits

 Analysis
● Given a circuit, find out its function ?

● Function may be expressed as: ?

♦ Boolean function
♦ Truth table

 Design
● Given a desired function, determine its circuit
● Function may be expressed as:
♦ Boolean function ?
♦ Truth table
 Analysis Procedure

 Boolean Expression Approach

T2=ABC
T1=A+B+C
T3=AB'C'+A'BC'+A'B'C

F’2=(A’+B’)(A’+C’)(B’+C’)

F2=AB+AC+BC

F1=AB'C'+A'BC'+A'B'C+ABC
F2=AB+AC+BC
 Analysis Procedure

 Truth Table Approach A B C F1 F2

=0 0
0 0 0 0 0
=0 0
=0
=0 0
=0 0
=0
1
=0 0
=0
=0 0 0
=0
=0 0
=0
 Analysis Procedure

 Truth Table Approach A B C F1 F2

=0 0
0 0 0 0 0
=0 1
0 0 1 1 0
=1
=0 1
=0 1
=1
1
=0 0
=0
=0 0 0
=1
=0 0
=1
 Analysis Procedure

 Truth Table Approach A B C F1 F2

=0 0
0 0 0 0 0
=1 1
0 0 1 1 0
=0
=0
0 1 0 1 0
1 1
=1
=0
1
=0 0
=1
=0 0 0
=0
=1 0
=0
 Analysis Procedure

 Truth Table Approach A B C F1 F2

=0 0
0 0 0 0 0
=1 0
0 0 1 1 0
=1
=0
0 1 0 1 0
1
=1 0 0 1 1 0 1
=1
0
=0 0
=1
=0 0 1
=1
=1 1
=1
 Analysis Procedure

 Truth Table Approach A B C F1 F2

=1 0
0 0 0 0 0
=0 1
0 0 1 1 0
=0
=1
0 1 0 1 0
1 1
=0 0 1 1 0 1
=0
1 1 0 0 1 0
=1 0
=0
=1 0 0
=0
=0 0
=0
 Analysis Procedure

 Truth Table Approach A B C F1 F2

=1 0
0 0 0 0 0
=0 0
0 0 1 1 0
=1
=1
0 1 0 1 0
1 0
=0 0 1 1 0 1
=1
0 1 0 0 1 0
=1 0
=0 1 0 1 0 1
=1 1 1
=1
=0 0
=1
 Analysis Procedure

 Truth Table Approach A B C F1 F2

=1 0
0 0 0 0 0
=1 0
0 0 1 1 0
=0
=1
0 1 0 1 0
1 0
=1 0 1 1 0 1
=0
0 1 0 0 1 0
=1 1
=1 1 0 1 0 1
=1
1 1 0 0 1
0 1
=0
=1 0
=0
 Analysis Procedure

 Truth Table Approach A B C F1 F2

=1 1
0 0 0 0 0
=1 1
0 0 1 1 0
=1
=1
0 1 0 1 0
1 0
=1 0 1 1 0 1
=1
0 1 0 0 1 0
=1 1
=1 1 0 1 0 1
=1
1 1 0 0 1
1 1
=1 1 1 1 1 1
=1 1
=1
B B
0 1 0 1 0 0 1 0
A 1 0 1 0 A 0 1 1 1
C C

F1=AB'C'+A'BC'+A'B'C+ABC F2=AB+AC+BC
 Design Procedure

 Given a problem statement:

● Determine the number of inputs and outputs
● Derive the truth table
● Simplify the Boolean expression for each output
● Produce the required circuit

Example:
Design a circuit to convert a “BCD” code to “Excess 3”
code
 4-bits  4-bits
 0-9 values
?  Value+3
 Design Procedure

 BCD-to-Excess 3 Converter
C C
A B C D w x y z
1 1 1
0 0 0 0 0 0 1 1
1 1 1 1
0 0 0 1 0 1 0 0 B B
x x x x x x x x
0 0 1 0 0 1 0 1 A 1 1 x x A 1 x x
0 0 1 1 0 1 1 0
D D
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0 w = A+BC+BD x = B’C+B’D+BC’D’
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0 C C
1 0 0 0 1 0 1 1 1 1 1 1
1 0 0 1 1 1 0 0 1 1 1 1
1 0 1 0 x x x x x x x x
B x x x x
B
A x x A x x
1 0 1 1 x x x x 1 1
1 1 0 0 x x x x D D
1 1 0 1 x x x x
1 1 1 0 x x x x
y = C’D’+CD z = D’
1 1 1 1 x x x x
 Design Procedure

 BCD-to-Excess 3 Converter
A B C D w x y z
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
1 0 1 0 x x x x
1 0 1 1 x x x x
1 1 0 0 x x x x
1 1 0 1 x x x x w = A + B(C+D) y = (C+D)’ + CD
1 1 1 0 x x x x x = B’(C+D) + B(C+D)’ z = D’
1 1 1 1 x x x x
Seven-Segment Decoder
a
w x y z abcdefg
w a
0 0 0 0 1111110 b
0 0 0 1 0110000 c f b
g
0 0 1 0 1101101 x ? d
e
0 0 1 1 1111001 y f
0 1 0 0 0110011 g e c
z
0 1 0 1 1011011 BCD code
0 1 1 0 1011111
0 1 1 1 1110000 y
d
1 0 0 0 1111111 1 1 1
1 0 0 1 1111011 1 1 1
1 0 1 0 xxxxxxx x x x x
x
1 0 1 1 xxxxxxx w 1 1 x x
1 1 0 0 xxxxxxx z
1 1 0 1 xxxxxxx
1 1 1 0 xxxxxxx a = w + y + xz + x’z’ b=...
c=...
1 1 1 1 xxxxxxx
d=...
 Binary Adder

 Half Adder x S
y
HA
● Adds 1-bit plus 1-bit C

● Produces Sum and Carry x

+ y
───
x y C S C S
0 0 0 0
0 1 0 1
x S
1 0 0 1
1 1 1 0
y C
 Binary Adder

 Full Adder x S
y FA
● Adds 1-bit plus 1-bit plus 1-bit z C

● Produces Sum and Carry x

+ y
y + z
x y z C S ───
0 1 0 1
0 0 0 0 0 C S
0 0 1 0 1 x 1 0 1 0
z
0 1 0 0 1
S = xy'z'+x'yz'+x'y'z+xyz = x  y  z
0 1 1 1 0
y
1 0 0 0 1
0 0 1 0
1 0 1 1 0
x 0 1 1 1
1 1 0 1 0
z
1 1 1 1 1 C = xy + xz + yz
 Binary Adder

 Full Adder S = xy'z'+x'yz'+x'y'z+xyz = x  y  z

C = xy + xz + yz

x x
S y
z S
x
y y
C
z
z C
 Binary Adder

 Full Adder
x HA HA S
y
z C

x
S

y
C
z
 Magnitude Comparator

 Compare 4-bit number to 4-bit number

● 3 Outputs: < , = , >
● Expandable to more number of bits

x3  A3 B 3  A3 B 3 A3A2A1A0 B3B2B1B0

x2  A2 B 2  A2 B2
Magnitude
x1  A1 B 1  A1 B 1 Comparator
x0  A0 B 0  A0 B 0
A<B A=B A>B
( A  B )  x 3 x 2 x1 x 0
( A  B )  A3 B 3  x 3 A 2 B 2  x 3 x 2 A1 B 1  x3 x 2 x1 A 0 B 0
( A  B )  A3 B 3  x 3 A 2 B 2  x 3 x 2 A1 B 1  x 3 x 2 x1 A 0 B 0
Magnitude Comparator
 Magnitude Comparator

x7 x6 x5 x4 x3 x2 x1 x0
y7 y6 y5 y4 y3 y2 y1 y0

A3 A2 A1 A0 B3 B2 B1 B0 A3 A2 A1 A0 B3 B2 B1 B0
0 I(A>B) I(A>B)
1 I(A=B)
Magnitude
I(A=B)
Magnitude

0 I(A<B) Comparator I(A<B) Comparator
A<B A=B A>B A<B A=B A>B

A<B A=B A>B

 Decoders

 Extract “Information” from the code Only one

lamp will
 Binary Decoder turn on
● Example: 2-bit Binary Number

0 1 2 3
1
x1 0 0
Binary

0
x0 0 Decoder
0
 Decoders

 2-to-4 Line Decoder

y3
Decoder
I1 Binary

y2
y1
I0 y0

I1 I0 Y3 Y2 Y1 Y0
0 0 0 0 0 1
0 1 0 0 1 0
Y3  I1 I 0 Y2  I1 I 0
1 0 0 1 0 0
1 1 1 0 0 0 Y1  I1 I 0 Y0  I1 I 0
 Decoders

 3-to-8 Line Decoder  I2 I1 I 0

 I2 I1 I 0
Y7
 I2 I1 I 0
Y6
Y5  I2 I1 I 0
Decoder
Binary

I2 Y4
 I2 I1 I 0
I1 Y3
I0 Y2  I2 I1 I 0

Y1
 I2 I1 I 0
Y0
 I2 I1 I 0
 Decoders

 “Enable” Control
Y3

Decoder
I1
Binary
Y2
I0 Y1
E Y0

E I1 I0 Y3 Y2 Y1 Y0
0 x x 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
 Decoders

 Expansion I2 I1 I0

I2 I1 I0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0 Y3 Y7

Decoder
I0

Binary

0 1 0 0 0 0 0 0 1 0 0 Y2 Y6
I1 Y1 Y5
0 1 1 0 0 0 0 1 0 0 0 E Y0 Y4
1 0 0 0 0 0 1 0 0 0 0
1 0 1 0 0 1 0 0 0 0 0
1 1 0 0 1 0 0 0 0 0 0 Y3 Y3

Decoder
I0

Binary

1 1 1 1 0 0 0 0 0 0 0 Y2 Y2
I1 Y1 Y1
E Y0 Y0
 Decoders

 Active-High / Active-Low
I1 I0 Y 3 Y2 Y1 Y0 I1 I0 Y 3 Y2 Y1 Y0
0 0 0 0 0 1 0 0 1 1 1 0
0 1 0 0 1 0 0 1 1 1 0 1
1 0 0 1 0 0 1 0 1 0 1 1
1 1 1 0 0 0 1 1 0 1 1 1

Y3 Y3
Decoder

I1 I1 Decoder
Binary

Binary

Y2 Y2
Y1 Y1
I0 Y0 I0 Y0
 Implementation Using Decoders

 Each output is a minterm

Binary

Decoder
 All minterms are produced
Y7
 Sum the required minterms Y6
Y5
x I2 Y4
y I1 Y3
Example: Full Adder
z I0 Y2
S(x, y, z) = ∑(1, 2, 4, 7) Y1
Y0
C(x, y, z) = ∑(3, 5, 6, 7)

S C
 Implementation Using Decoders
Binary
Binary

Decoder Decoder

Y7 Y7
Y6 Y6
Y5 Y5
x I2 Y4 x I2 Y4
y I1 Y3 y I1 Y3
z I0 Y2 z I0 Y2
Y1 Y1
Y0 Y0

S C
S C
 Encoders

 Put “Information” into code Only one

switch
 Binary Encoder should
● Example: 4-to-2 Binary Encoder be
activated
at a time
x1
1 x3 x2 x1 y1 y0
x2 y1 0 0 0 0 0
2 Binary

Encoder
0 0 1 0 1
y0 0 1 0 1 0
x3
3 1 0 0 1 1
 Encoders

 Octal-to-Binary Encoder (8-to-3)

I7
I7 I6 I5 I4 I3 I2 I1 I0 Y2 Y1 Y0 I6
0 0 0 0 0 0 0 1 0 0 0 I5

Encoder
Y2

Binary

0 0 0 0 0 0 1 0 0 0 1 I4 Y1
0 0 0 0 0 1 0 0 0 1 0 I3 Y0
0 0 0 0 1 0 0 0 0 1 1 I2
0 0 0 1 0 0 0 0 1 0 0 I1
0 0 1 0 0 0 0 0 1 0 1 I0
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1
Y2  I7 I6 I5 I4
Y1  I7 I6 I3 I2
Y0  I 7  I 5  I 3  I1
 Priority Encoders

 4-Input Priority Encoder

I3 V

Priority

Encoder
I3 I2 I1 I0 Y1 Y0 V I2 Y1
0 0 0 0 0 0 0 I1 Y0
0 0 0 1 0 0 1 I0
0 0 1 x 0 1 1
0 1 x x 1 0 1
1 x x x 1 1 1

Y1 I1
Y1  I3 I2
1 1 1 1
1 1 1 1
I2 Y0  I3 I2 I1
I3 1 1 1 1
I0
V  I 3  I 2  I1  I 0
 Encoder / Decoder Pairs

Binary
Binary

Encoder Decoder

7 I7 Y7 7

6 I6 Y6 6

5 I5 Y5 5

Y2 I2 Y4 4
4 I4 Y1
3 I3 I1 Y3 3

Y0 I0 Y2 2
2 I2
1 I1 Y1 1

0 I0 Y0 0
Multiplexers

S1 S0 Y I0
0 0 I0 I1
0 1 I1 I2 MUX Y
1 0 I2 I3
S1 S0
1 1 I3
 Multiplexers

 2-to-1 MUX

I0
I1 MUX Y
S

 4-to-1 MUX

I0
I1
I2 MUX Y
I3
S1 S0
 Multiplexers

 Quad 2-to-1 MUX

x3 I0
y3 MUX Y
I1
S

x2 I0
y2 I1
MUX Y
S A3
A2
I0 A1
x1 MUX Y A0
Y3
y1 I1 Y
S MUX Y2
1
B3 Y0
B2
I0 B1
MUX Y
x0 I1
S
B0
S E
y0
S
 Multiplexers

 Quad 2-to-1 MUX

A3
A2
A1
Y3
A0
Y2
MUX Y
1
B3 Y0
B2
B1
B0
S E
Extra
Buffers
 Implementation Using Multiplexers

 Example

F(x, y) = ∑(0, 1, 3)

x y F I0
1
0 0 1 1 I1
0 1 1 0 I2 MUX Y F
1 0 0 1 I3
S1 S0
1 1 1
x y
 Implementation Using Multiplexers

 Example

F(x, y, z) = ∑(1, 2, 6, 7)
0 I0
x y z F 1 I1
0 0 0 0 1 I2
0 0 1 1 0 I3
I4 MUX Y F
0 1 0 1 0
0 I5
0 1 1 0
1 I6
1 0 0 0 1 I7
1 0 1 0 S2 S1 S0
1 1 0 1
1 1 1 1 x y z
 Implementation Using Multiplexers

 Example

F(x, y, z) = ∑(1, 2, 6, 7)

x y z F
0 0 0 0 z I0
F=z z I1 F
0 0 1 1
0 1 0 1 0 I2 MUX Y
0 1 1 0
F=z 1 I3
S1 S0
1 0 0 0
F=0 x y
1 0 1 0
1 1 0 1
F=1
1 1 1 1
 Implementation Using Multiplexers

 Example

F(A, B, C, D) = ∑(1, 3, 4, 11, 12, 13, 14, 15)
A B C D F
0 0 0 0 0
F=D
D I0
0 0 0 1 1
0 0 1 0 0
D I1
0 0 1 1 1
F=D D I2
0 1 0 0 1
F=D 0 I3
I4 MUX Y F
0 1 0 1 0
0 1 1 0 0 0
F=0
0 1 1 1 0 D I5
1 0 0 0 0
1 0 0 1 0 F=0 1 I6
1 0 1 0 0
F=D 1 I7
1 0 1 1 1
1 1 0 0 1 S2 S1 S0
F=1
1 1 0 1 1
1 1 1 0 1
F=1 A B C
1 1 1 1 1
 Multiplexer Expansion

 8-to-1 MUX using Dual 4-to-1 MUX

I0 I0
I1 I1
I2 I2 MUX Y
I3 I3
S1 S0 I0
I1 MUX Y Y
I4 I0 S
I5 I1
I6 I2 MUX Y
I7 I3
S1 S0

1 0 0
S2 S1 S0
DeMultiplexers

Y3
Y2
I DeMUX Y
1
Y0
S1 S0

S1 S0 Y3 Y2 Y1 Y0
0 0 0 0 0 I
0 1 0 0 I 0
1 0 0 I 0 0
1 1 I 0 0 0
 Multiplexer / DeMultiplexer Pairs

MUX DeMUX

7 I7 Y7
6 I6 Y6 7

5 I5 Y5 6

4 I4 Y4 5

3 I3 Y I Y3 4

2 I2 Y2 3

1 I1 Y1 2

0 I0 Y0 1

S2 S1 S0 S2 S1 S0

Synchronize
x2 x1 x0 y2 y1 y0
DeMultiplexers / Decoders

Y3 Y3

Decoder
I1

Binary

Y2 Y2
I DeMUX Y I0 Y1
1
Y0 E Y0
S1 S0

E I1 I0 Y3 Y2 Y1 Y0
S1 S0 Y3 Y2 Y1 Y0 0 x x 0 0 0 0
0 0 0 0 0 I 1 0 0 0 0 0 1
0 1 0 0 I 0 1 0 1 0 0 1 0
1 0 0 I 0 0 1 1 0 0 1 0 0
1 1 I 0 0 0 1 1 1 1 0 0 0
 Three-State Gates

 Tri-State Buffer
C A Y
0 x Hi-Z
A Y
1 0 0
1 1 1
C
A Y
 Tri-State Inverter
C
Three-State Gates

A C D Y
0 0 Hi-Z
Y 0 1 B
C
1 0 A
B 1 1 ?

Not Allowed
D
A
C A if C = 1
Y=
B if C = 0
B
Three-State Gates

I3

I2
Y
I1

I0
Y3
Decoder

S1 I1
Binary

Y2
S0 I0 Y1
E E Y0