Advanced Digital Design
EC9040
Department of Computer Engineering,
University of Jaffna.
Gate Level Modeling.
In gate level modeling, the circuit is specified with logic gates and
their interconnections.
The Verilog HDL includes 12 logic gates as predefined primitives
such as
– and, nand, or, nor, xor, xnor, buf and not and four of tri-
state type gates.
– Some of them are n input primitives (such as and and or)
– Some of are n output primitives (such as not and buf).
Gate Level Modeling.
Tri-state type gates
Gate Level Modeling.
The logic of each gate is based on a four-valued system,
which are
• The logic values of 0 and 1.
• Unknown value (denoted by x).
• High Impedance (denoted by z).
Gate Level Modeling.
An unknown value is assigned during the simulation when the
logical value of a signal is unknown.
A high impedance condition occurs at the output of a three-
state gate when the gate is not enabled or if a wire is
inadvertently left unconnected.
Gate Level Modeling.
The four-valued logic truth tables for the and, or, xor and not are
shown in Table 1. Table 1
Gate Level Modeling.
In gate level modelling, the identifiers with multiple bit width is
called as vectors and the syntax consists of a group of two
numbers are separated by a colon, is enclosed by a square
bracket,
e.g.:
output [3:0] D;
wire [7:0] sum;
Where the D has 4 bits and the sum has 7 bits.
2x4 Decoder.
Verilog HDL for a 2:4 decoder with active low logic is given in
next slide.
2x4 Decoder.
module decoder_2X4_gates (D, A, B, enable);
output [3:0] D;
input A, B, enable;
wire A_not, B_not, enable_not;
not
G1 (A_not, A),
G2 (B_not, B),
G3 (enable_not, enable);
nand
G4 (D[0], A_not, B_not, enable_not),
G5 (D[1], A_not, B, enable_not),
G6 (D[2], A, B_not, enable_not),
G7 (D[3], A, B, enable_not);
endmodule
Half adder and Full adder.
Two or more sub modules can be combined together to build
hierarchical description of a module.
e.g. Half adder (1 bit) -> Full Adder (1 bit).
Half adder and Full adder.
// 1-bit Half adder // 1-bit Full adder
module half_adder (S, C, x, y); module full_adder (S, C, x, y, z);
output S, C; output S, C;
input x, y; input x, y, z;
xor (S, x, y); wire S1, C1, C2;
and (C, x, y); half_adder (S1, C1, x, y);
endmodule half_adder (S, C2, S1, z);
or (C, C1, C2);
endmodule
Gate Level Modeling
Full adder (1 bit) -> Full adder (4 bit)
HDL Description of 4-bit full adder is shown in next slide.
Full adder (1 bit) -> Full adder (4 bit)
// 1-bit Full adder // 4-bit Full adder
module full_adder (S, C, x, y, z); module Four_bit_full_adder (S,
output S, C; C4, x, y, C0);
input x, y, z; output [3:0]S;
output C4;
wire S1, C1, C2; input [3:0] x, y;
half_adder (S1, C1, x, y); input C0;
half_adder (S, C2, S1, z);
or (C, C1, C2); wire C1, C2, C3;
endmodule full adder
F0 (S[0], C1, x[0], y[0], C0),
F1 (S[1], C2, x[1], y[1], C1),
F2 (S[2], C3, x[2], y[2], C2),
F3 (S[3], C4, x[3], y[3], C3);
endmodule
Dataflow Modeling - Operators.
Verilog uses a number of operators that act on binary operands
to produce end results. The available arithmetic, binary and
logical operators in Verilog is shown in Table 2.
Table 2
Dataflow Modeling.
Dataflow modeling of Verilog uses continuous assignments
which uses assign keyword and can drive only a net (wire or tri
data type).
e.g. The following continuous assignment statement describes a
two-to-one line multiplexer.
A
Y
B
S
2x4 Decoder.
Dataflow modeling of a 2x4 decoder is described in next slide.
2x4 Decoder.
module decoder_2x4_df (D, A, B, enable);
output [3:0]D;
input A, B, enable;
assign
D[0] = !((!A) && (!B) && (!enable)),
D[1] = !((!A) && B && (!enable)),
D[2] = !(A && (!B) && (!enable)),
D[3] = !(A && B && (!enable));
endmodule
Full adder.
Dataflow modeling of a four bit full adder with concatenation
operator is given in next slide.
Full adder.
module binary_adder (Sum, C_out, A, B, C_in);
output [3:0] Sum;
output C_out;
input [3:0] A, B;
input C_in;
assign {C_in, Sum} = A + B + C_in;
endmodule
Mag. Comparator.
Dataflow modeling of a magnitude comparator is given in next
slide.
Mag. Comparator.
module mag_compare (A_lt_B, A_gt_B, A_eq_B, A, B);
output A_lt_B, A_gt_B, A_eq_B;
input [3:0] A, B;
assign A_lt_B = (A < B);
assign A_eq_B = (A == B);
assign A_gt_B = (A > B);
endmodule
2x1 Mux.
Dataflow modeling of a 2:1 Mux with conditional operator is
given in next slide.
2x1 Mux.
module two_to_one_mux (m_out, A, B, select);
output m_out;
input A, B, select;
assign m_out = select ? A : B ;
endmodule
Behavioral Modeling.
Behavioral model represents digital circuits at a functional or
algorithmic level.
Behavioral modeling is used in most of sequential circuits but
can also be used to describe combinational circuits.
Behavioral description uses the keyword always or initial.
Always block
The always keyword is followed by an optional event control
statement and a list of procedural assignment statements.
always @ (event control expression) begin
// procedural assignment statements.
end
The event control statement specifies when the statements will
execute.
The list of procedural assignment statements will be executed
whenever the inputs in the event control statement changes.
Always block
• The target output of a procedural assignment (the variable at
L.H.S) statement must be a reg data type.
– A reg data type can be continuously updated and its values
will retain until a new value is assigned.
• The keyword always declares a cyclic behavior.
Initial Block
• The keyword initial is called single-phase behavior.
• It consists of a statement or block of statements and which
expires after the associate statements executes.
• Used to prescribe the stimulus signals in a test bench.
• Synthesize step will not include initial block.
Behavioral Modeling.
• Both type of behaviors execute at t = 0 and
– the initial expires after its statement executes
– the always executes and reexecutes indefinitely until the
simulation is stopped.
• A module may contain any number of always and/ or initial
behaviors and they execute concurrently.
2:1 Line Multiplexer
The behavioral description of a 2:1 line multiplexer is given in
next slide.
2:1 Line Multiplexer
module mux_2x1_behavior (m_out, A, B, select);
output m_out;
input A, B, select;
always @ (A or B or select)
begin
if (select == 1) m_out = A;
else m_out = B;
end
endmodule
A Clock
In sequential designs a clock input is necessary to simulate the
circuit. The three possible ways are listed to create a clock using
initial statement.
A Clock
In sequential designs a clock input is necessary to simulate the
circuit. The three possible ways are listed to create a clock using
initial statement.
initial initial
begin begin
clock = 1’b0; clock = 1’b0;
repeat (30) end
#10 clock = ~ initial #300 $finish;
clock; always #10 clock = ~clock;
end
initial begin clock = 1’b0; forever #10 clock = ~clock; end
Operators.
The activity associated with either type of behavioral statement
can be controlled by either
– a delay control operator (#) or
– an event control operator (@).
The delay control operator suspends execution of the statement
until a specified time has elapsed.
Operators.
The event control operator is used to suspend the activity until
an event occurs. An event can be either,
• An unconditional change in a signal value.
• A specified transition of a signal value.
Recap
The general form of always statement is,
always @ (event control expression) begin
// procedural assignment statements.
end
The variable in the left hand side of the procedural statement
must be a reg data type.
Recap
The event control expression specifies the event that must occur
to initiate the execution of the procedural statements. An event
can be,
– Level sensitive or Edge sensitive. e.g,
• always @ (A or B or C)
• always @ (posedge clock or negedge reset)
• always @ (posedge clock, negedge reset) // according
to Verilog 2005 standard.
Procedural assignments
• There are two types of procedural assignment statements,
such as
• Blocking assignment.
• Non blocking assignment.
• Blocking assignment uses the symbol (=) as the assignment
operator.
• Non blocking assignment uses the symbol (<=) as the
assignment operator.
Procedural assignments.
• Blocking assignment statements are executed sequentially in
the order they appear in the block of statements.
• Non blocking assignment statements are executed
concurrently by executing R.H.S of the list of statements.
e.g:
B= A B <= A
C=B+1 C <= B + 1
(Blocking assignments) (Non blocking assignments)
Procedural assignments.
A general rule
• Use blocking assignment when sequential ordering is
imperative and in cyclic behavior and the event control
statement is level sensitive.
• Use non blocking assignments when modelling concurrent
execution (e.g. edge sensitive behavior) and when
modelling latched behavior.
D Latch.
HDL description for D latch is given in next slide.
D Latch.
module D_latch (Q, D, enable);
output Q;
input D, enable;
reg Q;
always @ (D or enable)
if (enable)
Q <= D;
endmodule
D Flip flop
HDL description for D FF is given in next slide.
D Flip flop
// without reset // with asynchronous reset
module D_FF (Q, D, clock); module D_FF (Q, D, clock, reset);
output Q; output Q;
input D, clock; input D, clock, reset;
reg Q; reg Q;
always @ (posedge clock) always @ (posedge clock
Q <= D; or negedge reset)
endmodule if (reset == 0)
Q <= 1’b0;
else
Q <= D;
endmodule
Asynchronous input with synchronous
clock in edge sensitive events.
When modelling edge sensitive events of both asynchronous
input and synchronous clock, you need to explicitly say to the
software tool (the synthesizer) which are asynchronous input
and which is the synchronous clock.
.
Asynchronous input with synchronous
clock in edge sensitive events.
In order to model the both events you need to follow a general
rule which is,
1. Each if or else if statement in the procedural assignment
statement corresponds to an asynchronous event.
2. The last else statement corresponds to the clock event.
T and JK flip flop using D flip flops.
Characteristic Equations
• T FF: Q (t+1) = Q ⊕ T
• JK FF: Q (t+1) = JQ’ + K’Q
T and JK flip flop using D flip flops.
// D FF with asynchronous reset
module D_FF (Q, D, clock, reset);
output Q;
module T_FF (Q, T, clock, reset);
input D, clock, reset;
output Q;
reg Q;
input T, clock, reset;
wire QD;
always @ (posedge clock
or negedge reset)
assign QD= Q ^ T;
if (reset == 0)
D_FF DFF1 (Q, QD, clock,
Q <= 1’b0;
reset );
else
Q <= D; endmodule
endmodule
T and JK flip flop using D flip flops.
// D FF with asynchronous reset
module D_FF (Q, D, clock, reset); module JK_FF (Q, J, K, clock,
output Q; reset);
input D, clock, reset; output Q;
reg Q; input J, K, clock, reset;
wire QD;
always @ (posedge clock or
negedge reset) assign QD= (J & (~Q)) |
if (reset == 0) ((~K)&Q);
Q <= 1’b0; D_FF DFF2 (Q, QD, clock,
else reset );
Q <= D;
endmodule endmodule
JK flip flop using case statement
module JK_FF (Q, J, K, clock
output Q;
input J, K, clock;
always @(posedge clock)
begin
case ({J, K})
2’b00: Q <= Q;
2’b01: Q <= 1’b0;
2’b10: Q <= 1’b1;
2’b11: Q <= ~Q;
endcase
end
endmodule
References
[1]. “Digital Design”, “Fifth edition”, M.Morris
Mano, Michael D. Ciletti.
