MC

20 September 2024 22:14

Sir, let's break down these concepts step by step, focusing on the memory architecture and key concepts related
to the AVR Atmega32 microcontroller. I'll guide you through visualizing the memory map, registers, I/O ports,
stack, etc.
1. Memory Map of Atmega32
AVR microcontrollers like the Atmega32 have 3 main types of memory:
• Flash Memory (Program Memory): Stores the program you write in assembly or C.
• SRAM (Data Memory): Stores variables, stack, and I/O register data.
• EEPROM: Stores non-volatile data that needs to be saved after power off.
Here’s the layout:

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| Memory Type | Address Range | Size |
|-----------------|-----------------------|------------|
| Flash (Program) | 0x0000 to 0x3FFF | 32 KB |
| SRAM (Data) | 0x0060 to 0x085F | 2 KB |
| EEPROM | 0x0000 to 0x03FF | 1 KB |
Flash Memory
• Used to store your program (instructions).
• Atmega32 has 32 KB of flash memory (addresses: 0x0000 - 0x7FFF).
SRAM (Data Memory)
• Contains general-purpose registers, I/O registers, data memory (variables), and stack.
• Size: 2 KB (from 0x0060 to 0x085F).
Let's break down the SRAM:
2. Registers and I/O Ports
General-Purpose Registers (R0 - R31):
• R0 to R31 are 32 general-purpose registers.
• Size of each register: 8 bits (1 byte).
• Memory address of registers: They occupy addresses from 0x0000 to 0x001F in the SRAM.
Visualization:

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R0 -> Address 0x0000 (8 bits)
R1 -> Address 0x0001 (8 bits)
...
R31 -> Address 0x001F (8 bits)
I/O Registers:
• The I/O registers are mapped in memory from 0x0020 to 0x005F.
• They control I/O operations like ports (PORTA, PORTB, etc.) and timers.
Example I/O Ports:
○ PORTA: 0x003B
○ PORTB: 0x0038
○ PORTC: 0x0035
○ PORTD: 0x0032
Each I/O register is 1 byte (8 bits), meaning you can write an 8-bit value to control the pins (0 or 1).
Example:

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 Example:
○ Writing 0xFF to PORTA will set all 8 pins of PORTA high.
3. Stack
• The stack is used to store temporary data like return addresses when calling functions.
• The stack pointer (SP) holds the address of the top of the stack.
• In Atmega32, the stack grows downwards (from high memory to low memory in SRAM).
○ Default SP address starts at the end of SRAM (0x085F) and grows downwards.
When a function is called, the current address is pushed onto the stack, and when the function returns,
it is popped from the stack.
Visualizing the stack:

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0x085F (Top of SRAM)
↓
0x0060 (Bottom of SRAM)

4. Input/Output (I/O) Ports and Addresses

Each port controls 8 pins on the microcontroller, which can be used as input/output. Each port has three
associated registers:
1. DDRx (Data Direction Register): Defines whether the port's pins are input (0) or output (1).
2. PORTx: Controls whether an output pin is high (1) or low (0).
3. PINx: Reads the value at the input pin.
• PORTA, PORTB, PORTC, and PORTD are the four main I/O ports. Here's how you can visualize them:

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PORTA (0x003B): 8 pins PA7 to PA0
PORTB (0x0038): 8 pins PB7 to PB0
PORTC (0x0035): 8 pins PC7 to PC0
PORTD (0x0032): 8 pins PD7 to PD0
5. Stack Operations
• PUSH: Store data on the stack. The Stack Pointer (SP) decreases, and the data is stored in the new SP
location.
• POP: Retrieve data from the stack. The Stack Pointer (SP) increases, and data is fetched from the SP location.
Visualization of Stack Operations:
○ PUSH: SP moves from 0x085F → 0x085E, stores data at 0x085E.
○ POP: SP moves back to 0x085F, retrieves data from 0x085E.

6. Key Concepts to Remember

• Registers (R0 to R31) are used for arithmetic and logical operations, each being 8 bits.
• I/O ports (PORTA, PORTB, etc.) control the microcontroller pins and are accessed using memory-mapped
registers.
• The stack grows downwards in SRAM, and it is used for storing return addresses and local variables during
function calls.
Summary for Exam:
1. Visualize memory layout: Registers at the bottom, I/O registers in the middle, data/stack at the top.
2. Understand register size: General-purpose registers are 8-bit, I/O registers are 8-bit.
3. Remember stack grows downward: Know how PUSH/POP affects the Stack Pointer (SP).
4. Ports: Know how to configure and control input/output using DDRx, PORTx, and PINx.
By mentally visualizing the memory layout, you'll be able to understand how the microcontroller uses its memory
and how you access different sections like registers, I/O ports, and stack efficiently in assembly language. Let me

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and how you access different sections like registers, I/O ports, and stack efficiently in assembly language. Let me
know if you'd like any specific code examples or further explanation on any section!

Sir, I understand you're looking for clarification on the CALL instructions and their relation to memory
addressing, as well as the concepts behind RCALL, ICALL, and EICALL in AVR assembly. Let's go through
these instructions one by one and connect them to memory addressing, including how the Z-register
works in ICALL and EICALL.

1. RCALL (Relative Call)

Overview:
• RCALL is a relative call instruction that allows branching within a range of the current program
counter (PC).
• It can jump to a subroutine located within -2K to +2K words from the current PC.
Memory Address Calculation:
• The range is defined by 12 bits. Hence, the total memory range RCALL can address is: 212=
4096addresses=4Kwords2^{12} = 4096 \, \text{addresses} = 4K \, \text{words}212=
4096addresses=4Kwords
• This range of 4096 words allows the program to jump to subroutines located up to 2K words
backward or forward from the current PC.
Cycles:
• The RCALL instruction takes 3 cycles (1 cycle for fetching and 2 cycles for storing the return
address on the stack).
Example:
If your program counter (PC) is currently at address 0x1000, RCALL can branch to an address in the
range:
• From PC - 2048 (0x0800) to PC + 2048 (0x1800).

2. ICALL (Indirect Call)

Overview:
• ICALL is an indirect call instruction that jumps to the address stored in the Z-register (R31:R30).
• The Z-register is a 16-bit register pair (R31:R30) used for indirect addressing, which can hold the
full 16-bit program memory address.
Z-Register Memory Addressing:
• The Z-register can address the entire program memory range (up to 64K words of address space).
• ICALL can jump to any address stored in the Z-register, making it more flexible than RCALL.
• The upper bits (from 16 to 21) are not needed for addressing with ICALL, as it operates within the
64K range (16-bit space).
Cycles:
• The ICALL instruction takes 3 cycles: one to fetch the instruction and two to store the return
address on the stack.
Example:
Let’s say the Z-register contains the value 0x2000, representing an address in program memory. When
ICALL is executed, the program counter jumps to address 0x2000.

3. EICALL (Extended Indirect Call)

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3. EICALL (Extended Indirect Call)
Overview:
• EICALL is used in devices that support larger program memory, exceeding 64K words (typical for
AVR microcontrollers with more than 64K program memory).
• EICALL uses the EIND register in conjunction with the Z-register to support extended address
ranges.
Z-Register and EIND Register:
• The Z-register (R31:R30) still holds the lower 16 bits of the program memory address.
• The EIND register (Extended Indirect Register) holds the upper bits (17–21) to allow access to
program memory beyond 64K.
• Together, they can address up to 128K or more, depending on the architecture.
Cycles:
• The EICALL instruction takes 4 cycles due to the need to fetch the extended address and store the
return address on the stack.
Example:
If the EIND register contains the value 0x1 and the Z-register contains the value 0x2000, the combined
address is 0x12000 in extended program memory. Executing EICALL will jump to address 0x12000.

Key Points Summary:

1. RCALL:
○ Used for relative branching within a 4K word range.
○ Calculated by 2^12 = 4096 words.
○ Takes 3 cycles.
2. ICALL:
○ Uses the Z-register (R31:R30) to hold a 16-bit address.
○ Can address up to 64K words in program memory.
○ Takes 3 cycles.
3. EICALL:
○ Used for extended addressing beyond 64K words.
○ Combines EIND and Z-register to address extended program memory.
○ Takes 4 cycles.

Visualization of Memory Addressing:

• RCALL can jump within 2K words backward or 2K words forward from the current position in the
program counter.
• ICALL can jump to any 16-bit address stored in the Z-register, covering a full 64K word space.
• EICALL can jump to larger addresses by using the EIND register to extend the address space
beyond 64K words.

Sir, let's break down the details of the Unconditional Branch (JMP) instruction in AVR assembly,
including the bit structure and how the address is calculated.

JMP (Unconditional Jump) Instruction Overview

• JMP is an unconditional jump instruction that causes the program to jump to a specific address in

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 • JMP is an unconditional jump instruction that causes the program to jump to a specific address in
the program memory.
• Unlike RCALL, which uses relative addressing, JMP uses an absolute address in the program
memory.
• The destination (target address) is specified directly as part of the instruction.

Bit Breakdown of the JMP Instruction

The JMP instruction uses 32 bits in total:
• 16 bits are used for the opcode (instruction itself).
• 22 bits are used for the target address (the location where the program should jump).
Bit Structure:

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[15:0] Opcode for JMP
[21:0] Target address
• The 16-bit opcode defines the JMP instruction itself.
• The target address is specified using 22 bits. This gives the instruction the ability to jump
anywhere in the program memory within the 22-bit address space.

Memory Addressing with JMP

With 22 bits for the target address, the JMP instruction can address up to:
222=4,194,304words=4Mwords2^{22} = 4,194,304 \, \text{words} = 4M \, \text{words}222=
4,194,304words=4Mwords
Since AVR program memory is word-addressed (each instruction takes one word, typically 16 bits), the
JMP instruction can jump to any location in a 4M word address space. This means it can handle program
memory sizes of up to 8MB (since each word is 2 bytes).

Opcode and Target Address Details

1. 16-bit Opcode:
○ The first 16 bits are used to encode the actual instruction (JMP). These bits tell the
processor that this is a JMP instruction.
2. 22-bit Target Address:
○ The next 22 bits are used to specify the absolute address in the program memory where the
program should jump.
○ The 22-bit address space allows the processor to jump to any address within the 4M word
program memory.
To break it down further:
○ The most significant bits (higher bits) in this 22-bit address will handle large program
memory jumps.
○ The lower significant bits handle jumps within smaller address ranges.

How the Processor Executes JMP

1. The JMP instruction fetches the target address from the 22-bit address field.
2. The program counter (PC) is then loaded with this 22-bit address.
3. The program execution continues from the new address in program memory.

Example JMP Instruction:

Here’s an example of a JMP instruction:

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JMP 0x1F200 ; Jump to address 0x1F200
• The instruction tells the processor to jump to the absolute address 0x1F200 in program memory.
• This address is part of the 22-bit address space, so it could be anywhere within the first 4M words.

Key Differences Between JMP and RCALL

• RCALL uses relative addressing with a 12-bit offset to jump within a ±2K word range from the
current program counter.
• JMP uses absolute addressing with a 22-bit target address to jump anywhere in the entire
program memory (up to 4M words or 8MB).

Cycle Count for JMP

• The JMP instruction typically takes 3 cycles: one to fetch the instruction and two to load the new
address into the program counter.

Summary of JMP:
• Total instruction size: 32 bits (16 bits for opcode + 22 bits for target address).
• Address range: Can jump to any address within 4M words (or 8MB of memory).
• Cycle count: Typically 3 cycles.
• Absolute addressing: Directly specifies the target address in program memory.

Sir, let's go over the RJMP (Relative Jump) and IJMP (Indirect Jump) instructions in AVR assembly. These
are variations of jump instructions, each serving a different purpose when it comes to addressing memory
locations. I'll explain their operation, addressing methods, and bit structure.

1. RJMP (Relative Jump)

The RJMP instruction is a relative jump, which means it doesn't jump to an absolute address, but rather
an address that is a certain offset (positive or negative) from the current program counter (PC).
Bit Breakdown of RJMP:
• Instruction size: 16 bits
• 12-bit relative address offset (2’s complement).
• Can jump forward or backward within a range of -2K to +2K words.
Bit Structure:

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[15:12] Opcode for RJMP

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[15:12] Opcode for RJMP
[11:0] Relative address (signed 12-bit offset)
• The 12-bit relative address is in 2's complement form, meaning the jump can be either forward
(positive offset) or backward (negative offset) from the current program counter.
Address Range:
Since 12 bits are used for the offset, RJMP can jump to locations within a range of ±2K words from the
current instruction. Here's the breakdown:
• 2^12 = 4096 locations.
• Half of these are for forward jumps (+2047 words).
• The other half are for backward jumps (-2048 words).
Cycle Count:
• 2 cycles: One cycle for fetching the instruction and one for calculating the jump address and
updating the program counter.
Example:

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RJMP +100 ; Jump 100 instructions forward
RJMP -50 ; Jump 50 instructions backward
In the first case, it jumps 100 instructions forward from the current location. In the second case, it jumps
50 instructions backward.

2. IJMP (Indirect Jump)

The IJMP instruction performs a jump to an address stored in the Z-register (R30 and R31 combined). This
is known as indirect addressing because the target address is not given directly in the instruction but is
instead stored in a register.
Bit Breakdown of IJMP:
• Instruction size: 16 bits
• The Z-register (R30 and R31) holds the target address.
Bit Structure:

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[15:0] Opcode for IJMP
• There are no bits for the address itself since the address is stored in the Z-register.
• The Z-register is a 16-bit register made up of R30 (low byte) and R31 (high byte).
How IJMP Works:
• The Z-register contains the absolute target address.
• The IJMP instruction reads this address and jumps to it.
Example:

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LDI R30, LOW(0x1F00) ; Load the low byte of the address
LDI R31, HIGH(0x1F00) ; Load the high byte of the address
IJMP ; Jump to the address in Z-register (0x1F00)
Address Range:
Since the Z-register is 16 bits wide, IJMP can address the full 64K (65,536 words) of program memory.
Cycle Count:
• 2 cycles: One cycle to fetch the instruction and one to jump to the address stored in the Z-register.

3. EIJMP (Extended Indirect Jump)

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3. EIJMP (Extended Indirect Jump)
The EIJMP instruction extends the capability of IJMP to jump to a larger program memory space. It's used
in microcontrollers with more than 64K of program memory.
Bit Breakdown of EIJMP:
• Instruction size: 16 bits
• The EIND register is used to extend the address.
Address Range:
• EIND register provides the most significant bits (MSB) of the target address.
• The Z-register provides the lower bits (R30 and R31).
With EIND, the processor can address more than 64K program memory locations, extending it to larger
addressable ranges (up to 4M words, if EIND is large enough).
Cycle Count:
• 2 cycles, similar to IJMP.

Comparison of JMP, RJMP, IJMP, and EIJMP

Instructio Addressing Bit Size Address Cycles Usage
n Mode Range
JMP Absolute 32 bits 4M words 3 Jump to any location in the entire
Addressing memory space
RJMP Relative 16 bits ±2K words 2 Jump forward or backward within a ±2K
Addressing range
IJMP Indirect 16 bits 64K words 2 Jump to the address stored in the Z-
Addressing register (R30
)
EIJMP Extended Indirect 16 bits >64K words 2 Jump to extended memory locations
Jump using EIND and Z-register

Summary:
• RJMP is useful for short relative jumps within a small range of the current program counter.
• IJMP is used for indirect jumps where the address is stored in a register (Z-register).
• EIJMP extends this to larger memory spaces by using the EIND register for more significant bits.
Let me know if this clarifies the topic or if you need more examples!

GENERAL MEMORY ADDRESS OF ATMEGA 32

Sir, the memory architecture of the ATmega32 microcontroller is quite comprehensive, as it includes
several types of memory, each serving different purposes. Let’s break it down step by step to provide a
clear understanding of the memory address spaces in the ATmega32:

1. Flash Program Memory (ROM)

• Size: 32 KB (32,768 bytes)
• Purpose: Stores the program code (machine instructions).
• Access: It is non-volatile memory, meaning it retains the data even when the power is off.

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 • Access: It is non-volatile memory, meaning it retains the data even when the power is off.
• Addressing:
○ The Flash memory is word-addressable (each instruction word is 16 bits).
○ Flash memory uses 16-bit program counters (PC), meaning it can address 64K words or
128K bytes (even though only 32K bytes are used in ATmega32).
Memory Map:
• Addresses: 0x0000 to 0x7FFF (for 32 KB of memory)
• This is where the program instructions are stored. The CPU fetches instructions from this memory
during program execution.

2. SRAM (Static RAM)

• Size: 2 KB (2048 bytes)
• Purpose: Stores variables, stack, and temporary data during program execution.
• Access: It is volatile memory, meaning it loses its contents when power is lost.
Memory Map:
• Addresses: 0x0060 to 0x085F (for 2 KB of SRAM)
The first few addresses of the SRAM are reserved for registers and I/O ports (explained in the next
sections), and the rest is general-purpose data space.

3. Register File
• Size: 32 General-Purpose Registers (R0-R31)
• Purpose: Used by the CPU for arithmetic, logic operations, and general processing.
• Access: Fast access by the CPU.
Memory Map:
• Addresses: 0x0000 to 0x001F
Each register is 8 bits wide, and there are 32 such registers. They are named R0 to R31 and are used for
intermediate calculations and data storage during operations.

4. I/O Registers (I/O Memory)

• Size: 64 Bytes
• Purpose: Controls the operation of peripherals (timers, ADCs, USART, etc.) and I/O ports.
Memory Map:
• Addresses: 0x0020 to 0x005F
This range of memory is mapped to I/O control registers that allow interaction with the
microcontroller's peripherals and ports.

5. Extended I/O Registers

• Size: 160 Bytes
• Purpose: More I/O control registers that extend the capability of the I/O system.
Memory Map:
• Addresses: 0x0060 to 0x00FF
This area provides additional space for special function registers (SFRs) used to control more
peripherals, timers, ADC, etc.

6. EEPROM (Electrically Erasable Programmable Read-Only Memory)

• Size: 1 KB (1024 bytes)
• Purpose: Used to store non-volatile data that needs to be retained even when the power is off
(like user settings, calibration data, etc.).
Memory Map:
• Addresses: Separate from the standard SRAM and Flash memory.
• The EEPROM is accessed using special EE registers (EERE, EEWE, etc.), meaning the CPU cannot

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 • The EEPROM is accessed using special EE registers (EERE, EEWE, etc.), meaning the CPU cannot
directly manipulate it like the SRAM. Instead, specific instructions are used to read and write to
EEPROM.

7. Stack Memory
• Size: Variable, allocated within SRAM.
• Purpose: Used for storing return addresses when a subroutine is called and for saving temporary
data during interrupts or subroutine execution.
Memory Map:
• The stack grows from higher memory addresses to lower memory addresses (descending stack).
The location of the stack pointer (SP) is user-configurable and is generally initialized at the end of
the SRAM space and moves downwards as data is pushed onto the stack.
• The Stack Pointer (SP) is a 16-bit register and points to the current location in the SRAM where
the next value will be pushed or popped.

8. Interrupt Vector Table

• Purpose: Holds the addresses of the interrupt service routines (ISRs). When an interrupt occurs,
the processor jumps to the corresponding address in the interrupt vector table.
Memory Map:
• Addresses: The table is located at the beginning of Flash memory, starting from 0x0000. Each
interrupt source is assigned a specific address where the corresponding ISR (Interrupt Service
Routine) starts.

Memory Layout in ATmega32:

Memory Area Address Range Size Purpose
Flash Program 0x0000 to 0x7FFF 32 KB Program storage
Memory
SRAM 0x0060 to 0x085F 2 KB Data, stack, and variables
Register File 0x0000 to 0x001F 32 registers Fast-access registers
I/O Registers 0x0020 to 0x005F 64 bytes I/O port control
Extended I/O 0x0060 to 0x00FF 160 bytes Extended I/O control
Registers
EEPROM Special access 1 KB Non-volatile data storage
Stack Within SRAM Variable Stores return addresses and temporary
data
Interrupt Vectors 0x0000 and upwards - Interrupt service routines

Addressing the Different Memory Spaces

1. Program Memory (Flash):
• Accessed by PC (Program Counter): Instructions are fetched from Flash memory based on the PC
value. It’s word-addressable (16-bit instructions).
2. Data Memory (SRAM):
• Direct and Indirect Addressing: SRAM is accessed using direct, indirect, and indexed addressing
modes. The X, Y, and Z registers (16-bit pairs of R26–R31) are often used for indirect addressing of
SRAM.
3. EEPROM:
• Accessed using Special Registers: It’s not directly mapped to the SRAM or program memory
address space. Instead, the EEPROM is accessed through special function registers (like EEAR,

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 address space. Instead, the EEPROM is accessed through special function registers (like EEAR,
EEDR, EECR) and controlled with specific read/write instructions.
4. I/O Memory:
• Mapped to SRAM: I/O registers are mapped into the first 64 bytes of the SRAM address space.
You can use IN/OUT instructions to access I/O registers efficiently.

Visualizing the Memory in ATmega32

1. Flash Program Memory: At the top, you have the 32KB program memory, where your machine
instructions are stored. The interrupt vector table starts at the beginning.
2. SRAM: Below Flash, you have 2KB of SRAM, used for storing data variables, stack, etc. It starts
after the registers and I/O memory.
3. I/O Registers: The 64-byte I/O space is located in the lower addresses of SRAM. This is where
control registers for ports (like PORTB, PORTD) are found.
4. EEPROM: EEPROM is separate from the standard memory spaces but is accessed using EEPROM
registers.

DEF, EQU, SET instructions difference

Sir, in AVR Assembly (and assembly language in general), DEF, EQU, and SET are used to define
constants or symbolic names for values, but they have slightly different usages and behaviors. Here’s an
explanation of each:

1. DEF (Define Register)

• Purpose: Used to create a symbolic name for a register. You can think of it as giving a register a
meaningful name for easier reference in your program.
• Usage: This is particularly useful for making code more readable and maintainable, as it allows you
to refer to registers by name instead of their number.
Syntax:

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.DEF myRegister = R16
This tells the assembler that whenever you write myRegister, it should treat it as R16. The value of
myRegister is fixed and can only be a register.
Example:

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.DEF tempReg = R16 ; Define a symbolic name for register R16

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.DEF tempReg = R16 ; Define a symbolic name for register R16
LD tempReg, ZL ; Load a value into R16 using its symbolic name
ADD tempReg, R17 ; Add the value of R17 to the value in R16
In this case, tempReg refers to the register R16.

2. EQU (Equate)
• Purpose: Used to define a constant. The value associated with the name is fixed and cannot be
changed once defined. It is used to assign names to constants, such as addresses, bit positions, or
values that will be used throughout the program.
• Usage: It is a symbolic constant and is typically used for defining constants or memory addresses.
Syntax:

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.EQU myConstant = 0x20
This means that myConstant will always represent the value 0x20. It can’t be modified later in the
program.
Example:

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.EQU ledPin = 0x01 ; Define a constant value for the LED pin (bit 0)
.EQU portAddress = 0x25 ; Define a constant for the address of the I/O port
LDI R16, ledPin ; Load the LED pin value (0x01) into R16
OUT portAddress, R16 ; Write the value of R16 to the I/O port (0x25)
In this example, ledPin is a constant with a value of 0x01, and portAddress refers to an I/O address
(0x25).

3. SET
• Purpose: Similar to EQU, but it is not immutable. Once defined, the value associated with the
symbol can be changed later in the program. It's like a variable that can be reassigned multiple
times during assembly.
• Usage: Used when you want a symbolic name to represent a value that can change during
assembly (e.g., recalculating values during the assembly process).
Syntax:

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.SET myVariable = 0x10
This assigns the value 0x10 to myVariable, but unlike EQU, you can change the value later.
Example:

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.SET counterValue = 0x10 ; Set the initial value of the counter
LDI R16, counterValue ; Load counterValue (0x10) into R16
.SET counterValue = 0x20 ; Update the value of counterValue
LDI R17, counterValue ; Load the updated value (0x20) into R17
In this case, counterValue is first set to 0x10, but then later it is updated to 0x20.

Key Differences:
Feature DEF EQU SET

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Feature DEF EQU SET
Purpose Define a symbolic name Define a constant value Define a modifiable constant
for a register
Value Register only (e.g., R16, Fixed value, can’t be changed Value can be changed later
R17)
Usage Makes register access Assigns names to constants Assigns values that may change
easier (addresses, values) during assembly
Mutabilit Fixed (register name Fixed (can’t be changed) Mutable (can be reassigned)
y only)

When to Use Each:

• Use DEF to create aliases for registers, making your code easier to understand and manage.
• Use EQU when you need a constant value that you want to refer to symbolically throughout your
program (such as pin numbers, addresses, or fixed values).
• Use SET when you need a symbolic name for a value that you may want to change during
assembly, like recalculating an offset or other variable values.

MEMORIZE

1. Address Calculation Formula

• For a 16-bit address space: Maximum Address=2^16−1=65535(in decimal)
○ Hexadecimal Range: $0000H to $FFFFH.
2. Memory Size Insight
• Flash Memory Size: The Atmega32 has 32 KB of Flash memory.
○ Conversion: 32 KB=32×1024=3276832 \text{ KB} = 32 \times 1024 = 3276832 KB=32×1024=
32768 bytes.
Last Usable Address:

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 ○ Last Usable Address:
 327683276832768 in decimal is $7FFFH in hexadecimal.
3. Quick Reference for Bits
• 16-bit = 2^16:
○ Addresses: 216=655362^{16} = 65536216=65536
○ Range: $0000H to $FFFFH.
4. Important Addresses to Remember
• Starting Address: $0000H
• Ending Address for 32 KB: $7FFFH (for AtMega32 of 32kb)
• Unused Addresses: $8000H to $FFFFH.

BASIC PARTS EXPLANATION:

1. Program Flash Memory

• Purpose: Non-volatile memory that stores the program code. It retains data even when the power
is off.
• Size: 32 KB in the Atmega32.
2. Instruction Register (IR)
• Purpose: Holds the current instruction being executed. It temporarily stores the opcode fetched
from the program memory.
3. Instruction Decoder
• Purpose: Decodes the opcode from the Instruction Register and generates control signals to
execute the instruction.
4. Stack Pointer (SP)
• Purpose: Points to the current top of the stack in SRAM, allowing for efficient data storage and
retrieval during function calls and interrupts.
5. Status Register
• Purpose: Holds flags that indicate the status of the microcontroller and the results of arithmetic
and logical operations (e.g., zero flag, carry flag).
6. Crystal Oscillator
• Purpose: Provides the clock signal for the microcontroller, which is essential for timing and
synchronization of operations.
7. Internal Oscillator
• Purpose: An alternative to the external crystal oscillator, providing clock signals without the need
for external components. It can be configured for different frequencies.
8. Two Wire Interface (TWI)
• Purpose: A communication protocol (also known as I²C) used for connecting low-speed devices in
a system, allowing multiple devices to communicate using two wires (data and clock).
9. Interrupt Unit
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9. Interrupt Unit
• Purpose: Manages external and internal interrupts, allowing the microcontroller to respond to
asynchronous events by pausing the current execution and handling the interrupt.
10. EEPROM (Electrically Erasable Programmable Read-Only Memory)
• Purpose: Non-volatile memory used for storing small amounts of data that must be preserved
between power cycles, such as configuration settings.
11. USART (Universal Synchronous/Asynchronous
Receiver/Transmitter)
• Purpose: Serial communication module that allows the microcontroller to send and receive data
over serial connections, supporting both synchronous and asynchronous communication.
12. SPI (Serial Peripheral Interface)
• Purpose: A high-speed serial communication protocol used to connect the microcontroller to
peripherals, allowing full-duplex communication over four wires (MOSI, MISO, SCK, SS).
13. Comparator Interface
• Purpose: Compares two analog voltages and can trigger an interrupt or set a flag based on the
comparison result. Useful for applications that require analog signal processing.

1. SBI (Set Bit in I/O Register)

• Purpose: The SBI instruction is used to set (make HIGH or 1) a specific bit in an I/O register.
• Syntax:

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SBI Register_Address, Bit_Number
○ Register_Address: The address of the I/O register where you want to set a bit.
○ Bit_Number: The bit position (0 to 7) you want to set within that register.
• Example:

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SBI PORTB, 2

This instruction sets the 2nd bit (bit 2) of PORTB to 1, making PB2 high.
• Explanation:
If PORTB = 00000000, after executing the above SBI command, it will become 00000100 (binary),
where PB2 is set to 1.
• Cycle Time:
The SBI instruction takes 2 clock cycles to execute.

2. CBI (Clear Bit in I/O Register)

• Purpose: The CBI instruction is used to clear (make LOW or 0) a specific bit in an I/O register.
• Syntax:

assembly
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CBI Register_Address, Bit_Number
○ Register_Address: The address of the I/O register where you want to clear a bit.
○ Bit_Number: The bit position (0 to 7) you want to clear within that register.
• Example:

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CBI PORTB, 2

This instruction clears the 2nd bit (bit 2) of PORTB, making PB2 low.
• Explanation:
If PORTB = 00000100, after executing the above CBI command, it will become 00000000 (binary),
where PB2 is cleared to 0.
• Cycle Time:
The CBI instruction also takes 2 clock cycles to execute.

Key Differences and Usage:

• SBI sets a bit to 1 (high).
• CBI clears a bit to 0 (low).
• They work directly on I/O registers (for example, PORTB, DDRB, etc.).
• They are efficient and frequently used in I/O operations, such as controlling pins or configuring
peripherals.

Visualizing SBI/CBI:
Let’s say PORTB = 00001100 (binary):
• SBI PORTB, 0:
PORTB becomes 00001101 (sets bit 0).
• CBI PORTB, 3:
PORTB becomes 00000100 (clears bit 3).

1. SBIC (Skip if Bit in I/O Register is Cleared)

• Purpose: The SBIC instruction skips the next instruction if a specific bit in an I/O register is cleared
(i.e., the bit is 0).
• Syntax:

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SBIC Register_Address, Bit_Number
Register_Address: The address of the I/O register.

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 ○ Register_Address: The address of the I/O register.
○ Bit_Number: The bit position (0 to 7) to check.
• Example:

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SBIC PINB, 0

In this example, the instruction checks if bit 0 of the PINB register is cleared (0). If it is cleared, the
next instruction is skipped.
• Explanation:
Let's say PINB = 00000000, i.e., PB0 is 0 (cleared). The SBIC instruction will skip the next
instruction.
If PINB = 00000001, i.e., PB0 is 1, the next instruction will be executed normally.
• Cycle Time:
○ If the bit is cleared (skip occurs), it takes 1 additional clock cycle to skip the next instruction.
○ If the bit is set, it takes 1 clock cycle (the next instruction is executed).

2. SBIS (Skip if Bit in I/O Register is Set)

• Purpose: The SBIS instruction skips the next instruction if a specific bit in an I/O register is set (i.e.,
the bit is 1).
• Syntax:

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SBIS Register_Address, Bit_Number
○ Register_Address: The address of the I/O register.
○ Bit_Number: The bit position (0 to 7) to check.
• Example:

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SBIS PINB, 0

In this example, the instruction checks if bit 0 of the PINB register is set (1). If it is set, the next
instruction is skipped.
• Explanation:
Let's say PINB = 00000001, i.e., PB0 is 1 (set). The SBIS instruction will skip the next instruction.
If PINB = 00000000, i.e., PB0 is 0, the next instruction will be executed normally.
• Cycle Time:
○ If the bit is set (skip occurs), it takes 1 additional clock cycle to skip the next instruction.
○ If the bit is cleared, it takes 1 clock cycle (the next instruction is executed).

Key Differences Between SBIC and SBIS:

• SBIC checks if the bit is cleared (0) and skips the next instruction if true.
• SBIS checks if the bit is set (1) and skips the next instruction if true.
• Both instructions are used to conditionally control the flow of a program, often in response to
hardware events or I/O pin states.

Visual Example for SBIC/SBIS:

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SBIC PINB, 0 ; Check if PB0 is cleared (0)
OUT PORTB, R16 ; If PB0 is cleared, skip this instruction
SBIS PINB, 1 ; Check if PB1 is set (1)
OUT PORTB, R17 ; If PB1 is set, skip this instruction
Flow of Control:
• If PB0 is 0, the instruction OUT PORTB, R16 will be skipped.
• If PB1 is 1, the instruction OUT PORTB, R17 will be skipped.

1. ROR (Rotate Right Through Carry)

• Purpose: ROR rotates the bits in a register right by 1 position, with the carry bit (in the Status
Register) being shifted into the most significant bit (MSB), and the least significant bit (LSB) is
shifted into the carry flag.
• Syntax:

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ROR Rd ; Rotate right the contents of Rd through the carry flag
• Example:

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R16 = 10010110
Carry = 1

After ROR R16:

○ R16 becomes 11001011 (the carry is shifted into the MSB, and the LSB is shifted into the
carry).
• Effects: The C (carry) and Z (zero) flags are affected.

2. ROL (Rotate Left Through Carry)

• Purpose: ROL rotates the bits in a register left by 1 position, with the carry bit being shifted into
the least significant bit (LSB), and the most significant bit (MSB) is shifted into the carry flag.
• Syntax:

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ROL Rd ; Rotate left the contents of Rd through the carry flag
• Example:

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 assembly
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R16 = 10010110
Carry = 1

After ROL R16:

○ R16 becomes 00101101 (the carry is shifted into the LSB, and the MSB is shifted into the
carry).
• Effects: The C (carry) and Z (zero) flags are affected.

3. LSL (Logical Shift Left)

• Purpose: LSL shifts all bits in a register left by 1 position. The MSB is shifted into the carry flag, and
a 0 is shifted into the LSB.
• Syntax:

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LSL Rd ; Logical shift left the contents of Rd
• Example:

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R16 = 10010110

After LSL R16:

○ R16 becomes 00101100, and the MSB 1 is stored in the carry flag.
• Effects: The C (carry), Z (zero), N (negative), and V (overflow) flags are affected.

4. LSR (Logical Shift Right)

• Purpose: LSR shifts all bits in a register right by 1 position. The LSB is shifted into the carry flag,
and a 0 is shifted into the MSB.
• Syntax:

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LSR Rd ; Logical shift right the contents of Rd
• Example:

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R16 = 10010110

After LSR R16:

○ R16 becomes 01001011, and the LSB 0 is stored in the carry flag.
• Effects: The C (carry), Z (zero), and N (negative) flags are affected.

5. ASR (Arithmetic Shift Right)

• Purpose: ASR shifts all bits in a register right by 1 position, just like LSR, but preserves the sign.
This means the MSB (sign bit) is kept unchanged while the other bits shift right.
• Syntax:

assembly

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 assembly
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ASR Rd ; Arithmetic shift right the contents of Rd
• Example:

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R16 = 10010110

After ASR R16:

○ R16 becomes 11001011 (the MSB remains 1, indicating a negative number, and the LSB
shifts into the carry).
• Effects: The C (carry), Z (zero), N (negative), and V (overflow) flags are affected.

6. SWAP (Swap Nibbles)

• Purpose: The SWAP instruction swaps the upper and lower nibbles (4 bits) of a register.
• Syntax:

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SWAP Rd ; Swap the nibbles of Rd
• Example:

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R16 = 10010110 ; Upper nibble = 1001, Lower nibble = 0110

After SWAP R16:

○ R16 becomes 01101001 (upper and lower nibbles swapped).
• Effects: None of the flags are affected.

Summary of Operations:
Instruction Operation Example Before Example After
ROR Rotate right through carry 10010110 (C=1) 11001011 (C=0)
ROL Rotate left through carry 10010110 (C=1) 00101101 (C=1)
LSL Shift left by 1 (logical) 10010110 00101100 (C=1)
LSR Shift right by 1 (logical) 10010110 01001011 (C=0)
ASR Shift right by 1 (arithmetic) 10010110 11001011 (C=0)
SWAP Swap nibbles 10010110 01101001

These instructions are useful for manipulating bit-level data, and they are often used in applications like
signal processing, encryption, and compression algorithms.

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WAP to 1] keep monitoring PB2 until it becomes high 2] when PB2 is high, write value $45 to PORTC and
also send a high-to-low pulse to PD3

ChatGPT said:
ChatGPT
Let's break down the problem and write the assembly code step by step for the ATmega32 to achieve
the following:
1. Monitor Pin PB2 (bit 2 of PORT B) until it becomes high.
• This can be done by checking the input pin register (PINB) in a loop.
• We keep looping until PB2 becomes high.
2. When PB2 becomes high:
• Write $45 to PORTC.
• Send a high-to-low pulse to Pin PD3 (bit 3 of PORT D).

Assembly Code Explanation:

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; Define I/O registers
.equ DDRC = 0x07 ; Data Direction Register for PORTC (0x07 in I/O space)
.equ PORTC = 0x08 ; Output register for PORTC (0x08 in I/O space)
.equ DDRD = 0x0A ; Data Direction Register for PORTD (0x0A in I/O space)
.equ PORTD = 0x0B ; Output register for PORTD (0x0B in I/O space)
.equ DDRB = 0x04 ; Data Direction Register for PORTB (0x04 in I/O space)
.equ PINB = 0x03 ; Input register for PORTB (0x03 in I/O space)
; Monitor PB2 until it becomes high
START:
SBIC PINB, 2 ; Skip the next instruction if PB2 is high
RJMP START ; If PB2 is low, keep looping back to START
; PB2 is now high, write $45 to PORTC
LDI R16, 0x45 ; Load value 0x45 into register R16
OUT PORTC, R16 ; Write value from R16 to PORTC
; Send a high-to-low pulse to PD3
SBI PORTD, 3 ; Set PD3 high (SBI = Set Bit in I/O register)
CBI PORTD, 3 ; Clear PD3 to low (CBI = Clear Bit in I/O register)
END:
RJMP END ; Loop indefinitely

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1. SUB Instruction (Subtract Without Carry)
• SUB Rd, Rr: This instruction subtracts the contents of register Rr from register Rd and stores the
result back in Rd.
Syntax:

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SUB Rd, Rr
Example:

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LDI R16, 5 ; Load R16 with 5
LDI R17, 3 ; Load R17 with 3
SUB R16, R17 ; Subtract R17 from R16 (R16 = R16 - R17, R16 = 2)
• After the execution of the SUB instruction, R16 will contain 2 (because 5 - 3 = 2).
Status Register (SREG) flags affected by SUB:
• Carry (C): Set if there is a borrow from the result.
• Zero (Z): Set if the result is zero.
• Negative (N): Set if the result is negative (sign bit is 1).
• Overflow (V): Set if there is a signed overflow in the result.
• Sign (S): Combined result of N and V.

2. SBC Instruction (Subtract with Carry)

• SBC Rd, Rr: Subtracts the contents of register Rr and the carry flag (C in the status register) from
register Rd and stores the result back in Rd. This is typically used for multi-byte subtraction where
a carry from the lower byte must be considered in the upper byte subtraction.
Syntax:

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SBC Rd, Rr
Example (Multi-byte subtraction):

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LDI R16, 0x01 ; Low byte
LDI R17, 0x00 ; High byte
LDI R18, 0x02 ; Low byte to subtract
LDI R19, 0x00 ; High byte to subtract
SUB R16, R18 ; Subtract low byte
SBC R17, R19 ; Subtract high byte with carry if needed
• After the execution:
○ SUB subtracts R18 from R16 (low byte), and if there’s a borrow (carry), it will affect the SBC
instruction.
SBC subtracts R19 and takes into account the carry.

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 ○ SBC subtracts R19 and takes into account the carry.

3. SUBI Instruction (Subtract Immediate from Register)

• SUBI Rd, K: This instruction subtracts an immediate value (constant) K from a register Rd (without
carry) and stores the result in Rd.
Syntax:

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SUBI Rd, K
Example:

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LDI R16, 10 ; Load R16 with 10
SUBI R16, 5 ; Subtract 5 from R16 (R16 = 10 - 5 = 5)
• After execution, R16 will hold the value 5.

SBIW Instruction (Subtract Immediate from Word)

SBIW stands for Subtract Immediate from Word. This instruction is used in AVR Assembly to subtract an
immediate value from a 16-bit register pair (which represents a word). The instruction directly modifies
the content of the register pair by subtracting the specified immediate value.
Syntax:

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SBIW Rd+1, K
• Rd: The low byte of the register pair (R0-R1, R2-R3, ..., R30-R31).
• Rd+1: The high byte of the register pair (the register following the low byte).
• K: The immediate value to subtract (0 to 63).
Example:
Let's say you want to subtract 5 from a 16-bit register pair:

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LDI R24, 0x00 ; Load the high byte with 0
LDI R25, 0x0A ; Load the low byte with 10 (0x0A)
SBIW R24, 5 ; Subtract 5 from R25:R24 (10 - 5 = 5)
• After execution:
○ R24 will contain 0x00 (high byte).
○ R25 will contain 0x05 (low byte), resulting in a 16-bit value of 0x0005.

@Show how we can use ROR to divide 48 by 8

ChatGPT said:

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ChatGPT said:
ChatGPT
To use the ROR (Rotate Right) instruction to divide a number by 8, we can leverage the fact that dividing
by 8 is equivalent to right-shifting the number three times (since 23=82^3 = 823=8). The ROR instruction
rotates the bits of a register to the right, which effectively performs a division by 2 for each rotation.
Step-by-Step Example: Dividing 48 by 8
1. Start with the value 48:
○ In binary, 48 is represented as 0011 0000.
2. Use ROR to rotate right three times:
○ Each ROR operation will shift the bits to the right, and the least significant bit (LSB) will wrap
around to the most significant bit (MSB).
Assembly Code Example
Here’s how you could implement this in AVR Assembly:

assembly
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LDI R16, 48 ; Load the value 48 into register R16 (binary: 0011 0000)
; Rotate right three times to divide by 8
ROR R16 ; First ROR (48 becomes 0001 1000)
ROR R16 ; Second ROR (24 becomes 0000 1100)
ROR R16 ; Third ROR (12 becomes 0000 0110)
; R16 now contains the result of 48 / 8, which is 6
Bit-by-Bit Breakdown
Let's see the result after each ROR operation:
1. Initial Value (48):
○ R16: 0011 0000 (48 in decimal)
2. After First ROR:
○ R16: 0001 1000 (24 in decimal)
3. After Second ROR:
○ R16: 0000 1100 (12 in decimal)
4. After Third ROR:
○ R16: 0000 0110 (6 in decimal)
Final Result
After performing three ROR instructions, the value in R16 will be 6, which is the result of dividing 48 by
8.

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