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Digital Electronics

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Syllabus

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• Core subjects for CS/IT Students

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• In GATE 7-8 Marks out of 100 Marks, and 5-6 questions on an average

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• Understanding Digital Electronics (History and Motive)

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• Most questions are Numerical
• Boolean Algebra Laws and Logic Gates

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• Needs less time, good scoring

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• Boolean Expression (SOP and POS) (Minimization)

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• Not asked in Industry
• Combinational Circuit

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• Sequential Circuit

• Number System and Numberwww.knowledgegate.in

Representation

•
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Basics

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Electrical engineering is a professional engineering discipline that generally
•

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Electronic engineering is an electrical engineering discipline where we work on
low voltage devices (such as semiconductor devices, especially transistor,
diodes and integrated circuits) to design electronic circuits, VLSI devices and

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deals with the study and application of electricity, electronics and
electromagnetism and heavy voltage devices like transformers, motors etc. systems.

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Electronic systems are generally of two types –
• Analog system in an analog representation, a continuous value is used to
denote the information. Analog signal is defined as any physical quantity
•

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Digital system – the information is denoted by a finite sequence of discrete
value or digits. Digital signal is defined as any physical quantity having discrete
values. E.g. digital watch, calculator, bp machine, thermometer etc.

Watch, radio.

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which varies continuously with respect to time. e.g. amplifier, cro, ecg.
•

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Early digital computers were used for numeric computation. The discrete
elements were the digits, from this application, the term digital computer
emerged.

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Advantage of Digital system

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1) Digital system are easy to design because they do not require sound engineering
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Conclusion

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• Digital systems have such a prominent role in everyday life that we refer to the

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and mathematical knowledge, uses only switching circuit. present technological period as digital age.

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2) Storage for long time and processing of information is easy.
3) They provide better accuracy and precision compared to analog devices, as

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• Digital system are used in communication, business, transactions, traffic control,
space guidance, medical treatment, weather forecasting, the internet, and

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digital devices are less affected by noise, sound, electric or magnetic field etc. many other commercial, industrial and scientific enterprises.

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4) Better modularity and easy fabrication. It means the of digital devices are very
small compared to analog devices. E.g. integrated circuits.

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5) Less cost.

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Disadvantage of Digital system

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• Only analog signal is available in the real world, so an extra hardware is required
to convert this analog signal to digital signal by using analog to digital converter.
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•
Boolean algebra

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The signal in most present day electronic digital •

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Boolean algebra
In mathematics and mathematical logic, Boolean algebra is the branch of

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system uses just two discrete values and are algebra in which the values of the variables are the truth values true and false,
usually denoted 1 and 0 respectively.

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therefore said to be binary.

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Boolean algebra was introduced by George Boole in
his first book The Mathematical Analysis of
•

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Instead of elementary algebra where the values of the variables are numbers,
and the prime operations are addition and multiplication. The main operations
of Boolean algebra are

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Logic (1847), and set forth more fully in his An • The conjunction and denoted as ∧
Investigation of the Laws of Thought (1854).

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• The disjunction or denoted as ∨
• The negation not denoted as ¬
•

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George boole introduced the concept of binary

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number system in the studies of the mathematical
theory of logic and developed its algebra known as
Boolean algebra.
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Turing Machine
• The Church-Turing thesis states that any algorithmic procedure that can be carried out by
human beings/computer can be carried out by a Turing machine.(1936)
•

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Digital System
In the 1930s, while studying switching circuits, Claude Shannon observed that one could also
apply the rules of Boole's algebra in this setting, and he introduced switching algebra as a

ideal theoretical model of a computer.

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• It has been universally accepted by computer scientists that the Turing machine provides an
•

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way to analyze and design circuits by algebraic means in terms of logic gates.

These logic concepts have been adapted for the design of digital hardware since 1938 Claude
Shannon (father of information theory), organized and systematized Boole’s work.

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von Neumann architecture

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• The von Neumann architecture is a computer architecture based on a 1945 description
by John von Neumann. That document describes a design architecture for an electronic digital

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computer with these components:

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• A processing unit that contains an arithmetic logic unit and processor registers

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• A control unit that contains an instruction register and program counter
• Memory that stores data and instructions

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• External mass storage
• Input and output mechanisms

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• Digital systems have two logic levels

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The lower voltage level is called a logic low or logic 0 (0-1 v), which Solution

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Q Design a digital system for a car manufacturing company, where we want to design a warning
signal for a car, there are three inputs, lights of the car(L), day or night(D), ignition (on/off).?

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represent digit 0. 1) Understand the problem- here we will Understand the definition of the problem

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Design the truth table –
• The higher voltage level is called a logic high or logic 1 (3.5-5 v), which
represent digit 1.

g ge Light
0
Day
0
Engine Warning
0

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0 0 1

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0 1 0
0 1 1

ow ow 1
1
0
0
0
1

Kn Kn
1 1 0
1 1 1
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2) Write the Boolean expression

• W (L, D, E) = ∑m (1, 4, 6, 7)

ateLight
0
Day
0
Engine Warning
0 0
3) Minimize Boolean expression
W = a’b’c + ab’c’ + abc’ + abc

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0
Day
0
Engine Warning
0 0

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0 0 1 1 0 0 1 1
ab a’b’ a’b ab ab’

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0 1 0 0 0 1 0 0
c 00 01 11 10

ed g 0
1
1
0
1
0
0
1
c’ 0
c 1
0

1
2

3
6

7
4

ed g 0
1
1
0
1
0
0
1

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1 0 1 0 1 0 1 0
• W (L, D, E) = ∏M (0, 2, 3, 5)
1 1 0 1 1 1 0 1

w w
W=
1 1 1 1 1 1 1 1

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4) Implement the expression using

logic gates, draw the

ateLight
0
Day
0
Engine Warning
0 0 Idempotent Law

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Boolean Algebra Laws

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implementation using logic gates 0 0 1 1 a.a=a
a+a=a

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W = ac’ + ab + a’b’c 0 1 0 0

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0 Associative law
0 1 1
a. (b. c) = (a. b). c

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1 0 0 1 a + (b + c) = (a + b) + c

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1 0 1 0
Commutative law
1 1 0 1 a. b = b. a

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a+b=b+a

Distributive law

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a. (b + c) = a. b + a. c
a + (b. c) = (a + b). (a + c)

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De-Morgan law
(a + b)’ = a’ . b’
(a. b)’ = a’ + b’

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Logic gate
• In electronics, a logic gate is a physical device implementing a Boolean function. Logic gate
performs a logical operation on one or more binary inputs signals and produces a single binary

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Identity law output signal. Logic gate is the basic building block from which many kinds of logic circuits can
a+0=a

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a. 0 = 0
be constructed.

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a+1=1 • Logic gates are primarily implemented using diodes or transistors acting as electronic
a. 1 = a switches, but can also be constructed using vacuum tubes, electromagnetic relays (relay logic),

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fluidic logic, pneumatic logic, optics, molecules, or even mechanical elements.
Complementation law

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0’ = 1
1’ = 0
a. a’= 0

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a+ a’ = 1

Involution law

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Kn Kn
(a’)’ = a

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Not Gate(Inverter)

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• It represents not logical operator is also known as inverter, it is a unary operator,
which simply complement the input.

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Truth Table

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Electromagnetic Relays

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Input
X
Output
Y = X’

n ow Pneumatic Logic

n ow 0
1

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OR Gate

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• It is a digital logic gate, that implements logical disjunction. The output will be 1. Idempotent Law: a + a = a

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• OR gate satisfy all the 3 rules idempotent, associative, and commutative.

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high if at least one of the input lines is high.
2. Associative law: a + (b + c) = (a + b) + c

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Truth Table 3. Commutative law: a + b = b + a

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Input Output

wl A
0
B
0
Y=A+B

wl
o
0 1

Kn
1
1
0
1

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And Gate

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• It is a digital logic gate, that implements logical conjunction. Output will be high if and only if
all input are high otherwise low.
1. Idempotent Law: a. a = a

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• And gate satisfy all the 3 rules idempotent, associative, and commutative.

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Truth Table
G 2. Associative law: a.(b. c) = (a. b). C

3. Commutative law: a. b = b. a

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Input Output
A B Y=A.B

wl 0
0
0
1

wl
Kn o 1
1
0
1

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Nor gate
The output will be high if and only if all inputs are low. Or simply a OR gate followed by an
invertor.
1. NOR with same gives _________
• (a + a)’ =

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•

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NOR gate is also called universal gate because it can be used to implement any other logic

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gate. We will cover this property extensively in the next chapter.

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2. NOR with zero gives _________
• (a + 0)’ =

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Truth Table
Input Output

wl A
0
B
0
Y = (A + B)’

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3. NOR with complement gives_________

w
• (a + a’)’ =

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1
1
1
0
1

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4. NOR with one gives________
• (a + 1)’ =
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• Idempotent and associative law
• (a + a)’ a
ate •

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NAND Gate
The output will be low if and only if all inputs are high. Or simply an and gate followed by an
invertor

• ((a + b)’+ c)’ (a + (b + c)’)’

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NAND gate is also called universal gate because it can be used to implement any other logic
gate. We will cover this property extensively in the next chapter.

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Truth Table
Input Output

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• Commutative law.
wl A
0
B
0
Y = (A . B)’

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• (a + b)’

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(b + a)’
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1
1
1
0
1

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1. NAND with ZERO give________

• (a. 0)’ =

ate • NAND with idempotent and associative

law
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2. NAND with COMPLEMENT give________
• (a. a’)’ =

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3. NAND with SAME give________
ed • ((a. b)’. c)’

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(a. (b. c)’)’
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• (a. a)’ =
• NAND with commutative law

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4. NAND with ONE give________

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• (a. b)’ (b. a)’
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EX-OR

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• For two inputs, output will be high if and only if both the input values are
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EX-OR

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• The XOR gate is a digital logic gate that gives High as output when the number

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different. of inputs High are odd.
• a ⊕ b = a’. b + a. b’

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0
B
0
C
0

ge a⊕b⊕c

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Truth Table
Input Output 0 0 1

wl A
0
B
0
Y=A⊕B

wl 0
0
1
1
1
0
0
1
0

Kn o 0
1
1
1
0
1

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1
1
0
1
1
1
0
1

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1. EX-OR with ZERO give________

• (a ⊕ 0) =

ate • EX-OR with idempotent law

• (a ⊕ a) a
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2. EX-OR with ONE give________
• (a ⊕ 1) =

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3. EX-OR with SAME give________
• (a ⊕ a) =

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• ((a ⊕ b) ⊕ c) (a ⊕ (b ⊕ c)) ed
• EX-OR with associative and commutative law.
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4. EX-OR with COMPLEMENT give_________

K• (a ⊕ a’) =
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• (a ⊕ b) (b ⊕ a)

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Marks)
x # 0 = x,
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Q Consider the Boolean operator with the following properties: (GATE-2016) (1
Marks)

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Q The binary operator # is defined by the following truth table. (GATE-2015) (1

Which of the following is true about the binary operator # ?

x # 1 = x’,
x#x=0
and x # x’ = 1

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b) Commutative but not associative
c) Not commutative but associative

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Then x # y is equivalent to d) Neither commutative nor associative
a) xy’ + x’y b) xy’ + x’y’ c) x’y + xy d) xy + x’y’

wl p
0

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q P#q
0 0

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0 1 1

Kn Kn
1 0 1
1 1 0

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 ate
Q Let ⊕ denote the Exclusive OR (XOR) operation. Let ‘1’ and ‘0’ denote the binary
constants. Consider the following Boolean expression for F over two variables P
and Q.
Q A ⊕ P ⊕ A ⊕ P ⊕ B ⊕ P ⊕ B ⊕ P ⊕ B?

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F(P, Q) = ( ( 1 ⊕ P) ⊕ (P ⊕ Q) ) ⊕ ( (P ⊕ Q) ⊕ (Q ⊕ 0) )

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The equivalent expression for F is

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(A) P + Q
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(GATE-2014) (2 Marks)

(B) (P + Q)’

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o
(C) P ⊕ Q

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(D) (P ⊕ Q)’

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• a ⊙ b = a’. b’ + a. b
EX-NOR

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• For two input, output will be high if and only if both the input values are same

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EX-NOR

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• The EX-NOR gate is a digital logic gate that gives output High when the number
inputs low are even.

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Truth Table
A
0
B
0
C
0

geG a⊙b⊙c

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A
0
Input

edB
0
Output
Y=A⊙B

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0
0
0
0
1
1
ed1
0
1

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1
1
1
0
1

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1
1
0
0
1
0
1
0

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1. EX-NOR with ZERO give_________

• (a ⊙ 0) =

ate • EX-NOR with idempotent law

• (a ⊙ a) a
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2. EX-NOR with ONE give________
• (a ⊙ 1) =

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3. EX-NOR with SAME give________
• (a ⊙ a) =

w ed • ((a ⊙ b) ⊙c)
w
(a ⊙ (b ⊙ c))ed
• EX-NOR with associative and commutative law
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Kn o
4. EX-NOR with COMPLEMENT give_________
• (a ⊙ a’) =
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• (a ⊙ b) (b ⊙ a)

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(GATE-2007) (2 Marks)
Consider the following expressions P, Q and R.

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Q Define the connective * for the Boolean variables X and Y as: X * Y = XY + X’ Y’. Let Z = X * Y. A
0
B
0
C
0
a⊕b⊕c a⊙b⊙c

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P: X = Y⋆Z Q: Y = X⋆Z R: X⋆Y⋆Z=1

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X Y X⊙Y=Z
0 0 1

ed g 0
0
1
1
0
1

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wl 1

wl
0 0

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Which of the following is TRUE?

n
(A) Only P and Q are valid
(B) Only Q and R are valid.
(C) Only P and R are valid.
(D) All P, Q, R are valid.
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1
1
1
Kn o 0
1
1
1
0
1
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A B C

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Conclusion

a⊕b⊕c a⊙b⊙c a ⊕ b = a’ b = a b’ = (a
t
b)’ = (a’e
Relation of EX-OR and EX-NOR

a b’)’ = a’ b’ = (a’ b)’ = (a b’)’

0
0
0
0
0
1
0
1
0

geG0
1
1
0
1
1

geG
ed ed
0 1 1 0 0
1 0 0 1 1
1
1

wl 0
1
1
0
0
0
0
0

wl
a ⊙ b = a’ b = a b’ = (a b)’ = (a’ b’)’ = a’ b’ = (a’ b)’ = (a b’)’

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1 1 1 1 1

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• Ex-or and ex-nor gate behaves as a complement of each other if the number of input variable
is even.
• Ex-or and ex-nor gate behave same if no of input variables are odd.
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(A) (x ⊕ y) ⊕ z = x ⊕ (y ⊕ z)

ate
Q Which one of the following is NOT a valid identity? (GATE-2019) (2 Marks)
(B) (x + y) ⊕ z = x ⊕ (y + z) respecmvely.
Which one of the following is NOT CORRECT? (GATE-2018) (2 Marks)
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Q Let ⊕ and ⊙ denote the Exclusive OR and Exclusive NOR operamons,

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geG (A) (P ⊕ Q)’ = P ⊙ Q (B) Pn ⊕ Q = P ⊙ Q

geG
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(C) x ⊕ y = x + y, if xy = 0 (D) x ⊕ y = (xy + xʹyʹ)ʹ (C) Pn ⊕ Qn = P ⊕ Q (D) (P ⊕ Pn ) ⊕ Q = (P ⊙ Pn ) ⊙ Qn

wl wl
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(2 Marks)
ate
Q Let, X1 ⊕ X2 ⊕ X3 ⊕ X4 = 0 where X1, X2, X3, X4 are Boolean variables, and ⊕ is
the XOR operator. Which one of the following must always be TRUE? (GATE-2016) 0
1
X1

0
0
X2

0
0
X3

0
0
X4

0
1
X1 ⊕ X2 ⊕ X3 ⊕ X4 = 0

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X1X2X3X4 = 0 X1X3+X2 = 0 X’1 ⊕ X’3 = X’2 ⊕ X’4 X1 + X2 + X3 + X4 = 0

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2 0 0 1 0
a) X1X2X3X4 = 0 b) X1X3+X2 = 0 3 0 0 1 1

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4 0 1 0 0

g g
5 0 1 0 1
6 0 1 1 0

d d
7 0 1 1 1
8 1 0 0 0

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9 1 0 0 1

l l
10 1 0 1 0
c) X’1 ⊕ X’3 = X’2 ⊕ X’4 d) X1 + X2 + X3 + X4 = 0 11 1 0 1 1
12 1 1 0 0

n ow 13
14
15

n
1
1
1

ow 1
1
1
0
1
1
1
0
1

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and y? (GATE-2013) (1 Marks)

(A) xy + x’ y’
ate
Q Which one of the following expressions does NOT represent exclusive NOR of x

(B) x ^ y’ where ^ is XOR

(exclusive NOR) gate? (GATE-2011) (1 Marks)

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Q Which one of the following circuits is NOT equivalent to a 2-input XNOR

geG geG
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(C) x’ ^ y where ^ is XOR (D) x’ ^ y’ where ^ is XOR

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x+y+z=1

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Q The simultaneous equations on the Boolean variables x, y, z and w,

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Boolean Expressions

a
• Boolean expressions are the method using which we save the information about the Boolean
function, that when we get value 1 and when we get value 0 as output.

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xy = 0

xz + w = 1

ge understand where the output is 1 and when it is zero.

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• So, we convert the truth table of the function into an expression, reading which we can

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xy + z’w’ = 0 Light Day Engine Warning
0 0 0 0 • W = a’b’c + ab’c’ + abc’ + abc

l l
have the following solution for x, y, z and w, respectively. (GATE-2000) (2 Marks) 0 0 1 1
(A) 0 1 0 0 0 1 0 0

ow
(B) 1 1 0 1
(C) 1 0 1 1
(D) 1 0 0 0

n n
0
1
1
1
ow 1
0
0
1
1
0
1
0
0
1
0
1

K www.knowledgegate.in K 1 1 1 1

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• There are two popular approaches for writing these expressions.
• Sum of Product (SOP) (which remember when we get 1)

a
• Product of Sum (POS) (which remember when we get 0)
both SOP and POS.

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• Power of SOP and POS bother are same, i.e. any Boolean functions can be represented using

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• Mathematically speaking we should choose (0 or 1), whatever is less in number because then
• Make a note of this as we are studying Boolean function remembering both 0 and 1 is not required, so

e
it will be easy to represent.
we can either concentrate on 0 or 1.

g
• W (L, D, E) = ∑m (1, 4, 6, 7)

ge
ed ed
Light Day Engine Warning A B f1 = f2 =
0 0 0 0 • W (L, D, E) = ∏M (0, 2, 3, 5)

l l
0 0 1 1 0 0 0 0
0 1 0 0 0 1 1 0
0
1

ow 1
0
1
0
0
1

ow 1
1
0
1
1
1
0
1

Kn Kn
1 0 1 0
1 1 0 1
1 1 1 1

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Marks)

at
(C) X ⊕ Y
e
Q The truth table represents the Boolean function (GATE-2012) (1

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SOP (sum of product)
• A sum of product form expression contains product terms (AND terms) which are sum
(OR) together, that’s why called sum of product.

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(A) X (B) X+Y (D) Y

ge ge
• Each product terms (AND terms) consists of one or more literals (variables) appearing
either in complements or uncomplemented form. E.g. a’b + b’c’ + abc

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• A product term which contains all the literals (variables) either in complemented or
X Y F (X, Y)

wl 0
0
0
1
0
0

wl
uncomplemented form is called minterm.

• In a n variable function, there will be 2n minterms.

o o
1 0 1

Kn Kn
1 1 1

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• The result of a product term must always be 1, If a literal is having value 1 then it is ok, but if
not, then we complement those which is 0, it to make it 1.
• There is only 1 input sequence of variables for any minterm on which the output is 1, so it
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Canonical logic forms
• Either in POS or SOP form it is not essential that all product or sum terms contains all the
literals.
represents information.

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• Then the sum of all product term(minterm) to from a function, and functions will have value 1,
if at least one of the product term(minterm) is 1.

geG
• Canonical SOP form: - In a sum of product form expression, if each AND term (product term)
consists all the literals(variables) appearing either in complements or uncomplemented form.
E.g. a’bc + ab’c’ + abc. Then the form is said to be canonical SOP.

l
Binary Representation
000
001
ed
Sequence
0
1
Minterm
a’b’c’
a’b’c
Designation
m0
m1
l ed
n ow 010
011
100
101
2
3
4
5
a’bc’
a’bc
ab’c’
ab’c
m2
m3
m4
m5

n ow
K 110
111
6
7
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abc’
Abc
m6
m7
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te
Q The minterm expansion of f(P, Q, R) = PQ + QR’ + PR’ is (GATE-2010) (2 Marks)

a te
Q Consider a function and find no of minterms F (a, b, c) = a + a’b + abc + bc’?

a
geG geG
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(A) m2 + m4 + m6 + m7

wl
(B) m0 + m1 + m3 + m5

(C) m0 + m1 + m6 + m7

wl
Kn o
(D) m2 + m3 + m4 + m5

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te
POS (Product of Sum)

a
• A product of sum (POS) form of expression contains OR (sum) terms which are AND (product)
together, that’s why called product of sum expression.
te
• A OR (sum) term which contains all the literals(variables) either in complemented or
uncomplemented form is called maxterm. In a n variable function, there will be 2n maxterms.

a
eG
• Each OR term (sum term) consists of one or more literals(variables) appearing either in

g
complemented or uncomplemented form. (a’ + b). (b’ + c’). (a + c)
Binary Sequence Maxterm

geG Designation

ed ed
Representation
000

l l
0 a+b+c M0
001 1 a + b + c’ M1

w w
010 2 a + b’ + c M2
011 3 a + b’ + c’ M3

Kn o www.knowledgegate.in Kn o 100
101
110
111
4
5
6
7
a’ + b + c
a’ + b + c’
a’ + b’ + c
a’ + b’ + c’

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M4
M5
M6
M7

ate
• The result of the OR (sum) term must be 0, so If a variable is having value 0 then it is ok, but if
not then we complement the variable it to make it 0.

te
Canonical logic forms

a
• Canonical POS form: - In a product of sum form expression, if each OR term (sum term)
consists all the literals(variables) appearing either in complements or uncomplemented form.

G G
• There is only 1 input sequence for which the output of a Maxterm is 0. Because, it requires all E.g. (a’ + b + c). (a + b’ + c’). (a + b + c). Then the form is said to be Canonical POS form.
values as zero.

ge
• Then the product of all sum term (maxterm), from a function, and functions will have a value

ge
ed ed
0, if any of the sum term(maxterm) is 0.
Binary Representation Sequence Maxterm Designation

wl 000
001
010
011
0
1
2
3
a+b+c
a + b + c’
a + b’ + c
a + b’ + c’
M0
M1
M2
M3

wl
Kn o 100
101
110
111
4
5
6
7
a’ + b + c
a’ + b + c’
a’ + b’ + c
a’ + b’ + c’

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M4
M5
M6
M7

Kn o www.knowledgegate.in
 te
Q Given the function F = Pʹ+QR, where F is a function in three Boolean variables P, Q and R and Pʹ
=! P, consider the following statements. (GATE-2015) (2 Marks)
S1: F = Σ (4, 5, 6)

a te
No of functions possible

a
Q With n-Boolean variables how many different Boolean functions are possible?
S2: F = Σ (0, 1, 2, 3, 7)

S3: F = Π (4, 5, 6)

geG geG
ed ed
S4: F = Π (0, 1, 2, 3, 7)

wl
Which of the following is true?
(A) S1-False, S2-True, S3-True, S4-False

wl
o
(B) S1-True, S2-False, S3-False, S4-True

Kn
(C) S1-False, S2-False, S3-True, S4-True

(D) S1-True, S2-True, S3-False, S4-False

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ate
No of functions possible

Q With n-Boolean variables how many different Boolean functions are possible?
te
Q What is the maximum number of different Boolean functions

a
involving n Boolean variables? (GATE-2007) (1 Marks)

G G
Solution: with n binary variable we can generate 2n combinations. And as we know that a a) n2 b) 2n c) 22^n d) 2n^2
Boolean function can also have only 2 possible values either 0 or 1, so total number of different
functions possible will be 2^(2n).

ge
Similarly, we can generalize this idea as x^(yz) are the total number of functions possible, x is the

d
nature of the function, y is the nature of the variable and z is the number of variables.

d ge
wl e wl e
Kn o www.knowledgegate.in Kn o www.knowledgegate.in

te
Complementation

a
• Let us consider a function f(a, b, c, d,……, 0, 1, +, . ), then the complement of the the function.

ate
• We can directly put a bar of the entire Boolean expression to find complement of

G G
function is defined as f’(a’, b’, c’,……, z’, 1, 0, ., +).
• We can also directly deal in minterms and maxterm to write complement

e
• i.e. When all the variables are replaced by their compliments, 0à1,1à0, or

g
àand, and à or, then we will be called them compliment of a function.
function.

ge
ed ed
OR NOR
AND NAND

wl EX-OR

wl Complement EX-NOR

Kn o www.knowledgegate.in Kn o www.knowledgegate.in

te
Q Consider the following Boolean expression F=(X+Y+Z)(X'+Y)(Y’+Z) Which of the

a
following Boolean expressions is/are equivalent to F' (complement of F)? (GATE
2021)(2 MARKS)
ate
Duality
• Let us consider a function f(a, b, c, d,……,z,0,1,+,. ), then the dual of the function

G G
is defined as fd(a, b, c,……,z,1,0,..,+).
(A) (X'+Y'+Z')(X+Y')(Y+Z’)

(B) XY’+Z’

ge ge
• When the nature of variable remains same but 0 à 1, 1 à 0, or à and, and à
or, then they are called dual functions.

ed ed
(C) (X+Z')(Y'+Z’)

wl
(D) XY'+YZ'+X'Y'Z'
a
L0H

wl b
L0H L0H L0H

Kn o www.knowledgegate.in
L0H

Kn
H1L
H1Lo H1L
L0H
H1L
H1L
H1L
H1L
L0H
L0H
H1L
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ate
• When we take dual of a function, then the functionality of a function remains the same but a
positive logic system is transformed to negative logic system.

te
Neutral Function

a
• A function f is said to be neutral if, it has equal number of minterms and

G G
• If a function works corrects in positive logic system, then it must also work correct in negative maxterms.
logic system as it do not depends on magnitude.
OR
NOR
AND
NAND

ge ge
ed ed
EX-OR EX-NOR

l l
dual

ow ow
Kn www.knowledgegate.in Kn www.knowledgegate.in
 ate
Self-Dual

• A function f is said to be self-dual if both the functions and its dual are same.
Q which of the following functions are self-dual?
f (a, b, c) = ∑m (0, 3)

ate
• f = fD
• F (a, b, c) = ab + bc + ca
geG F (a, b, c) = ∑m (0, 1, 6, 7)

F (a, b, c) = ∑m (0, 1, 2, 4)

geG
ed ed
F (a, b, c) = ∑m (3, 5, 6, 7)

wl wl
Kn o www.knowledgegate.in Kn o www.knowledgegate.in

ate
Q how to check weather a function is self-dual or not?
1) check whether function is neutral or not i.e. (minterm = maxterm)

te
Q The dual of a Boolean function F (X1, X2, ..., Xn, +, *, '), written as FD, is the same

a
expression as that of F with + and * swapped. F is said to be self-dual if F = FD. The
number of self-dual functions with n Boolean variables is. (GATE-2014) (1 Marks)

G G
2) A self-dual function does not have any mutually exclusive terms. So in every pair of mutual
exclusion term, we can pick only 1 minterm. a) 2n b) 2(n-1) c) 2(2014^n) d) 2(2^(n-1))

ge
3) for n variable functions total 2n minterms are possible, so we will have 2n-1 pair of mutually

d
exclusive minterms, in every pair of mutually exclusive minterms we have two choice so, For n
variable function total number of 2^(2(n-1)) self-dual functions are possible.

d ge
0ßà7
1ßà6

wl e wl e
o o
2ßà5
3ßà4

Kn
e.g. of Mutual exclusive min terms

www.knowledgegate.in Kn www.knowledgegate.in

Orthogonal

ate
• A function f is said to be orthogonal if the compliment and dual of the

ate
Q how to check weather a function is orthogonal or not?
1) check whether function is neutral or not i.e. (minterm = maxterm)

G G
function are same. A function can never be both orthogonal and self- 2) we can choose any pair of mutual exclusive terms, but the minterms and its complement, both

e
must be present.

e
dual because it will imply the function is same to its compliment,

g g
which is never possible. 3) If there is a function f of n-variables, so we will have 2n-1 pair of mutually exclusive minterms,

ed ed
out of which we have to select exactly half of the pairs (2n-2), then (2n-1)C(2n-2) different
• f’= fd orthogonal functions are possible.

wl
• f(a, b, c) = a’b’c’ + abc + a’bc’ + ab’c
0ßà7
1ßà6

wl
o o
2ßà5
3ßà4

Kn Kn
e.g. of Mutual exclusive min terms

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Q which of the following functions are self-dual?

f (a, b, c) = ∑m (0, 3)

ate •

ate
Simplification of Boolean expression
After deriving a Boolean expression from the truth table next important step is to minimise it,
so that the cost of implementation into hardware and delay because of additional gates can
F (a, b, c) = ∑m (0, 1, 6, 7)

F (a, b, c) = ∑m (0, 1, 2, 4)

geG 1) Using Karnaugh-map

geG
be reduced. There are following methods for simplifying a Boolean expression

ed ed
2) Using Algebraic method (Boolean Laws)
F (a, b, c) = ∑m (3, 5, 6, 7)

wl wl
Kn o www.knowledgegate.in Kn o www.knowledgegate.in

ate
• Maurice Karnaugh (born 4 October 1924)
is an American physicist, mathematician
and inventor known for the Karnaugh
ate
Karnaugh Map
• Problem with other methods: - The algebraic procedure using Boolean laws and rules for
minimising Boolean expression becomes difficult when a function becomes complex, because

geG map used in Boolean algebra.

• Age: 96

geG
we have to identify where is the scope of minimization based on some Boolean laws and It is
difficult to understand where we reach saturation point or not.

ed ed
a + a’b + a’b’c + a’b’c’d’

wl wl
Kn o www.knowledgegate.in Kn o www.knowledgegate.in
• Karnaugh map is one of the most extensively used tool, it is a graphical representation,
represents truth table by pictorial form, provides a systematic method for simplifying or

a
minimizing a Boolean expression. For a n-variable k-map, there will be 2n cells addressed by a
te cd
ab a’b’ a’b ab ab’
00 01 11 10
ate ab
cd

G G
gray code. Each cell corresponds to one minterm or maxterm.
c’d’ 00

e e
a b c d F 0 4 12 8
ab

g g
0
1
0
0
0
0
0
0
0
1
c’d 01 1 5 13 9
cd

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2
3
0
0
0
0
1
1
0
1
cd 11 3 7 15 11
4 0 1 0 0
cd’ 10

l l
5 0 1 0 1 2 6 14 10
6 0 1 1 0
7 0 1 1 1
8
9
10

ow 1
1
1
0
0
0
0
0
1
0
1
0

ow
Kn Kn
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1

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cd
ab a’b’ a’b ab ab’
00 01 11 10
ate ab
cd c’d’ c’d cd cd’
00 01 11 10 bc
ad a’d’ a’d ad ad’
00 01 11 10
ate ca
db d’b’ d’b db db’
00 01 11 10
c’d’ 00
c’d 01
0

1
4

5
12

13
8

g
9

eG a’b’ 00
a’b 01
0

4
1

5
3

7
2

6
b’c’ 00
b’c 01
0

2
1

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9

10
8

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c’a 01
0

8
4

12
5

13
1

d d
cd 11 3 7 15 11 ab 11 12 13 15 14
bc 11 6 7 15 14 ca 11 10 14 15 11

e e
cd’ 10 ab’ 10 bc’ 10 ca’ 10

l l
2 6 14 10 8 9 11 10 4 5 13 12 2 6 7 3

n ow n ow
K www.knowledgegate.in K www.knowledgegate.in

c
ab a’b’ a’b ab ab’
00 01 11 10
ate a
bc b’c’
00
b’c bc bc’
01 11 10
a a’ a

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G G
b 0 1 a 0 1

e e
c’ 0 0 2 6 4 a’ 0 b’ a’
0 1 3 2 0 0
c 1

g g
0 2 0 1
1 3 7 5 a 1 4 5 7 6

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b 1 1 3
a 1 2 3
a a’ a

wl bc

b’c’ 00
0
0
1
4

wl
Kn o b’c
bc
bc’
01
11
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1

2
5

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5-Variable K-Map

ate 6-Variable K-Map

ate
a'
bc b’c’ b’c bc bc’
a
bc

geG b’c’ b’c bc bc’

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cd c’d’ c’d cd cd’
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cd

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de 00 01 11 10 de 00 01 11 10 ef 00 01 11 10 ef 00 01 11 10
d’e’ 00 0 4 12 8
d’e’ 00 16 20 28 24
e’f’ 00 0 4 12 8
e’f’ 00 16 20 28 24

l l
d’e 01 1 5 13 9 d’e 01 17 21 29 25 e’f 01 1 5 13 9 e’f 01 17 21 29 25
de 11 3 7 15 11 de 11 19 23 31 27 ef 11 3 7 15 11 ef 11 19 23 31 27
de’ 10 de’ 10 ef’ 10 ef’ 10

w w
2 6 14 10 18 22 30 26 2 6 14 10 18 22 30 26

ab' ab

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cd

e’f’ 00
e’f 01
ef 11
ef’ 10
c’d’
00
32

33

35

34
c’d cd cd’
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36

37

39

38
44

45

47

46
40

41

43

42
ef

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cd

e’f’ 00
e’f 01

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c’d’
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48

49

51

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50
c’d cd cd’
01 11 10
52

53

55

54
60

61

63

62
56

57

59

58

a'b’c’
7-Variable K-Map
a’b’c

ate a’bc’ a’bc ef

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cd

00
a'b’c’d’
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cd
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c’d’
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c’d’
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cd c’d’
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cd c’d’
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cd c’d’
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cd c’d’
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01
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16-31 e’f
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01
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32-47 e’f
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01
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48-63
ef’ 10 ef’ ef’ ef’

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10 10 10
e’f’ 00 e’f’ 00 e’f’ 00 e’f’ 00
e’f 01 0-15 e’f 01
16-31 e’f 01
32-47 e’f 01
48-63 a’bc’d’ a’bc’d a’bcd’ a’bcd

g g
ef 11 ef 11 ef 11 ef 11
cd c’d’ c’d cd cd’ cd c’d’ c’d cd cd’ cd c’d’ c’d cd cd’ cd c’d’ c’d cd cd’
ef’ 10 ef’ 10 ef’ 10 ef’ 10 ef 00 01 11 10 ef 00 01 11 10 ef 00 01 11 10 ef 00 01 11 10

ed ed
e’f’ 00 e’f’ 00 e’f’ 00 e’f’ 00
ab’c’ ab’c abc’ abc e’f
ef
01
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64-79 e’f
ef
01
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ef 11
96-111 e’f 01
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112-127
cd c’d’ c’d cd cd’ cd c’d’ c’d cd cd’ cd c’d’ c’d cd cd’ cd c’d’ c’d cd cd’ ef’ 10 ef’ 10 ef’ 10 ef’ 10

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ef 00 01 11 10 ef 00 01 11 10 ef 00 01 11 10 ef 00 01 11 10
e’f’ 00 e’f’ 00 e’f’ 00 e’f’ 00 ab’c’d’ ab’c’d ab’cd’ ab’cd
e’f 01
64-79 e’f 01
80-95 e’f 01
96-111 e’f 01
112-127
cd c’d’ c’d cd cd’ cd c’d’ c’d cd cd’ cd c’d’ c’d cd cd’ cd c’d’ c’d cd cd’

w
ef ef

w
00 01 11 10 00 01 11 10 ef 00 01 11 10 ef 00 01 11 10
ef 11 ef 11 ef 11 ef 11 e’f’ 00 e’f’ 00 e’f’ 00 e’f’ 00
ef’ 10 ef’ 10 ef’ 10 ef’ 10 e’f 01
128-143 e’f 01
144-159 e’f 01
160-175 e’f 01
176-191

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ef 11 ef 11 ef 11 ef 11
ef’ 10 ef’ 10 ef’ 10 ef’ 10

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abc’d’ abc’d abcd’ abcd
cd c’d’ c’d cd cd’ cd c’d’ c’d cd cd’ cd c’d’ c’d cd cd’ cd c’d’ c’d cd cd’
ef 00 01 11 10 ef 00 01 11 10 ef 00 01 11 10 ef 00 01 11 10
e’f’ 00 e’f’ 00 e’f’ 00 e’f’ 00
e’f 01
ef 11 192-207 e’f 01
ef 11 208-223 e’f 01
ef 11 224-239 e’f 01
ef 11 240-255
ef’ 10 ef’ 10 ef’ 10 ef’ 10

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 t
K-Map for POS

a e K-Map for POS

ate
c+d
a+b

geG c+d
a+b a+b a+b’ a’+b’ a’+b

c+d 0+0
0+0 0+1 1+1 1+0

geG
ed ed
0 4 12 8

c+d’ 0+1 1 5 13 9

wl wl
c’+d’ 1+1
c’+d 1+0
3

2
7

6
15

14
11

10

Kn o www.knowledgegate.in Kn o www.knowledgegate.in

• Minimal function: - A function is said to be

minimal if it is representing the function
expression, if it is using minimal no of
ate cd
ab a’b’ a’b ab ab’
00 01 11 10 function.
Don’t care condition

ate
• Don’t care cases are those cases which can never occur logically in that

literals to represent the function.

• Rules of grouping: -
1. Every minterm must be covered

geG c’d’ 00
c’d 01
0

1
4

5
12

13
8

eG
• It is not essential to cover don’t care conditions, but if don’t care are helping to
generate bigger prime implicants, then we can use them.

g
ed
2. Group must have contiguous Cells(circular)
3. Group must be in horizontal or vertical

l
fashion(circular)
4. Number of cells in a group must be in power of 2
cd11
cd’ 10
3

2
7

6
15

14
11

10

l ed
w
5. Will Try to make largest group possible, so that

o
number of literals in the expression can be
reduced

n
6. Can also take don’t care if it helps in creating the

n ow
Klarger groups, other wise don’t care.
7. Will consider new implicant if it is covering some
new minterm. www.knowledgegate.in K www.knowledgegate.in

cd
ab a’b’ a’b ab ab’
00 01 11 10
ate cd
ab a’b’ a’b ab ab’
00 01 11 10
ate
c’d’ 00
c’d 01 D
1

g
D
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c’d’ 00
c’d 01
1

geG
1 1 1

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cd 11 1 1 cd 11 1 1 1
cd’ 10 1 1 cd’ 10 1

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Kn o www.knowledgegate.in Kn o
First try to cover those minterms which do not have an option.
www.knowledgegate.in

te
For some functions more than one minimal Boolean expression are possible

a te
• Implicants: - Collection of adjacent minterms are called implicants.

a
• Prime Implicant (PI): - Implicant is called Prime implicant (PI) if it is not subset of any other

G
ab a’b’ a’b ab ab’

G
implicant(group). (overlapping is allowed).
• We will always try to find Prime Implicant
cd
c’d’ 00 D
e
00 01 11 10

g D f (a, b, c, d) = ∑m {4,5,6,7,8,9,10,11,13,14}

ge
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ab a’b’ a’b ab ab’
c’d 01 1 1 D
cd 00 01 11 10

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0 4 12 8

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ate
Essential Prime Implicant (EPI)
• If a prime implicant (PI) have some unique minterm which no other prime
te
Q f(a, b, c) = ∑m {1,2,3,4,5}, find Number of PI, Number of EPI, Number of literals

a
are there in minimal expression, Number of different minimal expression possible?

G G
implicant covers then, it is called essential prime implicant (EPI).
1. Number of PI

expression.

ge
• Essential prime implicant (EPI) must always be present in the minimal Boolean ab a’b’ a’b ab ab’

ge 2. Number of EPI

ed ed
c 00 01 11 10 3. Number of different minimal
expression possible

wl c’ 0
c 1

wl 0

1
2

3
6

7
4

5
4. Number of literals are there in
minimal expression

Kn o www.knowledgegate.in Kn o www.knowledgegate.in
 te
Q Consider the minterm list form of a Boolean function F given below.

a
F (P, Q, R, S) = ∑m (0, 2, 5, 7, 9, 11) + d (3, 8, 10, 12, 14)
Here, m denotes a minterm and d denotes a don’t care term. The number of essential prime
10) is ________. (GATE-2015) (1 Marks)
(A) 2 (B) 3 (C) 4
ate
Q The total number of prime implicants of the function f(w, x, y, z) = Σ(0, 2, 4, 5, 6,

(D) 5

G G
implicants of the function F is ______. (GATE-2018) (2 Marks)

ge wx w’x’ w’x wx wx’

ge
ed ed
pq p’q’ p’q pq pq’ yz 00 01 11 10
rs

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r’s’ 00
00 01 11 10
0 4 12 8

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y’z’ 00
y’z 01
0

1
4

5
12

13
8

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r’s 01
rs 11
rs’ 10
1

2
5

6
13

15

14
9

11

10

www.knowledgegate.in Kn o
yz 11
yz’ 10
3

2
7

6
15

14
11

10

www.knowledgegate.in

(GATE-2004) (1 Marks)
f (a, b, c) = a’c + ac’ + b’c
ate
Q Which are the essential prime implicants of the following Boolean function? Q Consider the functions given below ?
ab a’b’ a’b ab ab’

ate
G G
c 00 01 11 10
(A) a’c and ac’ (B) a’c and b’c
(C) a’c only

ab a’b’ a’b ab ab’

d ge(D) ac’ and bc’ c’
c
0
1
1

1. Number of PI
1
1 1
1
1

d ge
c
c’ 0
wl 00 01 11 10
e wl
2. Number of EPI

3. Number of different minimal e

o o
0 2 6 4
expression possible
c 1

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n
4. Number of literals are there in

K minimal expression

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Q Consider the functions given below ?

1. Number of PI

ate ab a’b’ a’b ab ab’ ab a’b’ a’b ab ab’

ate
G G
2. Number of EPI
cd 00 01 11 10 cd 00 01 11 10

e e
c’d’ 00 1 1 c’d’ 00 1 D D 1

g g
3. Number of different minimal expression possible c’d 01 1 1
c’d 01 D

ed ed
cd 11 1 1
4. Number of literals are there in minimal expression cd 11
cd’ 10 1 1

wl wl cd’ 10 1 D

Kn o www.knowledgegate.in Kn o www.knowledgegate.in

ab a’b’ a’b ab ab’

ate ab a’b’ a’b ab ab’

ate
G G
cd 00 01 11 10 cd 00 01 11 10

e e
c’d’ 00 1 1 c’d’ 00 D 1 1
c’d 01
cd 11
D
D

ed g1
1
c’d 01
cd 11 1
1
D
D
D

ed g
wl
cd’ 10 1 1 D

wl cd’ 10 D D

Kn o www.knowledgegate.in Kn o www.knowledgegate.in

ab a’b’ a’b ab ab’

ate ate
Q Given f (w, x, y, z) = Σm (0,1,2,3,7,8,10) + Σd (5,6,11,15), where d represents the don’t-care
condition in Karnaugh maps. Which of the following is a minimum product-of-sums (POS) form of
f (w, x, y, z)? (GATE-2017) (2 Marks)

G G
cd 00 01 11 10 a) f = (w' + z’) (x' + z) b) f = (w' + z) (x + z) c) f = (w + z) (x ' + z) d) f = (w + z’) (x' + z)

c’d’ 00
c’d 01
D 1
1 D
ge
1
yz
wx w’x’ w’x wx wx’
00 01 11 10 y+z

ge
w+x w+x w+x’ w’+x’ w’+x
0+0 0+1 1+1 1+0

ed ed
y’z’ 00 0 4 12 8
y+z 0+0
cd 11 1 D D y’z 01 y+z’ 0+1
0 4 12 8

l l
1 5 13 9 1 5 13 9

cd’ 10 1 D D yz 11 3 7 15 11 y’+z’ 1+1 3 7 15 11

w w
yz’ 10 2 6 14 10 y’+z 1+0 2 6 14 10

Kn o www.knowledgegate.in Kn o www.knowledgegate.in
F(P, Q, R, S) = Σ (0, 2, 5, 7, 8, 10, 13, 15)
The minterm 2, 7, 8, 13 are ‘do not care’ term.
te
Q Consider the following minterm expression for F: (GATE-2014) (2 Marks)

a pq p’q’ p’q pq pq’ (A) b’d’ (B) b’d’ + b’c’

te
Q What is the minimal form of the Karnaugh map shown below? Assume that X denotes a don’t
care term. (GATE-2012) (2 Marks)

a
(C) b’d’ + a’b’c’d’ (D) b’d’ + b’c’ + c’d’

G G
The minimum sum-of-products from for F is
a) QS’ + Q’S
rs 00 01 11 10

ge r’s’
r’s
00
01
0 4 12 8
ab a’b’ a’b ab ab’

ge
ed ed
b) Q’S’ + QS 1 5 13 9 cd 00 01 11 10
rs 11 c’d’ 00 1 D D 1

l l
3 7 15 11

c) Q’R’S’ + Q’RS’ + QR’S + QRS rs’ 10 c’d 01 D 1

w w
2 6 14 10

cd 11

Kn o
d) P’Q’S’ + P’QS + PQS + PQ’S’

www.knowledgegate.in Kn o cd’ 10 1 D

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A) b’d’ + a’d’ B) a’b’ + b’d’ + a’bd’

te
Q In the Karnaugh map shown below, X denotes a don’t care term. What is the minimal form of
the function represented by the Karnaugh map? (GATE-2008) (2 Marks)

a
C) b’d’ + a’bd’ D) a’b’ + b’d’ + a’d’
f (w, x, y, z) = ∑ (1,3,4,6,9,11,12,14)
The function is:

ate
Q Consider the following Boolean function of four variables: (GATE-2007) (2 Marks)

wx w’x’ w’x wx wx’

G G
(A) independent of one variable.
yz 00 01 11 10

cd
ab a’b’ a’b ab ab’

c’d’ 00 1
00 01 11 10
1 1
d ge (B) independent of two variables.

d ge y’z’
y’z
00
01
0

1
4

5
12

13
8

l
c’d 01

w
cd 11
D
D e wl
(C) independent of three variables.

e yz
yz’
11
10
3

2
7

6
15

14
11

10

o o
(D) dependent on all the variables.
cd’ 10 1 1 D

Kn www.knowledgegate.in Kn www.knowledgegate.in

(GATE-2005) (2 Marks)
(A) BC’D’ + A’C’D + AB’D
ate
Q The switching expression corresponding to f(A, B, C, D) = Σ (1, 4, 5, 9, 11, 12) is
ab a’b’ a’b ab ab’

ate
Q The literal count of a Boolean expression is the sum of the number of times each literal
appears in the expression. For example, the literal count of (xy + xz’) is 4. What are the minimum
possible literal counts of the product-of-sum and sum-of-product representations respectively of

G cd 00 01 11 10

G
the function given by the following Karnaugh map? Here, X denotes “don’t care” (GATE-2003) (2
Marks)

(B) ABC’ + ACD + B’C’D

ge c’d’ 00
c’d 01
0 4 12 8 (A) (11, 9) (B) (9, 13)

ge (C) (9, 10) (D) (11, 11)

ed ed
1 5 13 9 z+w z+w z+w’ z’+w’ z’+w
zw z’w’ z’w zw zw’
cd 11 3 7 15 11
x +y 0+0 0+1 1+1 1+0
xy 00 01 11 10

wl
(C) ACD’ + A’BC’ + AC’D’ cd’ 10
2 6 14 10
x’y’
x’y
wl00 X
01
1
1 X
1 x+y

x+y’
0+0

0+1
X
0
0
X 0

Kn o
(D) A’BD + ACD’ + BCD’

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xy

Kn
xy’ o 11 1
10 X
X X
X
x’+y’ 1+1

x’+y 1+0

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X
X
0
X
0
0
X

(A) xz + y’z (B) xz’ + zx’ (C) x’y + zx’

te
Q Minimum sum of product expression for f (w, x, y, z) shown in Karnaugh-map
below is (GATE-2002) (2 Marks)

a (D) None of these

te
Q Given the following Karnaugh map, which one of the following represents the

a
minimal Sum-Of-Products of the map? (GATE-2001) (2 Marks)
(A) xy + y’z (B) wx’y’ + xy + xz (C) w’x + y’z + xy (D) xz + y

yz
wx w’x’
00
w’x wx wx’
01 11 10 yz

geG
wx w’x’
00
w’x wx wx’
01 11 10 yz
wx w’x’ w’x wx wx’
00 01 11 10 yz

geGwx w’x’ w’x wx wx’

00 01 11 10

ed ed
y’z’ 00 D 1 0 1 y’z’ 00 D 1 1
y’z’ 00 0 D 0 D y’z’ 00 D D
y’z 01 0 1 D 0 y’z 01 1 D
yz
yz’

wl
11 1
10 D
D
0
D
0
0
D
yz
yz’
11 1
10 D
D D
D
y’z
yz
yz’

wl01
11
10
D
0
0
1
D
1
D
1
D
1
0
0
y’z
yz
yz’
01
11
10
D 1
D
1
D
1
D
1

Kn o www.knowledgegate.in Kn o www.knowledgegate.in

NOT equivalent to f? (GATE-2007) (2 Marks)

(A) x’y’z’ + w’xy’ + wy’z + xz
ate
Q Let f (w, x, y, z) = ∑ (0, 4, 5, 7, 8, 9, 13, 15). Which of the following expressions are
wx w’x’ w’x wx wx’ A) (W + X) Y

ate
Q Which function does NOT implement the Karnaugh map given below? (GATE - 2000) (2 Marks)

wz w’z’ w’z wz wz’

(B) w’y’z’ + wx’y’ + xz

geG yz
y’z’
y’z
00
01
00 01 11 10
0 4 12 8
B) XY + YW

geG xy
x’y’
00 01 11 10
00 0 X 0 0

ed ed
1 5 13 9 x’y 01 0 X 1 1
yz 11 xy 11 1 1 1 1

l l
3 7 15 11
(C) w’y’z’ + wx’y’ + xyz + xy’z xy’ 10 0 X 0 0
yz’ 10 2 6 14 10 C) (W + X) (W’ + Y) (X’ + Y)

ow
(D) x’y’z’ + wx’y’ + w’y

ow
Kn Kn
D) none of the above
i

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F(P, Q, R, S) = PQ + P’QR + P’QR’S pq
te
Q Consider the following Boolean expression for F: (GATE-2014)(2 Marks)

a
p’q’ p’q pq pq’
Q The simplified SOP (Sum of Product) form of the Boolean expression
(P + Q’ + R’). (P + Q’ + R). (P + Q + R’) is (GATE-2011)(1 Marks)

ate
the minimal sum-of-products from of F is
a) PQ + QR + QS
rs

eG
r’s’

g
00
00
0
01
4
11
12
10
8
(A) (P’.Q + R’)

(C) (P’.Q + R)

geG (B) (P + Q’.R’)

(D) (P.Q + R)

ed ed
r’s 01 1 5 13 9
pq p’q’ p’q pq pq’
rs 11

l l
3 7 15 11
rs 00 01 11 10
b) P + Q + R + S rs’ 10 r’s’ 00

w w
2 6 14 10 0 2 6 4
r’s 01

o o
1 3 7 5

c) P’ + Q’ + R’ + S’

Kn Kn
p+q p+q p+q’ p’+q’ p’+q

r 0+0 0+1 1+1 1+0

r 0
d) P’R + P’R’S + P 0 2 6 4
r’ 1 1 3 7 5
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(GATE-2008) (1 Marks)
(A) PQ’ (B) PR’
te
Q If P, Q, R are Boolean variables, then (P + Q’)(PQ’ + PR)(P’R’ + Q’) simplifies

a
(C) PQ’ + R (D) PR’ + Q (A) AC’+AB+A’C (B) AB’+AC’+A’C
te
Q The function AB’C + A’BC + ABC’ + A’B’C + AB’C’ is equivalent to (GATE-2004) (1 Marks)

a
(C) A’B+AC’+AB’ (D) A’B+AC+AB’

rs
pq p’q’ p’q
00 01 11 10
pq pq’

geG p+q p+q p+q’ p’+q’ p’+q

ab a’b’ a’b ab ab’
geG
d d
r 0+0 0+1 1+1 1+0

e e
r’s’ 00 r 0 c 00 01 11 10

l l
0 2 6 4 0 2 6 4

r’s 01 r’ 1 c’ 00

w w
1 3 7 5 1 3 7 5
0 2 6 4

Kn o www.knowledgegate.in
c 01

Kn o 1 3 7 5

www.knowledgegate.in

te
Q Which of the following expressions is equivalent to (A⊕B)⊕C (GATE-2004) (2 Marks)

a ab a’b’ a’b ab ab’

t
Q The Boolean function x’y’ + xy + x’y is equivalent to (GATE-2004) (1 Marks)

a e
G G
(A) x’ + y’ (B) x + y (C) x + y’ (D) x’ + y
c 00 01 11 10
(A) (A+B+C)(A’+B’+C’)

ge c’ 00 0 2 6 4

ge
ed ed
c 01 1 3 7 5

l l
(B) (A+B+C)(A’+B’+C)
x x’ X

w
(C) ABC+A’(B⊕C)+B’(A⊕C)

o
y
y’
ow 0 1

Kn Kn
0 0 2
(D) None y 1 1 3

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a) wx + w (x + y) + x (x + y) = x + wy
te
Q If w, x, y, z are Boolean variables, then which one of the following is INCORRECT? (GATE-2017)
(2 Marks)

a wx w’x’ w’x wx wx’ 2002) (2 Marks)

(A) x’ + z (B) xyz (C) xy’ + z
ate
Q Let f(A, B) = A’ + B. Simplified expression for function f(f(x + y, y), z) is : (GATE-

(D) None of these

G G
yz 00 01 11 10

e e
y’z’ 00 0 4 12 8

g g
b) (wx’ (y + z’))’ + w’x = w’ + x + y’z y’z 01 1 5 13 9

ed ed
yz 11 3 7 15 11

yz’ 10

l l
2 6 14 10

c) (wx’ (y + xz’) + w’x’) y = xy’

n ow
d) (w + y) (wxy + wyz) = wxy + wyz

n ow
K www.knowledgegate.in K www.knowledgegate.in

Q Consider two functions f1 and f2?

F1 = ∑m (1,2,5,6)
F2 = ∑m (2,3,4,5)
ate Q Consider two functions f1 and f2?
F1 = ∑m (1,2,5,6)
F2 = ∑m (2,3,4,5)
ate
G G
Find f1.f2 and f1 + f2 Find f1.f2 and f1 + f2
F1 F2 f1 + f2 f1 . f2

ge 0
1

ge0
1
0
0

ed ed
2 1 1

l l
3 0 1
4 0 1

ow ow 5
6
1
1
1
0

Kn Kn
7 0 0

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Q Consider f1 & f2 –
F1(a, b, c) = ∑m (0,2,4) + d (3,5,7)
F2(a, b, c) = ∑m (2,3) + d (1,6,7)
ate
0
F1
1
F2
0
f1 + f2 f1. f2
Q Consider f1 & f2 –
F1(a, b, c, d) = ∑m (1,3,4,5,9,10,11) + d (6, 8)
F2(a, b, c, d) = ∑m (0,2,4,7,8,15) + d (9, 12)

ate 1
0
F1
0
1
F2
1
0
f1 + f2 f1 . f2

G G
Find f1.f2 and f1 + f2 2 0 1
Find f1.f2 and f1 + f2

e e
3 1 0
1 0 D 4 1 1

ed g 2
3
1
D
1
1

ed g 5
6
7
1
D
0
0
0
1

wl 4
5
1
D
0
0

wl 8
9
10
D
1
1
1
D
0

o o
11 1 0
6 0 D 12 0 D

Kn Kn
7 d d 13 0 0
14 0 0
15 0 1
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don’t care conditions?

a) d(2,4) b) d(2,7)
te
Q Consider a function f (a, b, c) = ∑m (3, 5, 6) is being minimized to A + BC. Predict what are the

a c) d(4,7) d) d (2,4,7)
minterms as
f1 = (0, 2, 5, 8, 14)
ate
Q Consider three 4-variable functions f1, f2, and f3, which are expressed in sum-of-

ab a’b’ a’b ab ab’

geG f2 = (2, 3, 6, 8, 14, 15)
f3 = (2, 7, 11, 14)

geG
c

l
c’ 00
00 01 11 10
0 2 6 4
ed f can be

l
expressed as: (GATE-2019) (2 Marks)
ed
For the following circuit with one AND gate and one XOR gate, the output function

w w
a) Σ(7, 8, 11)
c 01 b) Σ(2, 7, 8, 11, 14)

o o
1 3 7 5
c) Σ(2, 14)

Kn www.knowledgegate.in Kn
d) Σ(0, 2, 3, 5, 6, 7, 8, 11, 14, 15)

www.knowledgegate.in

te
Q Given f1, f3 and f in canonical sum of products form (in decimal) for the circuit (GATE-2008) (1 Marks)

a te
Q Consider the following circuit. (GATE-2005) (1 Marks)
Which one of the following is TRUE?

a
geG geG
ed ed
A) Σm(4, 6)

wl
B)Σm(4, 8)

wl
(A) f is independent of X
(B) f is independent of Y

o
C)Σm(6, 8)

Kn
D)Σm(4, 6, 8)
www.knowledgegate.in Kn o
(C) f is independent of Z
(D) None of X, Y, Z is redundant

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F1(a, b, c, d) = ∑m (0,2,5,6,8,10,15)
F2(a, b, c, d) = ∑m (0,5,8,12,14)

ate ate
• Irredundant function: - A function f is said to be irredundant if no product term can be
removed from the function without changing the functional capability of the function.
• Minimal function: - A function is said to be minimal if it is representing the function

G G
F (a, b, c, d) = ∑m (0,5,6,7,8,12,13) expression, if it is using minimal no of literals to represent the function.

e e
f3(a, b, c, d) =?
• If a function is irredundant then, it may or may not be minimal, but if a function is minimal,

ed g then it is irredundant.

ed g
• F (x, y, z) = xz’ + y’z’ + yz + xz, this function is irredundant but not minimal
• F (x, y, z) = X + yz + y’z’

wl wl
• Minimal ⊆ irredundant

xy x’y’ x’y xy xy’

Kn o www.knowledgegate.in K
z

n o
z’ 00
z 01
00 01 11
0

1
2

3
6

7
10
4

5
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• Absorption law
• a + ab = a

ate _________. (GATE-2015) (1 Marks)

[Dʹ + ABʹ + AʹC + ACʹD + AʹCʹD]ʹ
ate
Q The number of min-terms after minimizing the following Boolean expression is

G G
• a.(a+b) =a
(A) 1 (B) 2 (C) 3 (D) 4
• Compensation theorem
• ab + a’c + bc = ab + a’c
ge ge cd
ab a’b’
00
a’b
01
ab
11
ab’
10

ed ed
c’d’ 00
0 4 12 8

• (a+b) (a’ + c) (b + c) = (a+b) (a’ + c) c’d 01 1 5 13 9

l l
cd 11 3 7 15 11
cd’ 10
2 6 14 10

w w
• a + a’b = a + b
• a.(a’+b) = a. b

Kn o www.knowledgegate.in Kn o www.knowledgegate.in
Q Consider the following Boolean expression:
F = (x+y+z) (x’+y) (y’+z)

ate
Which of the following Boolean expressions is/are equivalent to F’? (GATE-2021) (2 Marks)
f(w,0,0,z) =1
f(1,x,1,z) =x+z

ate
Q Consider a Boolean function f(w,x,y,z) such that (GATE-2021) (2 Marks)

G G
(A) xy’+yz’+x’y’z’ (B) (x’+y’+z’)(x+y’)(y+z’) f(w,1,y,z)=wz+y

e e
The number of literals in the minimal sum-of-products expression of f is _________

(C) (x+z’)(y’+z’)

ed g (D) xy’ + z’

ed g
wl cd
ab a’b’ a’b ab ab’
00 01 11 10

wl
Kn o c’d’
c’d
cd
cd’
00
01
11
10
0

3
4

6
12

13

15

14
8

11

2 www.knowledgegate.in
10
Kn o www.knowledgegate.in

0
1
w

0
0
x

0
0
y

0
0
z

0
1
F

ate ate
G G
2 0 0 1 0
3 0 0 1 1
4
5
6
7
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1

d ge d ge
8
9
10
1
1
1

wl
0
0
0
0
0
1
0
1
0
e wl e
o o
11 1 0 1 1
12 1 1 0 0
13
14
15

Kn
1
1
1
1
1
1
0
1
1
1
0
1

www.knowledgegate.in Kn www.knowledgegate.in

te
AND-OR(NAND-NAND) Implementation

a te
OR-AND(NOR-NOR) Implementation

a
geG geG
wl ed wl ed
Kn o www.knowledgegate.in Kn o www.knowledgegate.in

te
Q What is the Boolean expression for the output f of the combinational logic

a
circuit of NOR gates given below? (GATE-2010) (1 Marks)
te
Implementing Every Gate with NAND Gate

a
geG NOT
geG
wl ed wl ed
K o
(A) (Q+R)’

n
(C) (P+R)
(B) (P+Q)’

(D) (P+Q+R)’

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AND
Kn o www.knowledgegate.in

te
Implementing Every Gate with NAND Gate

a te
Implementing Every Gate with NAND Gate

a
OR
geG EX-OR
geG
wl ed wl ed
NOR

Kn o www.knowledgegate.in Kn o
EX-NOR
www.knowledgegate.in
 te
Implementing Every Gate with NOR Gate

a te
Implementing Every Gate with NOR Gate

a
NOT
geG OR
geG
wl ed wl ed
AND

Kn o www.knowledgegate.in
NAND

Kn o www.knowledgegate.in

te
Implementing Every Gate with NOR Gate

a te
Conclusion

a
G G
NOT AND OR NAND NOR EX-OR EX-NOR

EX-OR
d ge NOR
NAND

d ge
wl e wl e
n
EX-NOR
K o www.knowledgegate.in Kn o www.knowledgegate.in

te
Q What is the minimum number of NAND gates required to implement a 2-input

a
EXCLUSIVE-OR function without using any other logic gate? (GATE–2004) (1 Marks)
(A) 3 (B) 4 (C) 5 (D) 6
ate
Q Consider the Karnaugh map given below, where X represents “don’t care” and blank
represents 0. Assume for all inputs (a, c, d) the respective complements (a’, b’, c’, d’) are also
available. The above logic is implemented 2-input NOR gates only. The minimum number of gates

G G
required is _________. (GATE-2017) (1 Marks)

ge ge
wl ed wl ed
Kn o www.knowledgegate.in Kn o www.knowledgegate.in

te
Q what is the minimum number of gates required to implement the Boolean

a
function (AB+C) if we have to use only 2-input NOR gates? (GATE-2009) (1 Marks)
(A) 2 (B) 3 (C) 4 (D) 5
ate
Functionally Complete Function

• As we know there are only three fundamental Boolean operator NOT, AND and OR. All the

geG universal gates.

geG
other operators are derived from these operators

• We understand NOT along with OR(NOR) and NOT along with AND(NAND) are used as

ed ed
• Any Boolean operation or function can be implemented with NAND or NOR operation.

wl wl
• If any function can implement NOT along with it either AND or OR then, we indirectly prove
that the function can also implement any other function, so function can said to be

o o
functionally complete.

Kn www.knowledgegate.in Kn
• Support of 0, 1 or complemented form of variables are not allowed.

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Q Consider the operations (GATE-2015) (2 Marks)

f(X, Y, Z) = XʹYZ + XYʹ + Y'Z'

ate a) ⊕, not b) ⊕, 1, +
te
Q which of the following is functionally complete?
c) ⊕, 1, not

a d) ⊙, 1, not

g(X, Y, Z) = XʹYZ + XʹYZʹ + XY

geG geG
l
Which one of the following is correct?

w ed
(A) Both {f} and {g} are functionally complete

wl ed
o o
(B) Only {f} is functionally complete
(C) Only {g} is functionally complete

Kn Kn
(D) Neither {f} nor {g} is functionally complete

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Q f (a, b) = a’ + b is functionally complete ?

ate Q f (a, b, c) = a’ + bc’ is functionally complete

ate
geG geG
wl ed wl ed
Kn o www.knowledgegate.in Kn o www.knowledgegate.in

ate
Partially Functionally Complete: - A function is said to be partially functionally
complete, if it can be implement any digital circuit with support of logic 0 or 1 as a
input line (can’t use complemented form).
te
Q f (a, b) = ab’ + a’b not fully or partially complete

a
geG geG
l ed l ed
n ow n ow
K www.knowledgegate.in K www.knowledgegate.in

te
Q f (a, b, c) = ab + bc +ca is not fully or partially complete

a te
Combinational Circuits

a
geG geG O/p = f(i/p)

wl ed wl ed
Kn o www.knowledgegate.in Kn o www.knowledgegate.in

ate
Combinational Circuits
When logic gates are connected together to produce a specified out put on certain specified
combinations of input variables, with no memory involved, then the resulting circuit is called

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• Other circuits such as half adders, full adders, half subtractors, full subtractors, multiplexers,
demultiplexers, encoders and decoders are also made by using combinational logic.

•
a combinational circuit.

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Output depends only on present input. O/p = f(i/p), combinational circuit performs an

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operation that can be specified logically by a set of Boolean function. A combinational circuit
may have n-binary inputs and m-binary outputs.

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• Application, Practical computer circuits normally contain combinational and sequential logic.

l
For e.g. the part of ALU, that does mathematical calculations is constructed using
combinational logic.

w wl
Kn o www.knowledgegate.in Kn o www.knowledgegate.in

Design procedure: -

ate
1. Analyse the given problem and identify the number of i/p and o/p variables. •

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Adder
An adder is a digital combinational circuit that performs addition of numbers. Are used in
the arithmetic logic units or ALU.

G G
2. Write the truth table based on the specification of the problem.
• They are also utilized in other parts of the processor, where they are used to

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3. Convert the truth table in minimized Boolean expression using k-map.

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operations.

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calculate addresses, table indices, increment and decrement operators, and similar

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4. Draw the logic circuit for the above obtained output expression. • Although adders can be constructed for many number representations, such as binary-coded
decimal or excess-3, the most common adders operate on binary numbers.

wl •

l
In cases where two's complement or ones' complement is being used to represent negative

w
numbers, it is trivial to modify an adder into an adder–subtractor.

Kn o www.knowledgegate.in Kn o www.knowledgegate.in
• Basics of addition: - (A)x+ (B)x = ?

ate t
Half adder

e
• The simplest form of addition is addition of two binary digits, consists of four possible
elementary operations

a
geG 1
+1
geG
1
+0
0
+1
0
+0

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• The first three operations produce a sum of two digits, but when both augend and addend

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bits are equal to 1, the binary sum consists of two digits. The higher significant bit of this

o o
result is called a carry.

Kn www.knowledgegate.in Kn www.knowledgegate.in

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• It is a combinational circuit, which perform the arithmetic addition of two one-bit binary
numbers is referred to as an half-adder.

a ate
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• So, in half adder inputs are adds two single binary bits A and B, and two outputs, sum (S) and
carry (C).
INPUTS
A
0

d
B
0
ge OUTPUTS
Carry Sum

d ge
wl
0
1
1
e 1
0
1

wl e
1. Cost of implementation a half adder is one EX-OR gate and one AND gate.

2. A half adder has only two inputs and there is no provision to add a carry coming from the

o o
lower order bits when multi bit number addition is performed. For this reason, we have
designed a full adder.

Kn www.knowledgegate.in Kn www.knowledgegate.in

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Full adder

a
1. A full adder is a combinational logic circuit that performs the arithmetic sum of three input
bits.
•

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Two output bits are same as of half adder, which is Sum and Carryout.

When the augend and addend number contain more significant digits, the carry obtained

G G
from the addition of two bits is added to the next higher order pair of significant bits.

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2. Where An, Bn are the nth order bits of the number A and B respectively and Cn is the carry INPUTS OUTPUTS ab a’b’ a’b ab ab’
A B C in C out Sum

g g
generated from the addition of (n-1)th order bits. cin 00 01 11 10
0 0 0
cin’ 0

ed ed
0 2 6 4

3. It consists of three input bits, denoted by A (First operand), B (Second operand), Cin 0 0 1
cin 1 1 3 7 5
(Represents carry from the previous lower significant position). 0 1 0

wl wl 0
1
1
1
0
0
1
0
1 cin
ab a’b’ a’b
00 01
ab
11
ab’
10

o o
1 1 0 cin’ 0 0 2 6 4

1 1 1 cin 1

Kn Kn
1 3 7 5

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A
INPUTS
B C in
OUTPUTS
Sum C out

ate ate
G G
0 0 0 0 0

e e
0 0 1 1 0

g g
0 1 0 1 0
0 1 1 0 1

ed ed
1 0 0 1 0

l l
1 0 1 0 1
1 1 0 0 1

n ow 1 1 1 1 1

n ow
K www.knowledgegate.in K www.knowledgegate.in

ate te
Four-bit parallel binary adder / Ripple adder

a
• As we know that full adder is capable of adding two 1 bit number and 1 previous carry, but in
order to add binary numbers with more than one bits, additional full adders must be

geG geG
employed. For e.g. a four bit binary adder can be constructed using four full adders.

wl ed wl ed
Kn o www.knowledgegate.in Kn o www.knowledgegate.in
 the carry input of the next higher-order adder.

ate
• Theses four full adders are connected in cascade, carry output of each adder is connected to •

te
The longest propagation delay time in an adder is the time it takes the carry to propagate through the full
adders. For carry in a 4-bit adder we have 2 gate delays at each adder and for sum we have 1 gate delay.

a
• For an n -bit adder, there are 2n gate levels for the carry to propagate from input to output. And for Sum we

G G
• So a n-bit parallel adder is constructed using ‘n’ number of full adders.
have 2n-1 Gate delays.

ge ge
wl ed wl ed
Kn o www.knowledgegate.in Kn o www.knowledgegate.in

t
• There are some scope of improvement in adder like

a e • Can adder be modified to work as subtractor

• Adder/subtractor or ripple adder

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Carry propagation delay

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Look ahead Carry Generator

geG
l ed l ed
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Q A half adder is implemented with XOR and AND gates. A full adder is implemented with two half adders
and one OR gate. The propagation delay of an XOR gate is twice that of an AND/OR gate. The propagation

a
delay of an AND/OR gate is 1.2 microseconds. A 4-bit ripple-carry binary adder is implemented by using

ate
G G
full adders. The total propagation time of this 4-bit binary adder in microseconds is (GATE-2015) (2
Marks)

ge ge
wl ed wl ed
Kn o www.knowledgegate.in Kn o www.knowledgegate.in

te
Four-bit ripple adder/subtractor

a
• The subtraction A - B can be done by taking the 2’s complement of B and adding it to A. The 2’s
complement can be obtained by taking the 1’s complement and adding 1 to the least
•
1, the circuit becomes a subtractor.

ate
The mode input M controls the operation. When M = 0, the circuit is an adder, and when M =

When M = 0, we have B ⊕ 0 = B. The full adders receive the value of B, the input carry is 0,

G G
•
significant pair of bits.

e
and the circuit performs A plus B.
• The 1’s complement can be implemented with inverters, and a 1 can be added to the sum

g
through the input carry. The circuit for subtracting A - B consists of an adder with inverters •

ge
When M = 1, we have B ⊕ 1 = B’ and C0 = 1. The B inputs are all complemented and a 1 is

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placed between each data input B and the corresponding input of the full adder. added through the input carry. The circuit performs the operation A plus the 2’s complement
of B.

wl wl
Kn o www.knowledgegate.in Kn o www.knowledgegate.in

te
Q Consider an eight-bit ripple-carry adder for computing the sum of A and B, where A and B are
integers represented in 2’s complement form. If the decimal value of A is one, the decimal value of B

a
that leads to the longest latency for the sum to stabilize is _____________ (GATE-2016) (2 Marks)
Q Consider the ALU shown below.

ate
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If the operands are in 2’s complement representation, which of the following operations can be performed by

ed ed
suitably setting the control lines K and C0 only (+ and – denote addition and subtraction respectively)? (GATE-2007)
(2 Marks)

wl wl
(A) A + B, and A – B, but not A + 1

(B) A + B, and A + 1, but not A – B

Kn o www.knowledgegate.in Kn o
(C) A + B, but not A – B, or A + 1

(D) A + B, and A – B, and A + 1

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 ate
Look ahead carry adder
• In parallel adder all bits of augend and addend are available for computation initially, but sum and carry outputs
of any stage cannot be produced until the input carry occurs. This leads to delay in the addition process known as
te
• The carry propagation time is an important attribute of the adder because it limits the speed with which two
numbers are added. The solution to delay is to increase the complexity of the equipment in such a way that the
carry delay time is reduced.

a
carry propagation delay.

eG
• In any combinational circuit, the signal must propagate through the gates before the correct output sum is

g
available in the output terminals. The total propagation time is equal to the propagation delay of a typical gate

eG
• To solve this problem most widely used technique employs the principle of ‘look ahead carry’. This method
utilizes logic gates to look at the lower order bits of the augend and addend to see if a higher order carry is to be
generated. It uses two functions carry generate Gi and carry propagate Pi

g A(A3 A2 A1 A0)

ed ed
* times the number of gate levels in the circuit.
B(B3 B2 B1 B0)

wl wl
Kn o www.knowledgegate.in Kn o www.knowledgegate.in

ate Pi = A i ⊕ Bi
Gi= Ai . Bi
Si = Pi ⊕ Ci
te
• Gi is called a carry generate, and it produces a carry of 1 when both Ai and Bi are 1, regardless of the input carry Ci.

a
• Pi is called a carry propagate, because it determines whether a carry into stage i will propagate into stage i + 1.

G G
• We now write the Boolean functions for the carry outputs of each stage and substitute the value of each Ci from the previous
Ci+1 = Gi + Pi Ci equations:

d ge • Pi = Ai ⊕ Bi
Gi= Ai . Bi
Si = Pi ⊕ Ci
Ci+1 = Gi + Pi Ci

d ge
wl e • C0 =

• C1 =

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• C2 =

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• C3 =
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te
• Gi is called a carry generate, and it produces a carry of 1 when both Ai and Bi are 1, regardless of the input carry Ci.

a
• Pi is called a carry propagate, because it determines whether a carry into stage i will propagate into stage i + 1.

ate
• Since the Boolean function for each output carry is expressed in sum-of-products form. Each
function can be implemented with one level of AND gates followed by an OR gate (or by a two-
level NAND).

the previous equations:

• Pi = Ai ⊕ Bi
Gi= Ai . Bi

geG
• We now write the Boolean functions for the carry outputs of each stage and substitute the value of each Ci from
• C0 = 0
• C1 = G0 + P0 C0

geG
ed ed
Si = Pi ⊕ Ci
• C2 = G1 + P1G0 + P1P0 C0
Ci+1 = Gi + Pi Ci
• C3 = G2 + P2G1 + P2P1G0 + P2P1 P0 C0
•
•
•

wl
C0 = 0
C1 = G0 + P0 C0
C2 = G1 + P1G0 + P1P0 C0

wl
• C4 = G3 + G2.P3 + G1.P2.P3 + G0.P1.P2.P3 + C0.P0.P1.P2.P3

•
•

o
C3 = G2 + P2G1 + P2P1G0 + P2P1 P0 C0

Kn
C4 = G3 + G2.P3 + G1.P2.P3 + G0.P1.P2.P3 + C0.P0.P1.P2.P3

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through S3 have equal propagation delay times.

ate
• All output carries are generated after a delay through two levels of gates. Thus, outputs S1

te
• All output carries are generated after a delay through two levels of gates. Thus, outputs S1
through S3 have equal propagation delay times.

a
geG geG
wl ed wl ed
Kn o www.knowledgegate.in Kn o www.knowledgegate.in

(A) Θ(1) (B) Θ(Log (n))

ate
Q Consider a carry lookahead adder for adding two n-bit integers, built using gates of fan-in at
most two. The time to perform addition using this adder is (GATE–2016) (2 Marks)
(C) Θ(√ n) (D) Θ(n)
Pi = Ai ⨁ Bi and Gi = AiBi

ate
Q In a look-ahead carry generator, the carry generates function Gi and the carry propagate function Pi for inputs Ai
and Bi are given by (GATE-2007) (2 Marks)

The expressions for the sum bit Si and the carry bit Ci+1 of the look-ahead carry adder are given by:

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Si = Pi ⨁ Ci and Ci+1 = Gi + PiCi , where C0 is the input carry.

e
Consider a two-level logic implementation of the look-ahead carry generator. Assume that all Pi and Gi are available
for the carry generator circuit and that the AND and OR gates can have any number of inputs. The number of AND

g
gates and OR gates needed to implement the look-ahead carry generator for a 4-bit adder with S3, S2, S1, S0 and C4 as
its outputs are respectively:

ed ed
(A) 6, 3 (B) 10, 4 (C) 6, 4 (D) 10, 5

wl wl
Kn o www.knowledgegate.in Kn o www.knowledgegate.in
 te
Q Given two three-bit numbers a2a1a0 and b2b1b0 and c, the carry in, the function that represents
the carry generate function when these two numbers are added is (GATE-2006) (2 Marks)

a te
Q A 4-bit carry lookahead adder, which adds two 4-bit numbers, is designed using AND, OR, NOT,

a
NAND, NOR gates only. Assuming that all the inputs are available in both complemented and
uncomplemented forms and the delay of each gate is one-time unit, what is the overall

G G
propagation delay of the adder? Assume that the carry network has been implemented using
two-level AND-OR logic. (GATE-2004) (2 Marks)

ge (A) 4 time units (B) 6 time units

e
(C) 10 time units

g
(D) 12 time units

wl ed wl ed
Kn o www.knowledgegate.in Kn o www.knowledgegate.in

ate ate
geG geG
d d
---

wl e wl e
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ate
Multiplexer (Selector)
• Multiplexer are special and one of the most widely used combinational circuits.
•

•
a set of selection lines.

There are 2n input lines and n selection lines whose

ate
The selection of a particular input line is controlled by

eG
• Main requirement is out of many inputs we have to select one for e.g. telephone or train
leaving the station. So multiplexer do not perform any logical operation or comparison, it just
acts as a switch or relay.

g
• A multiplexer is a combinational circuit that selects binary information from one of many input
bit combinations determine which input is to be
selected.

• No of Input line =< 2n

• Note:

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lines and directs it to a single output line. A multiplexer is also called a data selector, since it • Can never have two i/p connected to out at any time
selects one of many inputs and steers the binary information to the output line.

wl wl
Application
• Parallel data to serial data conversion
• Used as data selector, as the output of a multiplexer

Kn o www.knowledgegate.in Kn o
is directed from one of various inputs
• Used in implementation of Boolean functions
• Used in communication systems, Computer Memory,
Telephone Network, Transmission from the
Computer System of a Satellite

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te
A two-to-one-line multiplexer

a
• This multiplexer acts like an electronic switch that selects one of two sources.

ate
A two-to-one-line multiplexer

• When S = 0, the upper AND gate is enabled and I0 has a path to the output.

G G
• When S = 1, the lower AND gate is enabled and I1 has a path to the output.

e e
• The circuit has two data input lines, one output line, and one selection line S.
Input Output

ed g S
0

ed
Y
g
I0

wl wl 1 I1

Kn o www.knowledgegate.in
n o
Characteristic equation: Y = S0’ I0 + S0 I1

K www.knowledgegate.in

te
Case study of 4 to 1

a
• The circuit has four data input lines I0, I1, I2, I3 one output line Y, and two
t
Case study of 4 to 1

e
• Each of the four inputs, I0 through I3, is applied to one input of an AND gate.

a
• Selection lines S1 and S0 are decoded to select a particular AND gate.

G G
• The outputs of the AND gates are applied to a single OR gate that provides the one-line
selection line S0 and S1.

e
output.

g S1
Input
S0
Output
Y

ge
ed ed
0 0 I0
0 1 I1

wl wl 1
1
0
1
I2
I3

Kn o www.knowledgegate.in Kn o
Characteristic equation
Y = E [(S’1 S’0 I0) + (S’1 S0 I1) + (S1 S’0 I2) + (S1 S0 I3)]

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 ate
Q Which one of the following circuits implements the Boolean function given
below? f(x,y,z) = m0 + m1 + m3 + m4 + m5 + m6. where mi is the ith
minterm.(GATE 2021) (1 MARKS) is (Gate-CS-2014-Set-1) (2 Marks)

ate
Q Consider a 4-to-1 multiplexer with two select lines S1 and S0, given below
The minimal sum-of-products form of the Boolean expression for the output F of the multiplexer

G G
(A) P’Q + QR’ + PQ’R (B) P’Q + P’QR’ + PQR’ + PQ’R
(C) P’QR + P’QR’ + QR’ + PQ’R (D) PQR’

ge ge
Y = [(S’1 S’0 I0) + (S’1 S0 I1) + (S1 S’0 I2) + (S1 S0 I3)]

wl ed wl ed
Kn o www.knowledgegate.in Kn o www.knowledgegate.in

(B) P ⊕ Q ⊕ R

ate
Q The Boolean expression for the output ‘f’ of the multiplexer shown below is (GATE-2010) (2 Marks)
(A) (P ⊕ Q ⊕ R)’ (C) (P + Q + R)’ (D) P + Q + R

ate
Q Consider the following multiplexor where I0, I1, I2, I3 are four data input lines selected by two
address line combinations A1A0 = 00, 01, 10, 11 respectively and f is “the output of the
multiplexor. EN is the enable input. (Gate-CS-2002) (2 Marks)

G G
The function f(x, y, z) implemented by the above circuit is :
(A) xyz’ (B) xy + z (C) x + z (D) None of these

e e
Y = [(S’1 S’0 I0) + (S’1 S0 I1) + (S1 S’0 I2) + (S1 S0 I3)]

ed g ed g
Y = E [(S’1 S’0 I0) + (S’1 S0 I1) + (S1 S’0 I2) + (S1 S0 I3)]

wl wl
Kn o www.knowledgegate.in Kn o www.knowledgegate.in

te
Q Consider the circuit in below figure. f implements (GATE-1996) (2 Marks)

a te
Q Consider the two cascaded 2-to-1 multiplexers as shown in the figure. (GATE-2016) (2 Marks)

a Y = S 0 ’ I0 + S0 I1

(A) (ABC)’ + A’BC’ + ABC

geG geG
The minimal sum of products form of the output X is Y = S 0 ’ I0 + S0 I1

ed ed
Y = [(S’1 S’0 I0) + (S’1 S0 I1) + (S1 S’0 I2) + (S1 S0 I3)]

l l
(B) A + B + C

w
(C) A ⊕ B ⊕ C

o ow
Kn Kn
(D) AB + BC + CA

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2007) (1 Marks)
What are the values of X1, X2, X3?

ate
Q The following circuit implements a two-input AND gate using two 2-1 multiplexers. (GATE-
represents f (x, y, z)? (Gate-CS-2006) (2 Marks)
(A) xz’ + xy + y’z (B) xz’ + xy + (yz)’
ate
Q Consider the circuit above. Which one of the following options correctly

(C) xz + xy + (yz)’ (D) xz + xy’ + y’z

G G
(A) X1=b, X2=0, X3=a (B) X1=b, X2=1, X3=b
(C) X1=a, X2=b, X3=1 (D) X1=a, X2=0, X3=b Y = S 0 ’ I0 + S0 I1

ge
Y = S 0 ’ I0 + S0 I1 Y = S 0 ’ I0 + S0 I1

ge
wl ed wl ed
Y = S 0 ’ I0 + S0 I1

Kn o www.knowledgegate.in Kn o www.knowledgegate.in

(A) 1, 0, B (B) 1, 0, A

te
Q The circuit shown below implements a 2-input NOR gate using two 2-4 MUX (control signal 1 selects the upper
input). What are the values of signals x, y and z? (GATE-2005) (2 Marks)

a (C) 0, 1, B (D) 0, 1, A
(A) f = x1’+ x2 (B) f = x1’x2 + x1x2ʹ

ate
Q Consider the circuit shown below. The output of a 2:1 Mux is given by the function (ac’ + bc),
Which of the following is true? (GATE-2001) (2 Marks)
(C) f = x1x2 + x1’x2ʹ (D) f = x1 + x2ʹ

geG Y = S 0 ’ I0 + S0 I1

geG
Y = S 0 ’ I0 + S0 I1

wl ed Y = S 0 ’ I0 + S0 I1

wl ed Y = S 0 ’ I0 + S0 I1

Kn o www.knowledgegate.in Kn o www.knowledgegate.in
 (B) f = x1’x2 + x1x2ʹ

te
Q Consider the circuit shown below. Which of the following is true?
(A) f = x1’+ x2 (C) f = x1x2 + x1’x2ʹ

a
(D) none

te
Q Suppose only one multiplexer and one inverter are allowed to be used to implement any
Boolean function of n variables. What is the minimum size of the multiplexer needed? (Gate-CS-
2007) (2 Marks)

a
G G
(A) 2n line to 1-line (B) 2n+1 line to 1 line
(C) 2n-1 line to 1-line (D) 2n-2 line to 1 line

ge ge
wlY = S 0 ’ I0 + S0 I1
ed
Y = S 0 ’ I0 + S0 I1 Y = S 0 ’ I0 + S0 I1

wl ed
Kn o www.knowledgegate.in Kn o www.knowledgegate.in

ate
Q The majority function is a Boolean function f (x, y, z) that takes the value 1 whenever a
majority of the variables x, y, z is 1. In the circuit diagram for the majority function shown below,
the logic gates for the boxes labelled P and Q are, respectively? (GATE-2006) (2 Marks)

ate
Q The majority function is a Boolean function f (x, y, z) that takes the value 1 whenever a
majority of the variables x, y, z is 1. In the circuit diagram for the majority function shown below,
the logic gates for the boxes labelled P and Q are, respectively? (GATE-2006) (2 Marks)

(A) XOR, AND

(B) XOR, XOR

geG (A) XOR, AND

(B) XOR, XOR

geG x
0

0
y
0

0
z
0

1
f

(C) OR, OR

l
(D) OR, AND
ed (C) OR, OR

l
(D) OR, AND
ed 0

1
1

0
0

n ow n ow 1

1
0

1
1

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te
Multiplexer Expansion
(Implementation of Higher order MUX using lower order MUX)

a Input Output
Q How many 4 : 1 MUX using 16 : 1 MUX ?

ate
G G
Q How many 2:1 MUX are required to Implement
4:1 MUX ? S1 S0 Y

e e
Q How many 4X1 Mux are required in order to construct 128X1?
0 0 I0

ed g 0
1
1
0
I1
I2

ed g
l l
1 1 I3
Q How many 8X1 Mux are required in order to construct 4096X1?

ow ow
Kn www.knowledgegate.in Kn www.knowledgegate.in

Given:

Target:
mX1

nX1

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Demultiplexer

a
1. A demultiplexer (or DeMux) is a device that takes a single input line and routes it to one of

No of levels(K) logmn

geG several digital output lines.

geG
2. A demultiplexer is also called a data distributor.

ed ed
No of Mux at ith level (xi) (n/mi)
3. It is conceptually same as Mux just with reverse logic.

wl
Total Mux required
$
!"$

!"#
𝑥𝑖

wl
Kn o
Maximum capacity mk X 1

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output line to send the input.

ate
• A demultiplexer of 2n outputs has n select lines, which are used to select which

• A DeMux is a combinational circuit, which is used in data communication

te
1 to 2 Demultiplexer

a
• Serial to parallel conversation.

eG
• Different input/output configuration demultiplexers are available in the form of
single integrated circuits (ICs).

g
S0
0

geGO1
0
O0
I

ed ed
• Demultiplexers are mainly used in Boolean function generators and decoder 1 I 0
circuits.

wl wl
Kn o www.knowledgegate.in Kn o www.knowledgegate.in
 S1
te
1 to 4 Demultiplexer

a
S0 O3 O2 O1 O0
ate
Demultiplexer Expansion
(Implementation of Higher order DeMux using lower order DeMux)

0
0
1
0 0 0 0 I

e
1 0 0 I 0

g
0 0 I 0 0
G geG
Q 1 : 2 DeMux are required to implement 1 : 4 DeMux ?

ed ed
1 1 I 0 0 0

wl l
Q 1 : 2 DeMux are required to implement 1 : 8 DeMux ?

w
Kn o www.knowledgegate.in Kn o www.knowledgegate.in

ate t
Decoder

a e
• A decoder is a combinational circuit that decodes binary information from n input lines to a
maximum of 2n unique output lines.

geG G
• The decoders are called n -to- m -line decoders, where m ≤ 2n.

e
• Their purpose is to generate the 2n (or fewer) minterms of n input variables. Each combination
of inputs will assert a unique output.

g
• If the n -bit coded information has unused combinations, the decoder may have fewer than 2n

l ed l ed
outputs. Decoders are also combinational circuits logically we can say a DeMux can be
converted into a decoder by setting input line as enable line and selection line as input lines.

n ow n ow
K www.knowledgegate.in K www.knowledgegate.in

ate te
1-to-2 Decoder

I
a
O1 O0

geG 0
1
geG0
I 0
I

wl ed wl ed
Kn o www.knowledgegate.in Kn o www.knowledgegate.in

ate Input
te
2-to-4 Decoder

a Output

geG I1
0
0
I0 O3
0 0
1 0
geG O2
0
0
O1
0
1
O0
1
0

ed ed
1 0 0 1 0 0

wl wl 1 1 1 0 0 0

Kn o www.knowledgegate.in
E

Kn o www.knowledgegate.in

Q Implementation of a full adder with a decoder

ate
From the truth table of the full adder, we obtain the functions for the combinational circuit in
sum-of-minterms form:

ate
G G
S(x, y, z) = ∑ (1, 2, 4, 7)
C(x, y, z) = ∑ (3, 5, 6, 7)

ge ge
wl ed wl ed
Kn o www.knowledgegate.in Kn o www.knowledgegate.in
 te
Combinational Logic Implementation

a
• Any combinational circuit with n inputs and m outputs can be implemented with an n -to-2n -
line decoder and OR gates.
te
• Active High Decoder:- When output is directly from AND gate, we get exact minterms then, it
is called active high decoder. In the 2nd level here, we use OR-gate to find the function.

a
G G
• Active Low Decoder:- In active low decoders, output will be from NAND gates, on the 2nd level
• The procedure for implementing a combinational circuit by means of a decoder and OR gates

e
we again use NAND gate, as we know NAND-NAND implementation is SAME as AND-OR.
requires that the Boolean function for the circuit be expressed as a sum of minterms.

g
• A decoder is then chosen that generates all the minterms of the input variables. The inputs to

ge
ed ed
each OR gate are selected from the decoder outputs according to the list of minterms of each
function.

wl wl
Kn o www.knowledgegate.in Kn o www.knowledgegate.in

te
Q What Boolean function does the circuit below realize? (GATE-2006) (2 Marks)

(A) xz + x’z’
a te
Decoder Expansion

a
(B) xz’ + x’z

geG geG
l
(C) x’y’ + yz
ed l ed
ow
(D) xy + y’z’

n n ow
K www.knowledgegate.in K www.knowledgegate.in

Q 6-to-64 from 2-to-4 ?

ate Target:

Given:
ate
mXn

pXq

geG No of levels(K)

geG
floor(m/p)

ed ed
No of Mux at ith level (xi) (n/q k-i+1)

l
Q 7-to-128 from 3-to-8 ?

w wl
Total Mux required
#
𝑖=𝑘
𝑥𝑖

Kn o www.knowledgegate.in Kn o
Maximum capacity
𝑖=1
(p X k) X qk

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te
Q How many 3-to-8-line decoders with an enable input are needed to construct a

a
6-to-64-line decoder without using any other logic gates? (GATE-2007) (2 Marks)
(A) 7 (B) 8 (C) 9 (D) 10
16-line decoder.

ate
Q Two 3-to-8-line decoders with enable inputs connected to form a 4-to-

geG geG
wl ed wl ed
Kn o www.knowledgegate.in Kn o www.knowledgegate.in

Encoder
• An encoder is a combinational circuit that

ate te
2-to-1 Encoder

a
G G
encode binary information form one of a
2N input lines and encode it into N output

e
lines, which represent N bit code for the input.

g I1
ge
I0 O0

ed ed
• For simple encoders, it is assumed that only
one input line is active at a time. 0 1 0

l
• Encoder performs the inverse operation of a

w
decoder.

wl 1 0 1

Kn o www.knowledgegate.in Kn o www.knowledgegate.in
 t
4-to-2 Encoder

a e •

ate
Priority Encoder
In some practical cases more than one input can be high at a time, there we can not use
simple encoder. In a priority encoder more than one input can be high at a time. A priority

I3
0
I2
0
I1
0

geGI0 O1 O0
1 0 0
• O0 =
•

eG
encoder is an encoder circuit that includes the priority function.
The operation of the priority encoder is such that if two or more inputs are equal to 1 at the

g
same time, the input having the highest priority will take precedence.

ed ed
0 0 1 0 0 1 • They are often used to control interrupt requests by acting on the highest priority interrupt
0 1 0 0 1 0 • O1 = input. The priority encoders output corresponds to the currently active input which has the

wl 1 0 0 0 1 1
l
highest priority. So when an input with a higher priority is present, all other inputs with a
lower priority will be ignored.

w
Kn o www.knowledgegate.in Kn o www.knowledgegate.in

I3 > I2 > I1 > I0

I3 I2 I1
ate
I0 O1 O0
(A) Priority encoder (B) Decoder
te
Q In the following truth table, V = 1 if and only if the input is valid. (GATE-2013) (2 Marks)
What function does the truth table represent?

a (C) Multiplexer (D) Demultiplexer

0
0
0
0
0
1
0
1
d

geG 1
d
d

geG
l
1 d

ed
d d

l ed
n
O0 =
ow n ow
K
O1 =

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ate
SEQUENTIAL CIRCUITS
• Sequential Circuits consists of a combinational circuit to which memory elements are
connected to form a feedback path. The memory elements are devices capable of storing
te
Latches

a
• Latch means to hold something or something which do not change.
binary information.

eG
• The binary information stored in these elements at any given time defines the state of the
sequential circuit at that time.

g
• The sequential circuit receives binary information from external inputs (xn) that, together with
holding 1 bit until necessary.

geG
• latches are the basic building blocks of any flip flop and they are capable of

• Storage elements that operate with signal levels are referred to as latches.

ed ed
the present state (yn-1) of the memory elements, determine the binary value of the
outputs(yn). • Latches are level sensitive devices.

wl
• A sequential circuit is specified by a time sequence of inputs, outputs, and internal states.
f(xn, yn-1) = yn

wl
Kn o www.knowledgegate.in Kn o www.knowledgegate.in

and two inputs labeled S for set and R for reset.

ate
NOR Latch
• The SR latch is a circuit with two cross-coupled NOR gates or two cross-coupled NAND gates,

ate
NAND Latch S
0
R
0
Qn Qn+1
0

geG
• Outputs Qn and Qn’ are the complement of each other, in valid scenario.

geG 0
0
0
0
1
1
1
0
1

ed ed
S R Qn Qn+1 1 0 0

l l
0 0 0 1 0 1
0 0 1 1 1 0

n ow 0
0
1
1
1
0
0
1
0

n ow 1 1 1

K K
1 0 1
1 1 0
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(A) Q = 0, Q’ = 1
a
set to 0, then it will result in (GATE-2004) (2 Marks)
te
Q In an SR latch made by cross-coupling two NAND gates, if both S and R inputs are SR flip flop

ate
1. The operation of the basic SR latch can be modified by
providing an additional input signal that determines

(B) Q = 1, Q’ = 0

geG G
(controls), when the state of the latch can be changed by

e
determining whether S and R (or S and R) can affect the
circuit.

g
ed ed
2. It consists of the basic SR latch and two additional AND
gates. The control input CP / En acts as an enable signal

wl
(C) Q = 1, Q’ = 1

l
for the other two inputs.

w
3. The outputs of the AND gates stay at the 0 as long as the

o
(D) Indeterminate states

Kn www.knowledgegate.in Kn o
enable signal remains at 0 as one input of AND gate gets
0 resulting in 0 as output. When the enable input goes to
1, information from the S or R input is allowed to affect
the latch.

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 Implementation

ate S
Truth Table
R Qn Qn+1
Block Diagram Implementation

ate S
Truth Table
R Qn Qn+1
K-Map

G G
0 0 0 0
0 0 0 0 0 1 1

e e
0 1 0 0

0 0 1 0
1
1
0
1
0
0
1

g g
1 0 1 1
0 1 0 1 1 0 X

ed ed
1 1 1 X

0 1 1

l l
1 0 0 Characteristics Equation Function Table Excitation Table State Diagram

1 0 1

w w
S R Qn+1 Qn Qn+1 S R
Qn+1 = 0 0 0 0
1 1 0

o o
0 1 0 1
1 0 1 0
1 1 1

Kn Kn
1 1 1 1

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Block Diagram Implementation

ate S
Truth Table
R Qn Qn+1
K-Map

ate
G G
0 0 0 0
0 0 1 1

e e
0 1 0 0
0 1 1 0
1 0 0 1

g g
1 0 1 1
1 1 0 X

d d
1 1 1 X

wl
Characteristics Equation

Qn+1 = S + R’ Qn
S
0
R
0 e
Function Table

Qn+1
Qn
Excitation Table

Qn
0
Qn+1
0
S
0
R
d
State Diagram

wl e
o o
0 1 0 0 1 1 0
1 0 1 1 0 0 1

n n
1 1 X 1 1 d 0

K www.knowledgegate.in K www.knowledgegate.in

• Edge triggering is always preferred over

level triggering because in edge
triggering system is in transparent mode
ate te
Notes

a
• The key to the proper operation of a flip-flop is to trigger it only during a signal transition(edge).

for very less amount of time, so system

will be stable.
• Order of Priority

geG sequential circuit using latches.

edge).

geG
• This can be accomplished by eliminating the feedback path that is inherent in the operation of the

• A clock pulse goes through two transitions: from 0 to 1(+ve edge) and the return from 1 to 0 (-ve

ed ed
• -ve edge
• +ve edge • The way that a latch can be modified to form a flip-flop. To produce a flip-flop that triggers only during

l l
a signal transition(edge) (from 0 to 1 or from 1 to 0) of the synchronizing signal (clock) and is disabled
• -ve level during the rest of the clock pulse.

w w
• +ve level • Latches are the basic circuits from which all flip-flops are constructed.

o o
• The storage elements (memory) used in clocked sequential circuits are called flipflops.

Kn Kn
• A flip-flop is a binary storage device capable of storing one bit of information. In a stable state, the
output of a flip-flop is either 0 or 1 (it is called bi-stable multi-vibrator).

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ate
Notes
A flip-flop is said to be stable if it has complementary behavior.

ate
JK flip flop
• SR flip flop when both S and R = 1, results in invalid output. To resolve the problem we use JK
Flip Flop. We take a feedback from the outputs.

G G
• Latches are level sensitive devices; flip-flops are edge-sensitive devices.

e e
• Storage elements that operate with signal levels are referred to as latches; those controlled

g g
by a clock transition are flip-flops.
• Flip-flops can be either level-triggered (asynchronous, transparent or opaque) or edge-

ed ed
triggered (synchronous, or clocked).

l l
• The term flip-flop has historically referred generically to both level-triggered and edge-
triggered circuits that store a single bit of data using gates.

w
• Recently, some authors reserve the term flip-flop exclusively for discussing clocked circuits;

o
• the simple ones are commonly called transparent latches. Using this terminology, a level-
sensitive flip-flop is called a transparent latch

n
• Whereas an edge-triggered flip-flop is simply called a flip-flop.

n ow
K
• Using either terminology, the term "flip-flop" refers to a device that stores a single bit of data.
The terms "edge-triggered", and "level-triggered" may be used to avoid ambiguity.
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te
JK flip flop

a
• SR flip flop when both S and R = 1, results in invalid output. To resolve the problem we use JK
Flip Flop. We take a feedback from the outputs.

ate J
Truth Table
K Qn Qn+1

Block Diagram

geG Implementation

geG 0
0
0
0
0
1
0
1
0

ed ed
0 1 1

wl wl 1
1
0
0
0
1

o o
1 1 0

Kn Kn
1 1 1

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 J
Truth Table
K Qn Qn+1

ate JK J’K’ J’K JK

K-Map
JK’
Block Diagram Implementation

ate J
Truth Table
K Qn Qn+1
K-Map

G G
0 0 0 0

0 0 0 0 q 00 01 11 10 0 0 1 1

e e
0 1 0 0

0 0 1 1 0 1 1 0

q’ 00

g g
1 0 0 1
1 0 1 1
0 1 0 0

ed ed
1 1 0 1

0 1 1 0 q 01 1 1 1 0

l l
1 Characteristics Equation Function Table Excitation Table State Diagram
1 0 0
1 0 1 1
1
1
ow 1
1
0
1
1
0
ow
Qn+1 =
J
0
0
K
0
1
Qn+1 Qn
0
0
Qn+1
0
1
J K

Kn Kn
1 0 1 0
1 1 1 1

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Block Diagram Implementation

ate J
Truth Table
K Qn Qn+1
K-Map

when inputs J and K are tied together.

ate
T(Toggle) flip flop
• The T (toggle) flip-flop is a complementing flip-flop and can be obtained from a JK flip-flop

G G
0 0 0 0
0 0 1 1

e e
0 1 0 0
0 1 1 0

g g
1 0 0 1
1 0 1 1

d d
1 1 0 1
1 1 1 0

wl
Characteristics Equation

J K e
Function Table

Qn+1 Qn
Excitation Table

Qn+1 J K
State Diagram J
0
0

wl
K
0
0
Qn
0
1
Qn+1
0
1 e T
0
Truth Table
Qn
0
Qn+1

o o
Qn+1 = J Q’n + K’Qn 0 0 Qn 0 0 0 d 0 1 0 0
0 1 0 0 1 1 d 0

n n
0 1 1 0 1
1 0 1 1 0 d 1 1
1 0 0

K K
1 1 Q’n 1 1 d 0
1 0 1 1 1 0
1 1 0 1
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1 1
1 1 1

Block Diagram

ate
Truth Table

Qn Qn+1
K-Map
T T’ T
Block Diagram

T
te
Truth Table

a Qn Qn+1
K-Map
T T’ T

0
0
1
1

geG 0
1
0
1
0
1
1
0
q

q’

q
0
1
0 1 0
0
1
1

geG 0
1
0
1
0
1
1
0
q

q’

q
0
1
0

1
1
1

wl
Characteristics Equation

T ed
Function Table

Qn+1 Qn
Excitation Table

Qn+1 T
State Diagram

wl
Characteristics Equation

T ed
Function Table

Qn+1 Qn
Excitation Table

Qn+1 T
State Diagram

o o
Qn+1 = T ⊕ Qn
0 0 0 0 0
Qn+1 = 0 0 1 0 Qn 0 1 1

Kn Kn
1 1 0 1 Qn’ 1 0 1
1 1 1 1 0

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D flip flop

ate
• The D (Data/Delay) flip-flop, tracks the input at D and produces the same value
as output.
Block Diagram

ate
Truth Table

Qn Qn+1
K-Map
D D’ D

geG 0
0
1
1

geG 0
1
0
1
0
0
1
1
q
q’
q
0
1
0 1

ed ed
J K Qn Qn+1

l l
0 0 0 0
Truth Table Characteristics Equation Function Table Excitation Table State Diagram

D Qn Qn+1

w w
0 0 1 1
D Qn+1 Qn Qn+1 D
0 1 0 0 0 0 Qn+1 =

o o
0 0 0
0 1 1 0 1
0

n n
1 0 1
1 0 0 1 0 1 0

K K
1 0 1 1
1
1 1 1 1 1
1 1 0
1 1 1 0
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Block Diagram

ate
Truth Table

Qn Qn+1
K-Map
D D’ D

ate
Flip Flops Conversion

1. We will require the Characteristics Table of target flip flop.

0
0
1
1

geG 0
1
0
1
0
0
1
1
q
q’
q
0
1
0 1
1
1

geG
2. We will require the Excitation Table of given flip flop.

ed ed
3. Determine the excitation values for characteristics table.

l l
Characteristics Equation Function Table Excitation Table State Diagram
4. Obtain the expressions for input of given flip flop in terms of target.

owQn+1 = D D
0
Qn+1
0
Qn
0
Qn+1
0
D
0

ow
Kn Kn
0 1 1
1 0 0
1 1 1 1 1

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 ate
Convert D Flip Flop to T Flip Flop

te
Convert D Flip Flop to T Flip Flop

Excitation values for characteristics table

a
Obtaining simplified expression Using K-Map to Simplify

G G
Characteristics table of T- Flip Flop Excitation Table of D flip flop
T Qn Qn+1 D T Qn D T T’ T
T Qn Qn+1
0 0
ge Qn Qn+1 D
0 0
0 0 0 0 0

ge 0 q 0 1

ed ed
0 1 1 1 0 1 q’
0 1 0
0 1 1 0 1 1 1 0

wl 1 0
1 1
T Qn Qn+1 D
0 0 0
1
1
0
1
1

wl 1 0 0 1 1 q 1

Kn o 0 1 1
1 0 1
1 1 0
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te
Convert D Flip Flop to T Flip Flop

a te
Convert D Flip Flop to T Flip Flop

a
G G
Using K-Map to Simplify Block Diagram
Using K-Map to Simplify Block Diagram

d ge d ge
wl e wl e
Kn o D = Qn ⊕ T

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(A) (x ⊕ y)’and x’ ⊕ y’

ate
Q Consider the following state diagram and its realization by a JK flip flop, the combinational circuit
generates J and K in terms of x, y and Q. The Boolean expressions for J and K are : (GATE-2008) (2 Marks)
(B) (x ⊕ y)’and x ⊕ y •

ate
Basics of counters
A counter is a sequential circuit that goes through a predetermined sequence of binary states
upon the application of input pulses.

G G
(C) x ⊕ y and (x ⊕ y)’ (D) x ⊕ y and x ⊕ y
Qn Qn+1 J K

e e
X Y Qn Qn+1 X Y Qn Qn+1 J K

0 0 0 0 0 0 • The gates in the counter are connected in such a way as to produce the prescribed sequence
0 0

g g
0
0
0
1
1
0
0
0
0
1
1
0 0 1 of states.
0 1 1 0 1 1

ed ed
1 0
1 0 0 1 0 0
1 1
• A counter that follows the binary number sequence is called a binary counter.
1 0 1 1 0 1
1 1 0 1 1 0

l l
1 1 1 1 1 1 • An n - bit binary counter consists of n flip-flops and can count in binary from 0 through 2n - 1.

w w
X Y Qn J K XY X’Y’ X’Y XY XY’ • Counters are available in two categories: synchronous counters and Ripple counters
0 0 0 q 00 01 11 10 (asynchronous).

o o
0 0 1 q’ 00
0 1 0
q 01

Kn Kn
0 1 1
1 0 0
XY X’Y’ X’Y XY XY’
1 0 1
1 1 0 q 00 01 11 10
1 1 1 q’ 00
q 01

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ate ate
geG geG
wl ed wl ed
Kn o www.knowledgegate.in Kn o www.knowledgegate.in

Q Find out the counting sequence for the counter below?

The characteristics equation for JK Flip Flop is Qn+1 =
Q0N =

ate ate
Q Consider a 3-bit counter, designed using T flip-flops, as shown below: Assuming
the initial state of the counter given by PQR as 000, what are the next three states?
(GATE 2021) (2 MARKS)
The characteristics equation for T Flip Flop is Qn+1 =
Q1N =

geG (A) 011, 101, 000

(B) 001, 010, 111
(C) 011, 101, 111

geG
ed ed
(D) 001, 010, 000

l l
Present State Next State
Present State Next State Q2p Q1p Q0p Q2N Q1N Q0N

w w
Q1p Q0p Q1N Q0N 0 0 0
0 0 0 0 1

Kn
0
1
1o 1
0
1

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0

Kn
0
1
1
1
1
o 1
1
0
0
1
1
0
1
0
1
0
1
www.knowledgegate.in
 te
Q Consider a combination of T and D flip-flops connected as shown below. The output of the D flip-flop is connected to
the input of the T flip-flop and the output of the T flip-flop is connected to the input of the D flip-flop. Initially, both Q0

a
and Q1 are set to 1 (before the 1st clock cycle). The outputs (GATE-2017) (2 Marks) (A) 001, 010, 011 (B) 111, 110, 101

ate
Q The above sequential circuit is built using JK flip-flops is initialized with Q2Q1Q0 = 000. The state sequence for this
circuit for the next 3 clock cycle is (GATE-2014) (2 Marks)
(C) 100, 110, 111 (D) 100, 011, 001

geG geG
ed ed
Present State Next State

l l
Q2p Q1p Q0p Q2N Q1N Q0N
0 0 0
Present State Next State

w w
0 0 1
Q1p Q0p Q1N Q0N 0 1 0
0

Kn
0
1
1
o 0
1
0
1

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0
1
1
1
1

Kn o
1
0
0
1
1
1
0
1
0
1

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the value of PQR after the clock edge? (GATE-2011) (2 Marks)

(A) 000 (B) 001
te
Q Consider the following circuit involving three D-type flip-flops used in a certain type of counter configuration. If at
some instance prior to the occurrence of the clock edge, P, Q and R have a value 0, 1 and 0 respectively, what shall be

a (C) 010 (D) 011

(A) 3 (B) 4

ate
Q Consider the data given in previous question. If all the flip-flops were reset to 0 at power on, what is the total number
of distinct outputs (states) represented by PQR generated by the counter? (GATE-2011) (2 Marks)
(C) 5 (D) 6

geG geG
l e
Q2p Q1p
0 0 d
Present State
Q0p
0
Q2N
Next State
Q1N Q0N

l ed
w w
0 0 1
0 1 0

o o
0 1 1

n n
1 0 0
1 0 1

K K
1 1 0
1 1 1

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counter is (GATE-2011) (1 Marks)

ate
Q The minimum number of D flip-flops needed to design a mod-258

te
Q Consider the following circuit, The flip-flops are positive edge triggered D FFs. Each state is designated as a two-bit
string Q0Q1. Let the initial state be 00. The state transition sequence is: (GATE - 2005) (2 Marks)
a) 00, 11, 01
b) 00, 11

a
geG c) 00, 10, 01, 11
d) 00, 11, 01,10

geG
wl ed Q0p

wl
Present State

Q1p
Next State

Q0N Q1N ed
Kn o www.knowledgegate.in
0

Kn
0
1
1 o 0
1
0
1

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(A) 1,3,4,6,7,5,2 (B) 1,2,5,3,7,6,4

ate
Q Consider the circuit given below with initial state Q0 =1, Q1 = Q2 = 0. The state of the circuit is given by the value
4Q2 + 2Q1 + Q0 , Which one of the following is the correct state sequence of the circuit? (GATE-2001) (2 Marks)
(C) 1,2,7,3,5,6,4 (D) 1,6,5,7,2,3,4
Marks)

ate
Q The following arrangement of master-slave flip flops has the initial state of P, Q as 0, 1
(respectively). After three clock cycles the output state P, Q is (respectively), (GATE-2000) (2

G G
Present State Next State

e e
Q1p Q0p Q1N Q0N
0 0

Present State Next State

ed g ed g 0
1
1
1
0
1

l l
Q2p Q1p Q0p Q2N Q1N Q0N
0 0 0
0 0 1 (A) 1, 0
0
0
1
1

n
1
1
0
0
ow 0
1
0
1
ow
(B) 1, 1

n
K K
1 1 0 (C) 0, 0
1 1 1

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(A) 0 (B) 1

ate
Q The minimum number of JK flip-flops required to construct a synchronous counter with the
count sequence (0, 0, 1, 1, 2, 2, 3, 3, 0, 0,…) is ________ (GATE-2015) (2 Marks)
(C) 2 (D) 3
this counter is (GATE - 2016)
ate
Q We want to design a synchronous counter that counts the sequence 0-1-0-2-0-3
and then repeats. The minimum number of J-K flip-flops required to implement

geG geG
wl ed wl ed
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 te
Q A positive edge-triggered D flip-flop is connected to a positive edge-triggered JK flipflop as follows. The Q output of the D flip-
flop is connected to both the J and K inputs of the JK flip-flop, while the Q output of the JK flip-flop is connected to the input of

a
the D flip-flop. Initially, the output of the D flip-flop is set to logic one and the output of the JK flip-flop is cleared. Which one of
the following is the bit sequence (including the initial state) generated at the Q output of the JK flip-flop when the flip-flops are
(A) 134 (B) 133 (C) 124
ate
Q How many pulses are needed to change the contents of an 8-bit up counter from
10101100 to 00100111 (rightmost bit is the LSB)? (GATE-2005) (2 Marks)
(D) 123

G G
connected to a free-running common clock? Assume that J = K = 1 is the toggle mode and J = K = 0 is the state-holding mode of
the JK flip-flop. Both the flip-flops have non-zero propagation delays. (GATE-2015) (2 Marks)
(A) 0110110… (B) 0100100…

e
(C) 011101110…

g
(D) 011001100…

ge
w
Q0p
l
Present State

Q1p
Next State

Q0N Q1N ed wl ed
Kn o
0
0
1
1
0
1
0
1

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te
Q Consider the sequential circuit shown in the figure, where both flip-flops used are positive

a
edge-triggered D flip-flops. The number of states in the state transition diagram of this circuit
that have a transition back to the same state on some value of “in” is _____.(GATE-2018) (2

ate
Q Consider the following circuit involving a positive edge triggered D FF. (GATE-2005) (2 Marks)

Marks)

Present State Next State

geG geG
d d
Q2p Q1p Q0p Q2N Q1N Q0N
Consider the following timing diagram. Let Ai represent the logic level on the line A in the i-th clock period.
0 0 0

e e
0 0 1 Let A’ represent the complement of A. The correct output sequence on Y over the clock periods 1 through 5 is
0
0
1

wl
1
1
0
0
1
0

wl
(A) A0 Al A1ʹ A3 A4
(B) A0 Al A2ʹ A3 A4
(C) Al A2 A2ʹ A3 A4

o o
1 0 1
1 1 0 (D) Al A2ʹ A3 A4 A5ʹ

Kn
1 1 1

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te
Q Design a synchronous counter for sequence: 0 → 1 → 2 → 3 → 0, using T flip flop.

a Present State Next State

ate
Q Example: Design a synchronous counter for sequence: 0 → 1 → 2 → 3 → 0, using D flip flop.

G G
Present State Next State
Q1p Q0p Q1N Q0N Q1p Q0p Q1N Q0N
0
0
0
1

ge 0
0
0
1

ge
ed ed
1 0 1 0
1 1 1 1

wl wl
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flip-flop.

ate
Q Design synchronous counter for sequence: 0 → 1 → 3 → 4 → 5 → 7 → 0, using T
sequence 0-2-3-1-0, as shown below (GATE-2004) (2 Marks)
To complete the circuit, the input X should be

ate
Q Consider the partial implementation of a 2-bit counter using T flip-flops following the

(C) (Q1 ⊕ Q2)’ (D) Q1 ⊕ Q2

G G
(A) Q2ʹ (B) Q2 + Q1
Present State
Q2p Q1p Q0p Q2N
Next State
Q1N Q0N

ge Present State Next State

ge
ed ed
0 0 0
Q1p Q0p Q1N Q0N
0 0 1
0 0

l l
0 1 0
0 1 1 0 1

w w
1 0 0 1 0
1 0 1 1 1

Kn
1
1

o 1
1
0
1

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te
Q The next state table of a 2-bit saturating up-counter is given below. (GATE-2017) (2 Marks)
The counter is built as synchronous sequential circuit using T flip-flops. The value for T1 and T0 are
(A) T1 = Q0Q1 T0 = Q’0Q’1

a (B) T1 = Q’1Q0 T0 = Q’1 + Q’0

RIPPLE COUNTERS

ate
1. A binary ripple counter consists of a series connection of
complementing flip-flops, with the output of each flip-flop

G G
(C) T1 = Q1 + Q0 T0 = Q’1 + Q’0 (D) T1 = Q’1Q0 T0 = Q1 + Q0 connected to the input of the next higher order flip-flop.

Present State
Q1p Q0p
Next State
Q1N Q0N

ge incoming count pulses.

ge
2. The flip-flop holding the least significant bit receives the

ed ed
0 0
0 1
1 0
1

wl 1

wl
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(A) 11, 10, 01, 00 (B) 10, 11, 01, 00

ate
Q In the sequential circuit shown below, if the initial value of the output Q1Q0 is 00, what are the
next four values of Q1Q0? (GATE-2010) (2 Marks)
(C) 10, 00, 01, 11 (D) 11, 10, 00, 01

ate
geG Present State
Q1p
0
0
Q0p
0
1
Next State
Q1N Q0N

geG
ed ed
1 0
1 1

wl wl
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Nature of Clock

ate
Nature of Feedback Nature of counting SYNCHRONOUS COUNTER
In synchronous counter, all flip flops are triggered with same

ate
Asynchronous counters
ASYNCHRONOUS COUNTER
In asynchronous counter, different flip flops are triggered with

G G
+ve Qn’ UP Counting clock simultaneously. different clock, not simultaneously.

e e
Synchronous Counter is faster than asynchronous counter in Asynchronous Counter is slower than synchronous counter in
+ve Qn Down Counting operation. Tdelay = TFF + T CC operation. Tdelay = n x TFF + T CC

-ve

ed g Qn UP Counting
Synchronous Counter is also called Parallel Counter.
Synchronous Counter designing as well implementation are
complex due to increasing the number of states.

ed g Asynchronous Counter is also called Serial Counter.

Asynchronous Counter designing as well as implementation is
very easy.

wl -ve Qn’ Down Counting

l
Synchronous Counter will operate in any desired count
sequence.

w
Synchronous Counter examples are: Ring counter, Johnson
Asynchronous Counter will operate only in fixed count
sequence (UP/DOWN).
Asynchronous Counter examples are: Ripple UP counter, Ripple

o o
counter. DOWN counter.
A synchronous sequential circuit is a system whose behavior The behavior of an asynchronous sequential circuit depends

Kn www.knowledgegate.in Kn
can be defined from the knowledge of its signals at discrete
instants of time.

www.knowledgegate.in
upon the input signals at any instant of time and the order in
which the inputs change.

sequence irrespective of initial state.

ate
• Self-Starting Counter: - A counter is said to be self-starting if it provides the counting Restricted mod counter

ate
Q Consider a restricted mod counter and find what sequence it is counting?

G G
• Free running counter: - a counter is said to be free running If it maintains all possible states in Q2 Q1 Q0
the counting sequence. 0 0 0

• 0à3à2à1à0

ge 0
0
0
1
1
0

ge
ed ed
• 0à1à3à2à1
0 1 1
• 0 à 3 à 0, 1 à 2 à 3
1 0 0

l l
• 0 à 1 à 2 à 0, 3 à 3
1 0 1
• 0 à 1 à 2 à 3 à 4 à 5 à 6 à 2, 7 à 6
1 1 0

w w
• 1 à 3 à 4 à 5 à 6 à 2 à 1, 7 à 6
1 1 1

Kn o
• Conclusion: - if a counter is free running, it is also self-starting, but vice-versa not required to be true.

www.knowledgegate.in Kn o www.knowledgegate.in

Q3 Q2 Q1 Q0
Restricted mod counter

ate
Q Consider a restricted mod counter and find what sequence it is counting? The counter is connected as follows: (GATE-2007) (2 Marks)
Assume that the counter and gate delays are

ate
Q The control signal functions of a 4-bit binary counter are given below (where X is “don’t care”)

0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0

geG negligible. If the counter starts at 0, then it cycles

through the following sequence:
(A) 0, 3, 4

geG
ed ed
0 1 0 1
0 1 1 0 (B) 0, 3, 4, 5
0 1 1 1

l l
1 0 0 0
1 0 0 1 (C) 0, 1, 2, 3, 4

w w
1 0 1 0
1 0 1 1 (D) 0, 1, 2, 3, 4, 5

o o
1 1 0 0
1 1 0 1

n n
1 1 1 0
1 1 1 1

K www.knowledgegate.in K www.knowledgegate.in

ate
Registers
• Registers are basically storing devices which are also designed using basic element called flip-
flop.
ate
Serial In-Serial Out (SISO)
• The shift register, which allows serial input (one bit after the other through a single data line) and produces a
serial output is known as Serial-In Serial-Out shift register.

geG
• D-flip-flop are most popular choice for register because they don’t perform any functionality
and output is simply based on current input so, they act as a buffer.
• Apart from storing registers sometimes also be used in performing basic mathematical
name Serial-In Serial-Out Shift Register.

Sequence Input Q2 Q1 Q0

geG
• Since there is only one output, the data leaves the shift register one bit at a time in a serial pattern, thus the

Output

ed ed
operation like multiply by 2 by left shit and divide by 2 by right shift.

l l
• There are four different modes in which registers operate.
• Serial In-Serial Out (SISO)

ow
• Serial In-Parallel Out (SIPO)
• Parallel In-Serial Out (PISO)
• Parallel In- Parallel Out (PIPO)

ow
Kn www.knowledgegate.in Kn www.knowledgegate.in
• The main use of a SISO is to act as a delay element.

ate
• In SISO registers to provide n bit data serially in it requires n clock pulse and to provide serial
output it requires n - 1 clock pulses.
•

ate
Serial-In Parallel-Out shift Register (SIPO)
The shift register, which allows serial input (one bit after the other through a single data line)
and produces a parallel output is known as Serial-In Parallel-Out shift register.

SISO
No of clock (write)

geG No of clock (Read) total

•

into parallel data.

g G
They are used in communication lines where demultiplexing of a data line into several

e
parallel lines is required because the main use of the SIPO register is to convert serial data

ed ed
SIPO
PISO

wl PIPO

wl
o o
No of clock (write) No of clock (Read) total
SISO n n-1 2n-1

Kn Kn
SIPO
PISO
PIPO
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ate
Parallel-In Serial-Out Shift Register (PISO)
• The shift register, which allows parallel input (data is given separately to each flip flop and in a simultaneous manner) and
produces a serial output is known as Parallel-In Serial-Out shift register.
No of clock
(write)
ate No of clock
(Read)
total

G G
• The circuit consists of four D flip-flops which are connected.
• The clock input is directly connected to all the flip flops but the input data is connected individually to each flip flop through a

e SISO n

e n-1 2n-1
multiplexer at the input of every flip flop.
• The output of the previous flip flop and parallel data input are connected to the input of the MUX and the output of MUX is
connected to the next flip flop.

d g
• A Parallel in Serial out (PISO) shift register us used to convert parallel data to serial data.

e
SIPO
PISO
n

ed g 0 n

wl l
PIPO

w
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ate
Parallel-In Parallel-Out Shift Register (PIPO)
The shift register, which allows parallel input (data is given separately to each flip flop and in a simultaneous manner) and
also produces a parallel output is known as Parallel-In parallel-Out shift register.
No of clock
(write)
ate No of clock
(Read)
total

G G
• The circuit consists of four D flip-flops which are connected.
• In this type of register, there are no interconnections between the individual flip-flops since no serial shifting of the data is

•
•
required.

ge
Data is given as input separately for each flip flop and in the same way, output also collected individually from each flip flop.
A Parallel in Parallel out (PIPO) shift register is used as a temporary storage device and like SISO Shift register it acts as a delay
SISO
SIPO
n
n
ge n-1
0
2n-1
n

ed ed
element.
• For parallel input it requires 1 clock pulse and for parallel output it requires 0 clock.
PISO 1 n-1 n

wl l
PIPO

w
Kn o www.knowledgegate.in Kn o www.knowledgegate.in

a) 1 ns b) 31 ns c) 32 ns
ate
Q Consider a 32- bit shift register which uses a clock of 1 GHz. If register is
operated in SISO mode, find total time required to perform loading and reading?
d) 63 ns
ate
Q Consider the circuit in the diagram. The ⊕ operator represents Ex-OR. The D flipflops are
initialized to zeroes (cleared). (GATE-2006) (2 Marks)

geG geG
wl ed l ed
The following data: 100110000 is supplied to
the “data” terminal in nine clock cycles. After

w
that the values of q2q1q0 are:

o o
(A) 000
(B) 001

Kn www.knowledgegate.in Kn
(C) 010
(D) 101

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4-Bit Ring Counter

at
Ring Counter/ Straight Ring Counter

e
• A ring counter is a circular shift register with only one flip-flop being set at any particular time;
• Number of unused states in Ring Counter is 2n-n

ate
G G
all others are cleared.
• The single bit is shifted from one flip-flop to the next to produce the sequence of timing
signals.

ge
• Output of the last flip-flop is connected to the input of the first flip-flop in case of ring counter.

ge
ed ed
• No. of states in Ring counter = No. of flip-flop used

wl wl
CLK
0
1
Q3 Q2 Q1 Q0

Kn o www.knowledgegate.in Kn o 2
3
0

www.knowledgegate.in
 te
Johnson Counter/ Twisted ring counter/ Switch-tail ring counter/ Walking ring counter

a
• A k -bit ring counter circulates a single bit among the flip-flops to provide k distinguishable

ate
G G
states.
• The number of states can be doubled if the shift register is connected as a switch-tail ring

e
counter. A switch-tail ring counter is a circular shift register with the complemented output of

g
the last flip-flop connected to the input of the first flip-flop.
CLK Q3 Q2

g
Q1
e Q0

ed ed
0

l l
1
2

w w
3
4

Kn o www.knowledgegate.in Kn o 5
6
7
0

www.knowledgegate.in

(A) 0, 1, 3, 7, 15, 14, 12, 8, 0

ate
Q Consider a 4-bit Johnson counter with an initial value of 0000. The counting sequence of this
counter is (GATE-2015) (2 Marks)
(B) 0, 1, 3, 5, 7, 9, 11, 13, 15, 0
(A) k-bit binary up counter.
ate
Q Let k = 2n. A circuit is built by giving the output of an n-bit binary counter as
input to an n-to-2n bit decoder. This circuit is equivalent to a (CS-2014) (2 Marks)
(B) k-bit binary down counter.

G G
(C) 0, 2, 4, 6, 8, 10, 12, 14, 0 (D) 0, 8, 12, 14, 15, 7, 3, 1, 0
(C) k-bit ring counter. (D) k-bit Johnson counter.

d ge d ge
wl e wl e
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te
Basics

a
• Main idea in number system is counting and representation of quantity.

ate
• So next popular system we use in real life is decimal system, may be because we have 10
fingers on over hands, in history different cultures have been using base 10 for general
purpose counting, Indian, British, roman, Arabic etc.

G G
• In stone age or even today the basic idea of counting in Unary counting
• Remember how we started counting on fingers and using abacus • Thought Aryabhata (3500 years back) was the first one known to extensively worked on the

ge
• How can we use it for counting sheep or anything?
• But when we want to count larger quantity in anything, day to day life, business, maths or

ge
idea of zero, pie, number system, trigonometry, quadratic equations, astronomy etc.
• In Indian culture we were working on very complex math from much early time, Aryabhata

ed ed
research, we cannot work with unary system. was may be first one, who have properly written and published his understanding, and some
of his work even reached today.

wl wl
Kn o www.knowledgegate.in
Samsung pays Apple $1 Billion sending 30 trucks full of 5 cent coins
Kn o www.knowledgegate.in

ate
Number
System

ate
• Formally speaking number system is an ordered set of symbols called digits, from (o to r-1) if r
is this base or radix of the system with rules defined for performing arithmetic operations.
• So, point to be noted is we cannot use a digit higher than r-1 in base r

Real life

geG Computer
Science Number System Base or Radix

geG
• Very digit should be of single number, otherwise we may get confuse.
Digits or symbols

ed ed
Binary 2 0,1
Octal 8 0,1,2,3,4,5,6,7

l l
Unary Decimal Binary Octal Hexadecimal
(Base 1) (Base 10) (Base 2) (Base 8) (Base 16) Hexadecimal 16 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F

n ow n ow
Number System
Unary
Base or Radix
1
Digits or symbols
0/1

K www.knowledgegate.in K Decimal 10 0,1,2,3,4,5,6,7,8,9

www.knowledgegate.in

te
• Collection of digits makes a number which has two parts integer and fractional,
separated by a Radix point (decimal point)

a •(an-1 an-2 an-3 ……..a1 a0 . a-1 a-2…….. a-m)

ate
Value of any base in decimal(any base to decimal conversion)

G G
• The number system we use for counting are weighted number and the idea is

e
(an-1 an-2 an-3 ……..a1 a0 . a-1 a-2…….. a-m)
g ge
ed
• Nr = an-1rn-1 + an-2rn-2+ an-3rn-3+…….+ a1r1+ a0r0+ a-1r-1……….+ a-mr-m

wl wl
• 𝑉𝑎𝑙𝑢𝑒 = ∑)'*
%&'( aI . r
i
ed
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 te
Decimal Number System

a
• Decimal Number System is a base-10 system that has ten digits: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9.

te
a5 a4 a3 a2 a1 a0 . a-1 a-2 a-3

a
G G
• The decimal number system is said to be of base, or radix, 10 because it uses 10 digits and the
coefficients are multiplied by powers of 10.

ge
• This is the base that we often use in our day to day life.

ge
a5 105 + a4 104 + a3 103 + a2 102 + a1 101 + a0 100 + a-1 10-1 + a-2 10-2 + a-3 10-3

ed ed
• Example: (7,392)10 , where 7,392 is a shorthand notation for what should be written as

wl 7 * 103 + 3 * 102 + 9 * 101 + 2 * 100

wl
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te
Binary Number System

a
• The coefficients of the binary number system have only two possible values: 0 and 1.

• Each coefficient aj is multiplied by a power of the radix, e.g., 2j, and the results are added to obtain the decimal
system.

ate
• Similarly, there can be many bases and they can be easily converted to decimal number

G G
• An example of a base-5 number is
equivalent of the number.
(4021.2)5

• 𝑉𝑎𝑙𝑢𝑒 = ∑'%(
#$%& aI . 2
i

d e
• Nr = an-12n-1 + an-22n-2+ an-32n-3+…….+ a121+ a020+ a-12-1……….+ a-m2-m

g d ge
wl e
Example: (11010.11)2 value in Decimal?
l
4 * 53 + 0 * 52 + 2 * 51 + 1 * 50 + 2 * 5-1 = (511.4)10

w e
Kn o
1 * 24 + 1 * 23 + 0 * 22 www.knowledgegate.in
+ 1 * 21 + 0 * 20 + 1 * 2-1 + 1 * 2-2 = 26.75
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(4213.21)5 (

ate )10 ( )7

ate
Octal Number System
• The octal number system is a base-8 system that has eight digits: 0, 1, 2, 3, 4, 5, 6, 7.

geG Nr = an-1 8n-1 + an-2 8n-2+ an-3

geG
8n-3+…….+ a1 81 + a0 80 + a-1 8-1……….+ a-m8-m

ed ed
𝑉𝑎𝑙𝑢𝑒 = ∑%#&
!"#$ aI . 8
i

wl wl (127.4)8

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1 * 82 + 2 * 81 + 7 * 80 + 4 * 8-1 = (87.5)10
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than 10.

ate
Hexadecimal Number System
• The letters of the alphabet are used to supplement the 10 decimal digits when the base of the number is greater

ate
Conversion
• Basic idea is we want to convert from any base to any base. To do that first we convert from any base to decimal
and then from decimal to any base. But if the base is in the power to 2, then we can use base to two convert

G
• For example, in the hexadecimal (base-16) number system, the first 10 digits are borrowed from the decimal

e
system. The letters A, B, C, D, E, and F are used for the digits 10, 11, 12, 13, 14, and 15, respectively.

g
• Nr = an-1(16)n-1 + an-2(16)n-2+ an-3(16)n-3+…….+ a1(16)1+ a0(16)0+ a-1(16)-1……….+ a-m(16)-m
which is relatively easy.

leading to octal, hexadecimal.

Hexadecimal System / Base 16 System

geG
• In case a binary number usually becomes so large so better idea is to club digits in a group of three or four,

Octal System / Base 8 System base 4 System

ed ed
0000 0

• 𝑉𝑎𝑙𝑢𝑒 = ∑'%#
!"%& aI . (16)
i 0001 1 000 0 00 0
0010 2
001 1 01 1

l (B65F)16
l
0011 3
0100 4 010 2 10 2
0101 5

w w
011 3 11 3
0110 6
0111 7 100 4

o o
1000 8
101 5
1001 9

n n
1010 10-A 110 6
1011 11-B
111 7

K K
1100 12-C
1101 13-D
1110 14-E

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+ 5 * 161 + 15 * 160 = (46,687)10 1111 15-F

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representation of the number? (GATE 2021)

(a) 15
ate
Q Let the representation of a number in base 3 be 210. What is the hexadecimal Q If x and y are two decimal digits and (0.1101)2 = (0.8xy5)10, the
decimal value of x+y is _____ . (GATE 2021) (1 MARKS)

ate
(b) 21

geG geG
ed ed
(c) D2

(d) 528

wl wl
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 te
Q Consider the unsigned 8-bit fixed point binary number representation below,
b7 b6 b5 b4 b3.b2 b1 b0

a ate
Q Consider a quadratic equation x2 - 13x + 36 = 0 with coefficients in a
base b. The solutions of this equation in the same base b are x = 5 and

G G
where the position of the binary point is between b3 and b2. Assume b7 is the most significant bit. x = 6. Then b=________. (GATE-2017) (2 Marks)

e e
Some of the decimal numbers listed below cannot be represented exactly in the above

g g
representation (GATE-2017) (2 Marks)

ed ed
(i) 31.500 (ii) 0.875 (iii) 12.100 (iv) 3.001
Which one of the following statements is true?

wl
(A) None of (i), (ii), (iii), (iv) can be exactly represented
(B) Only (ii) cannot be exactly represented

wl
o
(C) Only (iii) and (iv) cannot be exactly represented

Kn
(D) Only (i) and (ii) cannot be exactly represented

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te
Q The representation of the value of a 16-bit unsigned integer X in a hexadecimal number system
is BCA9. The representation of the value of X in octal number system is: (GATE-2017) (SET-2)

a te
Q The n-bit fixed-point representation of an unsigned real number X

a
uses f bits for the fraction part. Let i = n-f. The range of decimal values
(A) 571244

(B) 736251

geG (A) 2-f to 2i

geG
for X in this representation is (GATE-2017) (2 Marks)

l
(C) 571247
ed (B) 2-f to (2i - 2-f)

l ed
n ow
(D) 136251

n ow
(C) 0 to 2i

K www.knowledgegate.in K
(D) 0 to (2i - 2-f )
www.knowledgegate.in

te
Q Consider the equation (123)5 = (x8)y with x and y as unknown. The

a
number of possible solutions is _____. (GATE-2014) (1 Marks)

ate (GATE-2014) (2 Marks)

G G
(A) 1
(123)5 = (x8)y

ge ge
ed ed
(B) 2

(C) 3

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Q (1217)8 is equivalent to (GATE-2009) (2 Marks)

A.(1217)16
ate te
Q Let r denote number system radix. The only value(s) of r that satisfy the equation

a
B.(028F)16
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(A) decimal 10

geG
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C.(2297)10 ed l
(B) decimal 11

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(C) decimal 10 and 11

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D.(0B17)16
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(D) any value > 2

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(657) at
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Q The hexadecimal representation of (657)8 is (CS-2005) (1 Marks)
(A) 1AF (A) (A72E)16 and (22130232)4

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Q The number (123456)8 is equivalent to (GATE-2004) (1 Marks)

(123456)8
(B) D78

g eG 8 (B) (A72E)16 and (22131122)4

geG
(C) D71

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(C) (A73E)16 and (22130232)4
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(D) (A62E)16 and (22120232)4

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(D) 32F

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Q What will be no of digits required to represent 123-bit binary
no into a decimal no?
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Representation of a number

a
geG geG Number

wl ed wl Unsigned
number ed Signed
number

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• Until now, we have considered only unsigned numbers.

ate
Unsigned number

• Unsigned numbers without any positive or negative sign, these numbers represent only
ate
Signed number
• To perform now a day’s mathematical work for e.g. profit and loss statement, temperature scale,
subtraction, representation of negative numbers is needed.

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• So, we use + and – symbols to represent the positive and negative sign respectively, along with
magnitude.

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magnitude or absolute value. Number without a sign is considered as positive.
• In real life, we have only unsigned numbers (considered as positive) (natural numbers) for e.g. • Suppose that an n-bit word is to contain a signed binary number. One bit is reserved to represent the
number of stars, number of trees etc.

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• If n bits are used to store the number, then all the n bits are used to store number /

e
minus respectively.

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sign of the number, while the remaining n-1 bits indicate its magnitude. To permit uniform processing
of all n-bits, the sign is placed to the leftmost magnitude (MSB), 0 and 1 are used to denote plus and

l l
magnitude / absolute value.
• If we have a n bit Unsigned number than range is from 0 to 2n-1

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• A signed number has to components of information

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Signed binary number
Signed number
representation

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• The sign of a number, i.e. positive(+ve) or negative(-ve)
• The magnitude and or absolute value

ge
• In real life when we write a signed number then we represent both information, sign and
magnitude or absolute value separately for e.g. +9, -543 etc.

ge Signed complement system

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Signed magnitude convention(here the (here the negative number is represented by
• Because of the limitation of the computer hardware as circuit only understand 0 and 1, every negative number is represented by it's sign) it's complement)

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piece of information in computer must be represented in terms of numbers i.e. 0 and 1,
weather it is sign or magnitude.

w
• So, a general convention in first bit (left most) of the number is reserved to represent the sign

o
of the number where 0 means +Ve number and 1 means -Ve number. And the rest of the bit

ow Signed magnitude
1's complement
representation
2's complement
representation

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represent the magnitude or absolute value representation

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Decimal
+7
+6
Signed Magnitude 1’s Complement

ate 2’s Complement Decimal

+7
+6
+5
Signed Magnitude
0111
0110
0101
1’s Complement
0111
0110
0101

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2’s Complement
0111
0110
0101
• All Positive number have 0 in the leftmost
position, negative numbers have 1 in the
leftmost bit position.

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+5 +4 0100 0100 0100
+4 +3 0011 0011 0011 • All three notations representations have

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+3 +2 0010 0010 0010 identical representation if the number is

g g
+1 0001 0001 0001
+2 positive.
+0 0000 0000 0000
+1

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-0 1000 1111 0000
+0 -1 1001 1110 1111
-0 -2 1010 1101 1110

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-3 1011 1100 1101
-1
-4 1100 1011 1100
-2

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-5 1101 1010 1011
-3 -6 1110 1001 1010

o o
-4 -7 1111 1000 1001
-5 -8 ------- ------- 1000

n
-6

K
-7
-8

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Sign magnitude representation

a
• Introduction: - It is the simplest form of representation, where in an n-bit word, the right most n-1 bits
and writing is possible.

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• Advantage: - Easy to read and write, because it is a weighted code system, directly reading

• Disadvantage: - One drawback in sign-magnitude representation is addition and subtraction

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(from LSB) hold the magnitude of the number and nth bit (Left most, MSB) is assigned for sign, where
0à+ve and 1à-ve. require consideration of first signs of the number and second their relative

ge
• Range: - from –(2n-1 – 1) to +(2n-1 – 1) total 2n -1

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magnitude/absolute value in order to carry out the required operation. This idea is used in
real life, but is awkward when employed in computer arithmetic because of the separate
handling of the sign and the magnitude.

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• How to read/write a number: - Convert the magnitude of the number in binary, then write the number
as right as possible, the left most bit must be filled with 0 or 1 according to +ve or -ve number • One more problem is there are two representation for 0, i.e. -0 & +0, because of which there

l l
respectively. is a loss of one presentation, and create confusion.

ow ow
• Number extension : - In computer the size of a location is fixed, so it is often required to write
a smaller number in a larger space, this can be done by sign extension, where, the magnitude
is written as far right as possible, sign bit is written left most, and all the empty cells must be

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filled/padded with zero.

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 t
Q Consider Z = X – Y, where X, Y and Z are all in sign-magnitude form. X
and Y are each represented in n bits. To avoid overflow, the

a e •

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COMPLEMENTS OF NUMBERS
Complements are used in digital computers to simplify the subtraction operation and for

G G
logical manipulation.
representation of Z would require a minimum of (GATE-2019) (1 Marks)
(A) n bits
(C) n + 1 bits
(B) n − 1 bits

g
(D) n + 2 bits
e •

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Simplifying operations leads to simpler, less expensive circuits to implement the operations.

There are two types of complements for each base-r system: the radix complements and the

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diminished radix complement.

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• The first is referred to as the r’s complement and the second as the (r - 1)’s complement.

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9’s Complement
Given a number N in base r having n digits, the (r - 1)’s complement of N, i.e., its diminished •

ate
1’s Complement
For binary numbers, r = 2 and r - 1 = 1, so the 1’s complement of N is (2n - 1) - N.

G G
radix complement, is defined as (rn - 1) - N. • For example, if n = 4, we have 24 = (10000)2 and 24 - 1 = (1111)2.
For decimal numbers, r = 10 and r - 1 = 9, so the 9’s complement of N is (10n - 1) - N.

e e
•
• “The 1’s complement of a binary number is formed by changing 1’s to 0’s and 0’s to 1’s.”
In this case, 10n represents a number that consists of a single 1 followed by n 0’s.

g g
•

10n - 1 is a number represented by n 9’s. • Example:

d d
•

• Example: if n = 4, we have 104 = 10,000 and 104 - 1 = 9999. o The 1’s complement of 1011000 is 0100111.
•

•
Some examples of 9’s complement:
o

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The 9’s complement of 546700 is 999999 - 546700 = 453299.

w
The 9’s complement of 012398 is 999999 - 012398 = 987601.
o

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The 1’s complement of 0101101 is 1010010.

Point to Note e
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•

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The (r - 1)’s complement of octal or hexadecimal numbers is obtained by subtracting each digit from 7 or F (decimal 15),
respectively.

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1’s Complement Representation
• Introduction: - here the negative number is represented by taking complement.

• Range: - from –(2n-1-1) to +(2n-1-1), total 2n -1 representation

a
operations.

ate
• Advantage: - it provides a way to easily understand the 2’s complement system, easy to calculate, used as logical

• Disadvantage: - One drawback in 1’s complement representation is addition and subtraction differ from simple

• How to read/write a number: -

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• how to write a number: - If the number is +ve then number is written same as of the sign magnitude

g
representation, first bit 0 representing the sign of the number, followed by n-1 bits of the magnitude.

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addition and subtraction of arithmetic, Not a weighted code system
• there are two representation for 0, i.e. -0 & +0, because of which there is a loss of one presentation.
• Neither we can write a negative number directly nor we can read a negative number directly, as it is not a
weighted code system.

g
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• But if the number is negative(-x) than first represent its +ve counterpart(+x) then take its 1’s complement of
the number. • Number extension
• 1’s complement of a binary number is obtained by changing each 0 to 1 and each 1 to 0, then we get

l l
• In computer the size of a location is fixed, so it is often required to write a smaller number in a larger space,
representation for -x.
this can be done by sign extension, where,
• we can directly read 2’s complement number and then add 1

w w
• how to read a number: - Similarly to read a number, if first bit is 0 then read it directly, otherwise take 1’s • if the number is positive extension is done same as that of sign magnitude extension.
complement of the number, then read the number if it is +x, then number was -x.

o o
• If the number is -ve then we must write the number as far right as possible and then all the empty cells must
• we can directly write 2’s complement number and then subtract 1
be filled with 1(in negative logic 0 is represented by 1).

Kn www.knowledgegate.in Kn www.knowledgegate.in

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2’s Complement Representation

a
• Introduction: - if 1 is added to 1’s complement of a binary number, the resulting number known as the 2’s
• How to Read: -

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• Similarly, to read a number, if first bit is 0 then read it directly,

a
• otherwise if it is a negative number(-x) first subtract 1 from it to make it 1’s complement of the number, then

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complement of the binary number. take 1’s complement, then read the number(+x) and then change its sign as number was -x.

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• Range: - from –(2n-1) to +(2n-1-1), total 2n representation • a number written in 2’c can be read directly, with the following formula. Value = (-1)(an-12n-1)+ ∑$%&
!"# ai. 2
i

• How to Write: -

ed g
• If the number is +ve then number is written same as that of the sign magnitude representation, first bit 0
representing the sign of the number, followed by the magnitude.
• Number extension

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• In computer the size of a location is fixed, so it is often required to write a smaller number in a
larger space, this can be done by sign extension, where,

l
• But if the number is negative(-x) than first represent its +ve counterpart then take its 1’s complement of the
number by changing each 0 to 1 and each 1 to 0 and then add 1 to it, to make it 2’s complement(-x).

w wl
• if the number is positive extension is done same as that of sign magnitude extension.
• If the number is -ve then we must write the number as far right as possible and then all the empty
cells must be filled with 1(in negative logic 0 is represented by 1).

o o
• Another direct method possible, where first 1 denotes the negative magnitude and the remaining 1
represent the positive magnitude.

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• Value = (-1)(an-12n-1)+ ∑$%&
!"# ai. 2
i

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• Advantage: -

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• Easy to do arithmetic operations with 2’s complement representation. As end round carry can be discarded.

a
• Has only one representation for zero which is always positive, therefore provides better clarity, efficiency and

ate
Q Let R1 and R2 be two 4-bit registers that store numbers in 2’s complement form. For the
operation R1+R2, which one of the following values of R1 and R2 gives an arithmetic overflow?
(GATE 2022) (1 MARKS)

G G
more range with no wastage.
(A) R1 = 1011 and R2 = 1110

e e
• It is a waited code system, direct reading and writing is possible.

g g
• Most popular representation used all the computers.
(B) R1 = 1100 and R2 = 1010

ed ed
• Disadvantage: -
• One drawback in 2’s complement representation is relatively difficult to understand. But in application like (C) R1 = 0011 and R2 = 0100

l l
floating point representation it is not much required, and it takes more space.
(D) R1 = 1001 and R2 = 1111

ow ow
Kn www.knowledgegate.in Kn www.knowledgegate.in
(GATE-2019) (2 Marks)

ate
Q In 16-bit 2’s complement representation, the decimal number −28 is

te
Q When two 8-bit numbers A7...A0 and B7...B0 in 2’s complement representation

a
(with A0 and B0 as the least significant bits) are added using a ripple-carry adder,

G G
the sum bits obtained are S7...S0 and the carry bits are C7...C0. An overflow is said to
(A) 1111 1111 0001 1100

e e
have occurred if (GATE-2017) (2 Marks)

g g
(A) the carry bit C7 is 1 (B) all the carry bits (C7,…,C0) are 1

ed ed
(B) 0000 0000 1110 0100
(C) (D)

wl
(C) 1111 1111 1110 0100

wl
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(D) 1000 0000 1110 0100

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te
Q The 16-bit 2’s complement representation of an integer is 1111 1111

a
1111 0101; its decimal representation is __________.(GATE-2016) (1 in (GATE- 2016) (1 Marks)

ate
Q The addition of 4-bit, two’s complement, binary numbers 1101 and 0100 results

G G
Marks)
(A) 0001 and an overflow
1111 1111 1111 0101
d ge (B) 1001 and no overflow

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(C) 0001 and no overflow
e
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(D) 1001 and an overflow

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ate
Q Let X be the number of distinct 16-bit integers in 2’s complement representation.
Let Y be the number of distinct 16-bit integers in sign magnitude representation.
Then X-Y is? (GATE-2016) (2 Marks)
te
Q The smallest integer that can be represented by an 8-bit

a
number in 2’s complement form is (GATE-2013) (1 Marks)

(a) 1

geG geG
ed ed
(b) 2

(c) 3

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te
Q P is a 16-bit signed integer. The 2's complement representation of P is (F87B)16.

a
The 2's complement representation of 8*P is (GATE-2010) (2 Marks)

ate
Q A processor that has carry, overflow and sign flag bits as part of its program status word (PSW)
performs addition of the following two 2’s complement numbers 01001101 and 11101001. After
the execution of this addition operation, the status of the carry, overflow and sign flags,

G G
respectively will be: (GATE-2008) (2 Marks)
a) (C3D8)16
F87B
ge (A) 1, 1, 0

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b) (187B)16
(B) 1, 0, 0

wl
c) (F878)16

wl
(C) 0, 1, 0

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d) (987B)16

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(D) 1, 0, 1

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te
Q We consider the addition of two 2’s complement numbers bn-1 bn-2 …b 0 and a n-1a n-2…a 0. A

a
binary adder for adding unsigned binary numbers is used to add the two numbers. The sum is
denoted by c n-1c n-2…c 0 and the carry-out by cout. Which one of the following options correctly
result in an overflow? (GATE-2004) (2 Marks)
(i) 1100 + 1100 (ii) 0011 + 0111
ate
Q Using a 4-bit 2’s complement arithmetic, which of the following additions will

(iii) 1111 + 0111

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identifies the overflow condition? (GATE-2006) (2 Marks)

ge (A) (i) only

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(B) (ii) only

wl wl
(C) (iii) only

(D) (i) and (iii) only

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 te
Subtraction with Complements

a
• The subtraction of two n-digit unsigned numbers M - N in base r can be done as follows:
• Note

ate
o M has five digits and N has only four digits. Both numbers must have the same number of digits, so we write
N as 03250.

G G
o Add the minuend M to the r’s complement of the subtrahend N. Mathematically, M + (rn - N) = M - N + rn.
o Taking the 10’s complement of N produces a 9 in the most significant position. The occurrence of the end

e e
o If M ≥ N, the sum will produce an end carry rn , which can be discarded; what is left is the result M - N. carry signifies that M ≥ N and that the result is therefore positive.

g g
o If M < N, the sum does not produce an end carry and is equal to rn - (N - M), which is the r’s complement of • Example: Using 10’s complement, subtract 3250 - 72532.
(N - M). To obtain the answer in a familiar form, take the r’s complement of the sum and place a negative

ed ed
sign in front.

l l
Example: Using 10’s complement, subtract 72532 - 3250.

ow ow
Kn www.knowledgegate.in Kn www.knowledgegate.in

Arithmetic Subtraction
•

ate
Subtraction of two signed binary numbers when negative numbers are in 2’s-complement form is simple and can be stated as
follows:
Gray Code

•
BINARY CODES

ate
The reflected binary code (RBC), also known just as reflected binary (RB) or Gray code after Frank

G G
Gray, is an ordering of the binary numeral system such that two successive values differ in only
• Take the 2’s complement of the subtrahend (including the sign bit) and add it to the minuend (including the sign bit). A carry one bit (binary digit).

e e
out of the sign-bit position is discarded. • The reflected binary code was originally designed to prevent spurious output from electromechanical
switches. Today, Gray codes are widely used to facilitate error correction in digital communications

g g
• Computers need only one common hardware circuit to handle both types of arithmetic such as digital terrestrial television and some cable TV systems.
• A binary number is converted to gray code to reduce switching operation.

d d
• The Gray code is used in applications in which the normal sequence of binary numbers generated by
the hardware may produce an error or ambiguity during the transition from one number to the next.

e e
• If binary numbers are used, a change, for example, from 0111 to 1000 may produce an intermediate

l l
erroneous number 1001 if the value of the rightmost bit takes longer to change than do the values of
the other three bits. This could have serious consequences for the machine using the information.
• The Gray code eliminates this problem, since only one bit changes its value during any transition

w w
between two numbers.
• Gray Code is an unweighted code. In gray code two successive values differ in only 1 bit.

o o
• Application
Some points to remember o Position encoders

n n
o Mathematical puzzles
• There can be certain cases of overflow in the addition such as if we take 6 + 4 = 10, in signed binary numbers (4
o Genetic algorithms

K K
digits) there is no way we can represent 10 using 4 bits. Similarly, if we take -6 + -4 = -10, this can also be not o Boolean circuit minimization
represented in signed binary numbers (4 digits). o Error correction

• In case we take a positive and a negative integer to add there can never be a condition of overflow.
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ate
Binary-Coded Decimal Code (BCD)
In computing and electronic systems, binary-coded decimal (BCD) is a class of binary encodings of decimal numbers where
each decimal digit is represented by a fixed number of bits, usually four or eight.
• A number with k decimal digits will require 4k bits in BCD.
• A group of 4 bits represents one decimal digit.

ate
• A decimal number in BCD is the same as its equivalent binary number only when the number
•

•
represent the range 0 to 9.

g G
BCD typically encodes two decimal digits within a single byte by taking advantage of the fact that four bits are enough to

e
BCD's main virtue is its more accurate representation and rounding of decimal quantities as well as an ease of conversion into
human-readable representations, in comparison to binary positional systems special used to represent currency value. BCD's
is between 0 and 9.

Decimal No

geGBCD Representation

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principal drawbacks are a small increase in the complexity of the circuits needed to implement basic arithmetic and a slightly 0 0000
less dense storage. 1 0001

l l
• BCD was used in many early decimal computers, and is implemented in the instruction set of machines such as the IBM 2 0010
System/360 series and its descendants, Digital Equipment Corporation's VAX, the Burroughs B1700, and the Motorola 68000- 3 0011
series processors.

w w
4 0100
• Although BCD per se is not as widely used as in the past and is no longer implemented in newer computers' instruction sets 5 0101

o o
(such as ARM; x86 does not support its BCD instructions in long mode any more), decimal fixed-point and floating- 6 0110
point formats are still important and continue to be used in financial, commercial, and industrial computing, where subtle 7 0111

Kn Kn
conversion and fractional rounding errors that are inherent in floating point binary representations cannot be tolerated.
8 1000
9 1001

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•
•
0’s.

ate
A BCD number greater than equal to 10 looks different from its equivalent binary number, even though both contain 1’s and

Moreover, the binary combinations 1010 through 1111 are not used and have no meaning in BCD.
Example: (185)10 = (0001 1000 0101) in BCD = (10111001)2
•
Excess-3 Code

ate
Excess-3, 3-excess or 10-excess-3 binary code (often abbreviated as XS-3, 3XS or X3)
or Stibitz code (after George Stibitz, who built a relay-based adding machine in 1937) is a
Decimal
0
1
Excess-3
0011
0100

G G
• 1 - 0001, 8 – 1000 and 5 – 0101 self-complementary binary-coded decimal (BCD) code and numeral system. 2 0101

e e
• The BCD value has 12 bits to encode the characters of the decimal value, but the equivalent binary number needs only 8 bits. • It is a biased representation. Excess-3 code was used on some older computers as well as in 3 0110
It is obvious that the representation of a BCD number needs more bits than its equivalent binary value. cash registers and hand-held portable electronic calculators of the 1970s, among other 4 0111

g g
•
• The advantage is that it is important to realize that BCD numbers are decimal numbers and not binary numbers, although uses. 5 1000

ed ed
they use bits in their representation. • To encode a number such as 127, one simply encodes each of the decimal digits as above, 6 1001
• The only difference between a decimal number and BCD is that decimals are written with the symbols 0, 1, 2, …, 9 and BCD giving (0100, 0101, 1010).
• Excess-3 arithmetic uses different algorithms than normal non-biased BCD or 7 1010

l l
numbers use the binary code 0000, 0001, 0010, .., 1001. The decimal value is exactly the same.
binary positional system numbers. After adding two excess-3 digits, the raw sum is excess-6. 8 1011
Some Points to Remember For instance, after adding 1 (0100 in excess-3) and 2 (0101 in excess-3), the sum looks like 6 9 1100

w w
(1001 in excess-3) instead of 3 (0110 in excess-3).
• BCD code is an example of weighted code. • In order to correct this problem, after adding two digits, it is necessary to remove the extra
In a weighted code, each bit position is assigned a weighting factor in such a way that each digit can be evaluated by adding

o o
• bias by subtracting binary 0011 (decimal 3 in unbiased binary).
the weights of all the 1’s in the coded combination.

n n
• The BCD code has weights of 8, 4, 2, and 1, which correspond to the power of two values of each bit. The bit assignment
0110, for example, is interpreted by the weights to represent decimal 6 because 8 * 0 + 4 * 1 + 2 * 1 + 1 * 0 = 6.

K www.knowledgegate.in K www.knowledgegate.in

•
•
Excess-3 codes are examples of self-complementing codes.

te
Excess-3 Code

a
Such codes have the property that the 9’s complement of a decimal number is obtained directly by changing 1’s to 0’s and 0’s

•
•

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to 1’s (i.e., by complementing each bit in the pattern).
Excess-3 is an unweighted code in which each coded combination is obtained from the corresponding binary value plus 3.
Example: 395 in decimal will be represented in excess-3 code as:
0110 1100 1000.

g
ed
3 9 5

l
• 3 in excess-3 representation is: 3 + 3 = 6 (0110)
• 9 in excess-3 representation is: 9 + 3 = 12 (1100)
5 in excess-3 representation is: 5 + 3 = 8 (1000)

w
•
• 9’s Complement of 395: 999-395 = 604, its excess-3 representation would be: 1001 0011 0111, which can be obtained by

o
simply doing a bitwise complementation of 395 excess-3 code.

Kn www.knowledgegate.in