CONTENTS

Module-3

 Latches
 Flip flops
 Flip flop conversions
 Finite State Machine – design using mealy and Moore state machines
 Sequence detectors and generators design
 Shift Registers
 Counters-synchronous and asynchronous counters
 Ring and Johnson counters

Sequential Logic Circuit Design 2

 CONTENTS

Lecture-9

 Shift Registers Applications

Sequential Logic Circuit Design 3

 BOOKS

Textbooks

1. M.Morris Mano, Michael D Ciletti, Digital Design, 5th edition, Pearson Publishers, 2013.
2. R.P. Jain, “Modern Digital Electronics”, 4th edition, TMH.

References

1. M.Morris Mano, Charles R. Kime, Tom Martin, Logic and Computer Design Fundamentals, 4th edition,
Pearson Publishers.
2. C. H. Roth and L. L. Kinney, Fundamentals of Logic Design, 5th edition, Cengage Publishers.

Sequential Logic Circuit Design 4

Sequential Logic Circuit Design 5
 SHIFT REGISTER APPLICATIONS

 Converting between serial data and parallel data

 Temporary storage in a processor
 Scratch-pad memories
 Some arithmetic operations
 Multiply, divide, Serial Addition
 Communications
 UART
 Some counter applications
 Ring counter
 Johnson counter
 Linear Feedback Shift Register (LFSR) counters
 Sequence Generator
 Time delay devices

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 SHIFT REGISTER APPLICATIONS

Parallel Data Transfer

 All data transfers on rising

clock edge.
 Data clocked into register Y.

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 SHIFT REGISTER APPLICATIONS

Parallel vs Serial

 Serial communications is defined as

 Provides a binary number as a sequence of binary digits, one after another, through one data line.

 Parallel communications
 Provides a binary number through multiple data lines at the same time.

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 SHIFT REGISTER APPLICATIONS

Parallel-to-serial conversion for serial transmission

parallel outputs

parallel inputs

serial transmission

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 SERIAL TRANSFER OF DATA

 Transfer from register X to

register Y

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 SERIAL TRANSFER OF DATA

Example: Serial Transfer of Data from register A to register B

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 SERIAL TRANSFER OF DATA

Example:

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 PATTERN RECOGNIZER

 Combinational function of input samples

 in this case, recognizing the pattern 1001 on the single input signal
OUT

OUT1 OUT2 OUT3 OUT4

IN D Q D Q D Q D Q
CLK
Clk IN OUT1 OUT2 OUT3 OUT4 OUT
Before
1 1 0 0 0 0 0
2 0 1 0 0 0 0
3 0 0 1 0 0 0
4 1 0 0 1 0 0
5 0 1 0 0 1 1

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 SERIAL ADDER

 Operations in digital computers are usually done in parallel because that is a faster mode of
operation.
 Serial operations are slower because a data path operation takes several clock cycles, but serial
operations have the advantage of requiring fewer hardware components.
 The parallel adder is a combinational circuit, whereas the serial adder is a sequential circuit.
 The parallel adder uses registers with a parallel load, whereas the serial adder uses shift
registers.
 The number of full‐adder circuits in the parallel adder is equal to the number of bits in the
binary numbers, whereas the serial adder requires only one full‐adder circuit and a carry
flip‐flop.

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SERIAL ADDER

Sequential Logic Circuit Design 15

 SERIAL ADDER

Operation
 Initially, register A holds the augend, register B holds the addend, and the carry flip‐flop is cleared to 0.
 The outputs (SO) of A and B provide a pair of significant bits for the full adder at x and y. Output Q of
the flip‐flop provides the input carry at z.
 The shift control enables both registers and the carry flip‐flop, so at the next clock pulse, both registers
are shifted once to the right, the sum bit from S enters the leftmost flip‐flop of A, and the output carry
is transferred into flip‐flop Q.
 The shift control enables the registers for a number of clock pulses equal to the number of bits in the
registers. For each succeeding clock pulse, a new sum bit is transferred to A, a new carry is transferred
to Q, and both registers are shifted once to the right.
 This process continues until the shift control is disabled. Thus, the addition is accomplished by passing
each pair of bits together with the previous carry through a single full‐adder circuit and transferring the
sum, one bit at a time, into register A.

Sequential Logic Circuit Design 16

 SERIAL ADDER

 With this adder, more than two binary numbers can be added.
 Initially, register A and the carry flip‐flop are cleared to 0, and then the first number is added
from B.
 While B is shifted through the full adder, a second number is transferred to it through its
serial input.
 The second number is then added to the contents of register A , while a third number is
transferred serially into register B.
 This can be repeated to perform the addition of two, three, or more four‐bit numbers and
accumulate their sum in register A.

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 UNIVERSAL SHIFT REGISTER

 A register capable of shifting in one direction only is a unidirectional shift register. One that can shift in
both directions is a bidirectional shift register.
 If the register has both left and right shift operations and parallel‐load capabilities, it is referred to as a
universal shift register.
 A Universal shift register has following operations

 Shift right control: serial input and output lines

 Shift left control: serial input and output lines
 Parallel load control: n input lines for parallel transfer and n parallel output lines
 Unchanged state control: A control state the leaves the information in the register unchanged in
response to clock.

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 UNIVERSAL SHIFT REGISTER

 MSB_in: for right shift operation

 LSB_in: for left shift operation
 I_par: Parallel input lines
 A_par: Parallel output lines
 S0 and S1 are the selection lines
 Clear_b: clear all the flip-flops

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 UNIVERSAL SHIFT REGISTER

 Shift registers are often used to interface digital systems situated remotely from each other.

Sequential Logic Circuit Design 20

 UNIVERSAL SHIFT REGISTER

 Shift registers are often used to interface digital systems situated remotely from each other.

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UNIVERSAL SHIFT
REGISTER

S1 S0 = 0 0

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UNIVERSAL SHIFT
REGISTER

S1 S0 = 0 1

Sequential Logic Circuit Design 23

UNIVERSAL SHIFT
REGISTER

S1 S0 = 1 0

Sequential Logic Circuit Design 24

UNIVERSAL SHIFT
REGISTER

S1 S0 = 1 1

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 UNIVERSAL SHIFT REGISTER

 When s1s0 = 00, the present value of the register is applied to the D inputs of the flip‐flops. This
condition forms a path from the output of each flip‐flop into the input of the same flip‐flop, so
that the output recirculates and no change of state occurs.
 When s1s0 = 01, terminal 1 of the multiplexer inputs has a path to the D inputs of the flip‐flops.
This causes a shift‐right operation, with the serial input transferred into flip‐flop A3. (data
enters MSB_in)
 When s1s0 = 10, a shift‐left operation results, with the other serial input going into flip‐flop A0.
(data enters in LSB_in)
 Finally, when s1s0 = 11, the binary information on the parallel input lines is transferred into the
register simultaneously during the next clock edge.

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Sequential Logic Circuit Design 27