CONTENTS

Module-3

 Latches
 Flip flops
 Flip flop conversions
 Finite State Machine – design using mealy and Moore state machines
 Sequence detectors and generators design
 Shift Registers
 Counters-synchronous and asynchronous counters
 Ring and Johnson counters

Sequential Logic Circuit Design 2

 CONTENTS

Lecture-6

 State Reduction
 State Assignment
 Sequential Circuit Design: FSM Design

Sequential Logic Circuit Design 3

 BOOKS

Textbooks

1. M.Morris Mano, Michael D Ciletti, Digital Design, 5th edition, Pearson Publishers, 2013.
2. R.P. Jain, “Modern Digital Electronics”, 4th edition, TMH.

References

1. M.Morris Mano, Charles R. Kime, Tom Martin, Logic and Computer Design Fundamentals, 4th edition,
Pearson Publishers.
2. C. H. Roth and L. L. Kinney, Fundamentals of Logic Design, 5th edition, Cengage Publishers.

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 STATE REDUCTION

 In analysis of sequential circuits, the sequence is

 However, the design of sequential circuits follow the sequence as

 Two sequential circuits may exhibit the same input–output behavior but have a different
number of internal states in their state diagram.
 The reduction in the number of flip-flops in a sequential circuit is referred to as the state-
reduction problem which means procedures for reducing the number of states in a state
table, without changing external input–output requirements.

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 STATE REDUCTION

 Since m flip-flops produce 2m states, a reduction in the

number of states may (or may not) result in a reduction in
the number of flip-flops. However, the new design may
require more combinational gates to realize its next state
and output logic.
Example:
 A sequential circuit is considered whose specification is
given in the state diagram. In this example, only the input–
output sequences are considered, however, the states
marked inside the circles are denoted by letter symbols
instead of their binary values.

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 STATE REDUCTION

 There are an infinite number of input sequences that may be applied

to the circuit; each results in a unique output sequence. As an
example, consider the input sequence
01010110100
starting from the initial state a.
 From the state diagram, we obtain the output and state sequence for
the given input sequence as follows: With the circuit in initial state a,
an input of 0 produces an output of 0 and the circuit remains in state
a. With present state a and an input of 1, the output is 0 and the next
state is b. With present state b and an input of 0, the output is 0 and
the next state is c. Continuing this process, we find the complete
sequence to be as follows in the next slide:

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 STATE REDUCTION

 The sequence is obtained as

From the state table,

it can be observed
that states e and g are
equivalent and one of
these state can be
removed

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 STATE REDUCTION

 The reduced state table by removing g and replacing it by e is given as

Again, from the

reduced state table, it
can be observed that
states d and f become
equivalent and one of
these state can be
removed

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 STATE REDUCTION

 The reduced state table by removing f and replacing it by d is given as

 The new state diagram is shown in the figure.

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 STATE ASSIGNMENT

 In order to design a sequential circuit with physical components, it is necessary to assign unique coded
binary values to the states.
 For a circuit with m states, the codes must contain n bits, where 2n ≥ m.
 For example, with three bits, it is possible to assign codes to eight states, denoted by binary numbers
000 through 111.
 Consider the previous example, the state
table is having 5 states, we must assign
binary values to 8 states; the remaining
states are unused. Hence, unused are
treated as don’t-care conditions during the
design.

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 STATE ASSIGNMENT

 The possible way of assignments are

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 STATE ASSIGNMENT

 The reduced state table after binary assignment

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 SEQUENTIAL CIRCUIT DESIGN: FSM DESIGN

 Design procedures or methodologies specify the hardware that will implement a desired
behavior.
 Design of clocked sequential circuits is very much the opposite of the analysis.

 The design of a clocked sequential circuit starts from a set of specifications and culminates
in a logic diagram or a list of Boolean functions from which the logic diagram can be
obtained.
 The first step in the design of sequential circuits is to obtain a state table or an equivalent
representation, such as a state diagram.

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 SEQUENTIAL CIRCUIT DESIGN: FSM DESIGN

Design Procedure:

1. From the word description and specifications of the desired operation, derive a state diagram for the
circuit.
2. Reduce the number of states if necessary (State reduction to reduce the number of Flip-flops).
3. Assign binary values to the states. (State Assignment)
4. Obtain the binary-coded state table.
5. Choose the type of flip-flops to be used.
6. Derive the simplified flip-flop input equations and output equations.
7. Draw the logic diagram.

Steps 4 through 7 in the design is accomplished by exact algorithms and is automated. This part of the
design procedure is known as synthesis.

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 SEQUENTIAL CIRCUIT DESIGN: FSM DESIGN

Example (Sequence Detector):

 Design a circuit that detects a sequence of three or more consecutive 1’s in a string of bits coming
through an input line (i.e., the input is a serial bit stream ).
 It is derived by starting with state S0, the reset state. If the input is 0, the circuit stays in S0, but if the
input is 1, it goes to state S1 to indicate that a 1 was detected. If the next input is 1, the change is to
state S2 to indicate the arrival of two consecutive 1’s, but if the input is 0, the state goes back to S0.
The third consecutive 1 sends the circuit to state S3. If more 1’s are detected, the circuit stays in S3.
 Any 0 input sends the circuit back to S0. In this way,
the circuit stays in S3 as long as there are three or State S0 : zero 1s detected
more consecutive 1’s received. State S1 : one 1 detected
 This is a Moore model sequential circuit, since the State S2 : two 1s detected
State S3 : three 1s detected
output is 1 when the circuit is in state S3 and is 0 otherwise.

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 SEQUENTIAL CIRCUIT DESIGN: FSM DESIGN

Solution:

Step 1: (State Diagram)

 The state diagram is obtained from the description given.

 Here, state reduction technique is not applied, so we can apply state
assignment technique.
Step 2: (State Assignment)

 Here, two D flip-flops are used to represent the 4 states, and we label
their outputs as A and B. There is one input x and one output y.
 The characteristic equation of the D flip-flop is
Q(t + 1) = DQ
which means that the next-state values in the state table specify the D input of the flip-flop.

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 SEQUENTIAL CIRCUIT DESIGN: FSM DESIGN

Step 3: (State Table)

State Assignment

S0 A=0 & B=0

S1 A=0 & B=1

S2 A=1 & B=0

S3 A=1 & B=1

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 SEQUENTIAL CIRCUIT DESIGN: FSM DESIGN

Step 4: (State Equations)

 The flip-flop input equations can be obtained directly from the next-state columns of A and B and
expressed in sum-of-minterms form

Q(t + 1) = DQ

DQ Q(t+1)

 However, we can minimize the above function using K-map.

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 SEQUENTIAL CIRCUIT DESIGN: FSM DESIGN

Step 4: (State Equations)

 The simplified equations are

DA = Ax + Bx
DB = Ax + B’x
y = AB
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 SEQUENTIAL CIRCUIT DESIGN: FSM DESIGN

Step 5: (Logic Diagram)

• The advantage of designing

with D flip-flops is that the
Boolean equations
describing the inputs to the
flip-flops can be obtained
directly from the state
table.

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