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Assignment 2

Uploaded by

areychacha
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© © All Rights Reserved
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Assignment-2 Digital Logic

Assignment 2
Note: Attempt any two questions from the following [5 Marks Each]
1.Explain the differences between volatile and non-volatile memory
technologies

Volatile Memory:
1. Loses data when power is off
2. Faster access times
3. Lower latency
4. Used for main memory (RAM)
Examples:
1. DRAM (Dynamic RAM)
2. SRAM (Static RAM)
Non-Volatile Memory:
1. Retains data when power is off
2. Slower access times
3. Higher latency
4. Used for storage (Hard Drives, SSDs)
Examples:
1. ROM (Read-Only Memory)
2. Flash Memory
3. EEPROM (Electrically Erasable Programmable Read-Only Memory)
4. Hard Disk Drives (HDD)
5. Solid-State Drives (SSD)

2,Describe the concept of a hierarchical memory system in computer


architecture. Explain
why hierarchical memory systems are utilized in modern computer
designs.

A hierarchical memory system consists of multiple levels of memory with varying


sizes, speeds,
and costs. The levels are:
1. Registers (smallest, fastest)
2. Cache Memory (small, fast)
3. Main Memory (RAM, larger, slower)
4. Secondary Storage (Hard Drives, SSDs, largest, slowest)

Characteristics:
1. Speed: Decreases from top to bottom
2. Size: Increases from top to bottom
3. Cost: Decreases from top to bottom
4. Access Time: Increases from top to bottom

Pranjal Vyas URN:2024-B-31012005


Assignment-2 Digital Logic

Why Hierarchical Memory Systems are Utilized:


1. Balances performance and cost
2. Optimizes data access times
3. Reduces memory access latency
4. Increases overall system efficiency
5. Supports large programs and data
6. Enhances multitasking capabilities

Benefits:
1. Improved performance
2. Increased capacity
3. Better resource utilization
4. Cost-effectiveness

Modern Computer Designs:


Hierarchical memory systems are essential in modern computers due to:
1. Processing speed increases
2. Memory demand growth
3. Cost constraints
4. Performance optimization needs

Note: Attempt any two questions from the following [10 Marks Each]

1.What are associative caches in computer architecture? Explain their


advantages and
disadvantages compared to other cache types with the help of
examples.

Associative caches are a type of cache memory that stores data in a


content-addressable memory
(CAM), allowing for fast retrieval of data based on its content.
Characteristics:
1. Fast search times
2. Flexible mapping
3. High hit rates
Advantages:
1. Fast data retrieval
2. Efficient use of cache space
3. Good for applications with irregular access patterns
Disadvantages:
1. Complex and expensive
2. Power-hungry
3. Limited scalability

Pranjal Vyas URN:2024-B-31012005


Assignment-2 Digital Logic

Comparison to Other Cache Types:


Cache Type | Advantages | Disadvantages
———-——|—————————|———————
Direct-Mapped | Simple, low power | Collision-prone
Set-Associative | Balances speed | Limited flexibility
Fully-Associative| | Fast search times | Complex, expensive
Examples:
1. CPU caches (L1, L2) use associative caching for fast instruction and data retrieval.
2. Translation Lookaside Buffers (TLBs) use associative caching for fast
virtual-to-physical address
translation.
3. Graphics processing units (GPUs) use associative caching for fast texture and
vertex data
Retrieval.

2.Describe various cache write strategies. Compare these strategies in


terms of their impact
on cache performance and system efficiency with the help of examples.
—>
Cache Write Strategies:
1. Write Through (WT): Write to both cache and main memory simultaneously.
2. Write Back (WB): Write to cache, update main memory when block is replaced.
3. Write Allocate (WA): Allocate cache block on write miss, write to both cache and
main memory.
4. Write No Allocate (WNA): Do not allocate cache block on write miss, write directly
to main
memory.
5. Cache Bypass: Bypass cache for write operations.

Examples:
1. Web browsers use WB strategy for caching frequently accessed data.
2. Database systems use WT strategy for ensuring data consistency.
3. Real-time systems use WA strategy for predictable performance.
Impact on Cache Performance and System Efficiency:
1. WB strategy improves performance by reducing memory traffic.
2. WT strategy ensures data consistency but increases memory traffic.
3. WA strategy balances performance and memory traffic.

Pranjal Vyas URN:2024-B-31012005


Assignment-2 Digital Logic

4. WNA strategy reduces memory traffic but increases cache misses.

Note: Attempt any two questions from the following [20 Marks]

1.Define tiled chip multicore processors (TCMPs) and elucidate their


advantages over conventional multicore architectures. Additionally,
enumerate and elaborate on three fundamental design considerations
that architects must account for when developing TCMPs.

TCMPs are multicore architectures where multiple processing cores are integrated
onto a single
chip, divided into tiles, each containing a core, cache, and interconnect.
Advantages over Conventional Multicore Architectures:

1. Scalability: Easier to add/remove tiles


2. Power efficiency: Reduced power consumption
3. Flexibility: Heterogeneous core configurations
4. Performance: Improved cache coherence and interconnect

Fundamental Design Considerations:


1. Tile Architecture:
- Core design and configuration
- Cache hierarchy and size
- Interconnect topology and bandwidth

2. Inter-Tile Communication:
- Network-on-Chip (NOC) design
- Communication protocols and latency
- Data coherence and consistency

3. Thermal and Power Management:


- Thermal modeling and simulation
- Power gating and voltage regulation
- Cooling systems and thermal interfaces
Key Benefits:
1. Improved performance/watt
2. Increased scalability
3. Enhanced flexibility
4. Better resource utilization

Examples:
1. Intel's Teraflops Research Chip
2. MIT's Raw Processor

Pranjal Vyas URN:2024-B-31012005


Assignment-2 Digital Logic

3. Tilera's Tile-Gx Processors

2.Compare and contrast two routing algorithms utilized within


Network-on-Chip
(NoC) architectures. Furthermore, elaborates on the significance of
flow control
techniques within NoC routers, highlighting their role in enhancing
communication
efficiency among cores.

Algorithm 1: XY Routing
1. Simple and efficient
2. Packet routes through shortest path
3. Low latency
Algorithm 2: DyAD Routing
1. Adaptive and flexible
2. Routes around congested areas
3. High throughput
Contrast:
1. XY Routing: Deterministic, low latency, but prone to congestion
2. DyAD Routing: Adaptive, high throughput, but higher complexity
Significance of Flow Control Techniques:
Flow control manages buffer occupancy and prevents packet loss.
Techniques:
1. Credit-based flow control
2. On/off flow control
3. Xon/Xoff flow control
Role:
1. Prevents packet loss and buffer overflow
2. Enhances network throughput and latency
3. Ensures reliable data transfer
Key Flow Control Considerations:
1. Buffer size and allocation
2. Packet injection rate
3. Network congestion management
NoC Router Components:
1. Routing computation
2. Switching fabric
3. Buffer management
4. Flow control
Optimized flow control enhances NoC performance:
1. Reduced latency
2. Increased throughput
3. Improved network reliability

Pranjal Vyas URN:2024-B-31012005


Assignment-2 Digital Logic

Examples:
1. Intel's Teraflops Research Chip
2. Tilera's Tile-Gx Processors

Pranjal Vyas URN:2024-B-31012005

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