RAJ KUMAR GOEL INSTITUTE OF TECHNOLOGY

5thKM Stone Delhi, Meerut Road, Near Raj Nagar Extension Road, Ghaziabad, UP-201003
Approved by AICTE, N. Delhi &Affiliated to Dr. A.P.J. Abdul Kalam Technical University, Lucknow
NBA Accredited Program (B. Tech- ECE, IT) & B. Pharmacy

LABORATORY RECORD

Faculty Name : Mr. Sanjay Srivastava Department : CSE

Course Name : Computer Organization Lab Course Code : BCS-352

Year/Sem : 2nd/3rd NBA Code : B 207

Email ID : [email protected] Academic Year : 2023-24

Department of Computer Science & Engineering

 Raj Kumar Goel Institute of Technology, Ghaziabad
Department of Computer Science & Engineering

VISION OF THE INSTITUTE

To continually develop excellent professionals capable of providing sustainable solutions to
challenging problems in their fields and prove responsible global citizens.
MISSION OF THE INSTITUTE
We wish to serve the nation by becoming a reputed deemed university for providing value
based professional education.

VISION OF THE DEPARTMENT

To be recognized globally for delivering high quality education in the ever changing field of
computer science & engineering, both of value & relevance to the communities we serve.

MISSION OF THE DEPARTMENT

1. To provide quality education in both the theoretical and applied foundations of Computer
Science and train students to effectively apply this education to solve real world problems.

2. To amplify their potential for lifelong high quality careers and give them a competitive
advantage in the challenging global work environment.

PROGRAM EDUCATIONAL OUTCOMES (PEOs)

PEO 1: Learning: Our graduates to be competent with sound knowledge in field of

Computer Science & Engineering.

PEO 2: Employable: To develop the ability among students to synthesize data and
technical concepts for application to software product design for successful careers
that meet the needs of Indian and multinational companies.

PEO 3: Innovative: To develop research oriented analytical ability among students to

prepare them for making technical contribution to the society.

PEO 4: Entrepreneur / Contribution: To develop excellent leadership quality among

students which they can use at different levels according to their experience and
contribute for progress and development in the society.

Computer Organization & Architecture Lab (BCS-352), CSE III SEM Page 2
SEM))
 Raj Kumar Goel Institute of Technology, Ghaziabad
Department of Computer Science & Engineering

PROGRAM OUTCOMES (POs)

Engineering Graduates will be able to:

PO1: Engineering knowledge: Apply the knowledge of mathematics, science,

engineering fundamentals, and an engineering specialization to the solution of
complex engineering problems.

PO2: Problem analysis: Identify, formulate, review research literature, and

analyze complex engineering problems reaching substantiated conclusions using
first principles of mathematics, natural sciences, and engineering sciences.

PO3: Design/development of solutions: Design solutions for complex

engineering problems and design system components or processes that meet the
specified needs with appropriate consideration for the public health and safety, and
the cultural, societal, and environmental considerations.

PO4: Conduct investigations of complex problems: Use research-based

knowledge and research methods including design of experiments, analysis and
interpretation of data, and synthesis of the information to provide valid conclusions.

PO5: Modern tool usage: Create, select, and apply appropriate techniques,
resources, and modern engineering and IT tools including prediction and modeling to
complex engineering activities with an understanding of the limitations.

PO6: The engineer and society: Apply reasoning informed by the contextual
knowledge to assess societal, health, safety, legal and cultural issues and the
consequent responsibilities relevant to the professional engineering practice.

PO7: Environment and sustainability: Understand the impact of the professional

engineering solutions in societal and environmental contexts, and demonstrate the
knowledge of, and need for s u s t a i n a b l e development.

PO8: Ethics: Apply ethical principles and commit to professional ethics and
responsibilities and norms of t h e engineering practice.

PO9: Individual and team work: Function effectively as an individual, and as a

member or leader in diverse teams, and in multidisciplinary settings.

PO10: Communication: Communicate effectively on complex engineering activities

with the engineering community and with society at large, such as, being able to

Computer Organization & Architecture Lab (BCS-352), CSE III SEM Page 3
SEM))
 Raj Kumar Goel Institute of Technology, Ghaziabad
Department of Computer Science & Engineering

Comprehend a n d write effective r e p o r t s and design documentation, make

effective presentations, and give and receive clear instructions.
PO11: Project management and finance: Demonstrate knowledge and
understanding of the engineering and management principles and apply these to
one’s own work, as a member and leader in a team, to manage projects and in
multidisciplinary environments.

PO12: Life-long learning: Recognize the need for, and have the preparation and
ability to engage in independent and life-long learning in the broadest context of
technological change.

PROGRAM SPECIFIC OUTCOMES (PSOs)

PSO1: The ability to use standard practices and suitable programming environment to
develop software solutions.

PSO2: The ability to employ latest computer languages and platforms in creating innovative
career opportunities.

Computer Organization & Architecture Lab (BCS-352), CSE III SEM Page 4
SEM))
 Raj Kumar Goel Institute of Technology, Ghaziabad
Department of Computer Science & Engineering

COURSE OUTCOMES (COs)

B 207.1 Illustrate HALF ADDER, FULL ADDER using basic logic gates and to learn
various code conversions: Binary -to -Gray, Gray -to –Binary

B 207.2 Design 3-8 line DECODER and Implementing 4x1 and 8x1 MULTIPLEXERS.
Demonstrate excitation tables of various FLIP-FLOPS and design of an 8-bit Input
B 207.3 Output system with four 8-bit Internal Registers.

B 207.4 Design of an 8-bit ARITHMETIC LOGIC UNIT.

B 207.5 Designing of I/O using Registers, ALU and Control Unit and demonstrating the
usage of Register Transfer Language(RTL)/implement on simulators

CO-PO MAPPING

PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12

B 207.1 3 3 3 1 - 1 1 - 2 - 2 2

B 207.2 3 3 3 1 3 1 1 - 2 - 1 2

B 207.3 3 3 3 1 3 1 1 - 2 - 1 1

B 207.4 3 3 3 1 - 1 1 - 2 - 1 1

B 207.5 3 3 3 1 - 1 1 - 2 - 1 2

B 207 3 3 3 1 3 1 1 - 2 - 1.2 1.6

CO-PSO MAPPING

PSO1 PSO2

B 207.1 2 -

B 207.2 2 -

B 207.3 2 -

B 207.4 2 -

B 207.5 2 -

B 207 2 -

Computer Organization & Architecture Lab (BCS-352), CSE III SEM Page 5
SEM))
 Raj Kumar Goel Institute of Technology, Ghaziabad
Department of Computer Science & Engineering

LIST OF EXPERIMENTS

Sr. Title of experiment Corresponding

No. CO
1. Implementing HALF ADDER, FULL ADDER using basic B 207.1
logic gates.
2. Implementing Binary -to -Gray, Gray -to -Binary code
B 207.1
conversions

3. Implementing 3-8 line DECODER

B 207.1

4. Implementing 4x1 and 8x1 MULTIPLEXERS.

B 207.1

5 Verify the excitation tables of various FLIP-FLOPS. B 207.2

6. Design of an 8-bit Input/ Output system with four 8-bit

B 207.3
Internal Registers.

7. Design of an 8- bit ARITHEMATIC LOGIC UNIT. B 207.3

8. Design the data path of a computer from its register transfer

language description. B 207.4

9. Implement a simple instruction set computer with a control

B 207.5
unit and a data path.

Implementing HALF SUBTRACTOR and FULL

10 B 207.1
SUBTRACTOR using basic logic gates

Computer Organization & Architecture Lab (BCS-352), CSE III SEM Page 6
SEM))
 Raj Kumar Goel Institute of Technology, Ghaziabad
Department of Computer Science & Engineering

INTRODUCTION

Computer Organization Lab consists of performing various experiments in Logically

Simulator. This simulator provides an interactive environment for creating and conducting
simulated experiments on computer organization and architecture. It supports gate level
design to CPU design.
The main features of the simulators are as follows:
 Logic: The simulator supports 5 valued logic. So the simulator supports wired AND
for bus based design. These 5 states along with their corresponding wire values are -
True (T) (wire color: blue), False (F) (wire color: black), High impedance (Z) (wire
color: green), Unknown (X) (wire color: maroon), Invalid (I) (wire color: orange)
 Graphical organization of the simulator: The simulator contains a pallete on the right
hand side. This pallete contains all the components and tools . Tools are used to act up
on the components. A toolbar on the top which contains several buttons. These
buttons are - save/open, simulate (after creating a circuit, this button has to be pressed
to simulate the circuit and to get output), plot graph (to plot input-output wave form),
undo/redo, delete, zoom in/zoom out, increment/decrement LED (for digital LED
which can also be used as input and display), start/stop clock pulse, to check the name
or pin configuration of a component, changing connection types, checking the user
identification. A canvas in the middle where the circuits will be designed. A toolbar
on the left side which contains the following buttons - Set Port to set the number of
input and output ports for a circuit, Set Label and set name to set the label contents
and the name of different components, Load Memory to load the memory content to
the inbuilt memory (4 bit address and 12 bit data) for performing the computer design
experiment. Data can be load either from file or through form.
 Components: Components have been categorized according to their functionality and
put into different drawers in the palette. The area under every drawer is scrallable, if
you are unable to see all the components in a particular drawer just click on the area
and scroll. Different drawers - Circuits- contains 8 and 16 terminal circuits and flow
container which can hold other circuit components, Logic gates- contains all kinds of
basic logic gates with 2 and 3 inputs, Display and inputs- contains all kinds of
component needed to give input to the circuit along with free running clock and
displaying outputs of the circuit, Adders- contains different types of adder circuits,
Computer Organization & Architecture Lab (BCS-352) Manual (CSE, III SEM)) Page 7
 Raj Kumar Goel Institute of Technology, Ghaziabad
Department of Computer Science & Engineering

Sequential ckt- contains basic flip-flops, registers for designing sequential circuits,
Other Components- contains different kinds of components like decoders,
multiplexers, arithmetic logic units(ALU), memory elements(RAM cell), cache
memory(without any replacement policy)required to design combinational circuits,
Control Unit- contains a controller whose state table (Moore m/c) can be loaded from
the interface, Computer Design- contains a single instruction CPU and a Memory (4
bit address and 12 bit data, can be loaded by user).

Computer Organization & Architecture Lab (BCS-352) Manual (CSE, III SEM)) Page 8
 Raj Kumar Goel Institute of Technology, Ghaziabad
Department of Computer Science & Engineering

PREFACE

This laboratory manual is designed to have students experience on how to implement

Computer Organization design using Logic Simulator. The idea of writing this lab manual is
to make the undergraduate students aware of the new Computer Organization tools and how
to use them properly & efficiently. This manual serves as a guide for learning and
implementing the designs through the simulator. The manual contains procedures, and pre-
experiment questions to help students prepare for experiments.

This practical manual will be helpful for students of Computer Science & Engineering for
understanding the course from the point of view of applied aspects. Though all the efforts
have been made to make this manual error free, yet some errors might have crept in
inadvertently. Suggestions from the readers for the improvement of the manual are most
welcomed.

Mr.Sanjay Srivastava, Assistant Professor

Mr.Ramveer Singh, Assistant Professor
Dr.Chandramani Tyagi, Professor
Dr. Pramod kumar Sagar, Associate Professor
Department of Computer Science & Engineering

Computer Organization & Architecture Lab (BCS-352) Manual (CSE, III SEM)) Page 9
 Raj Kumar Goel Institute of Technology, Ghaziabad
Department of Computer Science & Engineering

DO’S AND DONT’S

DO’s

1. Conform to the academic discipline of the department.

2. Enter your credentials in the laboratory attendance register.
3. Read and understand how to carry out an activity thoroughly before coming to the
laboratory.
4. Ensure the uniqueness with respect to the methodology adopted for carrying out the
experiments.
5. Shut down the machine once you are done using it.

DONT’S

1. Eatables are not allowed in the laboratory.

2. Usage of mobile phones is strictly prohibited.
3. Do not open the system unit casing.
4. Do not remove anything from the computer laboratory without permission.
5. Do not touch, connect or disconnect any plug or cable without your faculty/laboratory
technician’s permission.

Computer Organization & Architecture Lab (BCS-352) Manual (CSE, III SEM)) Page 10
 Raj Kumar Goel Institute of Technology, Ghaziabad
Department of Computer Science & Engineering

GENERAL SAFETY INSTRUCTIONS

1. Know the location of the fire extinguisher and the first aid box and how to use them in
case of an emergency.

2. Report fires or accidents to your faculty /laboratory technician immediately.

3. Report any broken plugs or exposed electrical wires to your faculty/laboratory

technician immediately.

4. Do not plug in external devices without scanning them for computer viruses.

Computer Organization & Architecture Lab (BCS-352) Manual (CSE, III SEM)) Page 11
 Raj Kumar Goel Institute of Technology, Ghaziabad
Department of Computer Science & Engineering

GUIDELINES FOR LABORTORY RECORD PREPARATION

While preparing the lab records, the student is required to adhere to the following guidelines:

Contents to be included in Lab Records:

1. Cover page
2. Vision
3. Mission
4. PEOs
5. POs
6. PSOs
7. COs
8. CO-PO-PSO mapping
9. Index
10. Experiments
 Aim
 Source code
 Input-Output

A separate copy needs to be maintained for pre-lab written work

The student is required to make the Lab File as per the format given on the next two pages.

Computer Organization & Architecture Lab (BCS-352) Manual (CSE, III SEM)) Page 12
 RAJ KUMAR GOEL INSTITUTE OF TECHNOLOGY
5thKM Stone Delhi, Meerut Road, Near Raj Nagar Extension Road, Ghaziabad, UP-201003
Approved by AICTE, N. Delhi &Affiliated to Dr. A.P.J. Abdul Kalam Technical University, Lucknow
NBA Accredited Program (B. Tech- ECE, IT) & B. Pharmacy

COMPUTER ORGANIZATION & ARCHITECTURE LAB FILE (BCS 352)

Name

Roll No.

Section- Batch
 Raj Kumar Goel Institute of Technology, Ghaziabad
Department of Computer Science & Engineering

INDEX

Experiment Experiment Date of Date of Faculty

No. Name Conduction Submission Signature

Computer Organization & Architecture Lab (BCS-352) (CS, III SEM) Page 15
 Raj Kumar Goel Institute of Technology, Ghaziabad
Department of Computer Science & Engineering

GUIDELINES FOR ASSESSMENT

Students are provided with the details of the experiment (Aim, pre-experimental questions,
procedure etc.) to be conducted in next lab and are expected to come prepared for each lab
class.
Faculty ensures that students have completed the required pre-experiment questions and they
complete the in-lab programming assignment(s) before the end of class. Given that the lab
programs are meant to be formative in nature, students can ask faculty for help before and
during the lab class.
Students’ performance will be assessed in each lab based on the following Lab Assessment
Components:
Assessment Criteria-1: Performance (Max. marks = 5)
Assessment Criteria-2: VIVA (Max. marks = 5)
Assessment Criteria-3: Record (Max. marks = 5)

In each lab class, students will be awarded marks out of 5 under each component head,
making it total out of 15 marks.

Computer Organization & Architecture Lab (BCS-352) (CS, III SEM) Page 16
 Raj Kumar Goel Institute of Technology, Ghaziabad
Department of Computer Science & Engineering

EXPERIMENT 1

Aim: Design and implementation of HALF ADDER, FULL ADDER using basic logic
gates

Equipment & Components Required:

S.No. Equipments Specification Quantity

1 Digital IC Trainer kit - 1
2 Digital Multimeter 1

S.No. Components Specification Quantity

7400, 7402,
7404,
1 each
1 Digital ICs 7408, 7432,
7486.
- 6
2 Patch cords

Theory:

a) To design and implement half adder using logic gates

HALF ADDER
OUTPUTS
INPUT A INPUT B
S C

0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

CIRCUIT DIAGRAM TRUTH TABLE

Computer Organization & Architecture Lab (BCS-352) (CS, III SEM) Page 17
 Raj Kumar Goel Institute of Technology, Ghaziabad
Department of Computer Science & Engineering

b) To design and implement full adder using logic gates

FULL ADDER

CIRCUIT DIAGRAM

TRUTH TABLE

Pre-Experiment Questions:
1.Explain the truth table of half adder.
2. How many EX-OR and OR gates can be used to make a half adder?

Computer Organization & Architecture Lab (BCS-352) (CS, III SEM) Page 18
 Raj Kumar Goel Institute of Technology, Ghaziabad
Department of Computer Science & Engineering

3. How do we convert half adder to full adder?

4.Explain the characteristics of half adder.

Procedure:
• Identify the pins.
• Connect the circuit as per circuit diagram.
• Obtain outputs with various input combinations.
• Verify it with the Boolean function using truth table

Result & Conclusion: All logical circuits have been implemented & verified through truth
table.

Post-Experiment Question:
a. What are the applications of half adder?
b. What are the applications of full adder?
c. Explain the advantages of half adder?
d. Elaborate the advantages of full adder over half adder.

Computer Organization & Architecture Lab (BCS-352) (CS, III SEM) Page 19
 Raj Kumar Goel Institute of Technology, Ghaziabad
Department of Computer Science & Engineering

EXPERIMENT 2

Aim: Design and implementation of Binary to Gray, Gray to Binary Code conversions

Equipment & Components Required:

1S.No. Equipments Specification Quantity

1 Digital IC Trainer kit - 1
2 Digital Multimeter 1

S.No. Components Specification Quantity

7400, 7402,
7404,
1 each
1 Digital ICs 7408, 7432,
7486.
- 6
2 Patch cords

Theory:

a) To design and implement Binary to Gray Code conversions

Pin diagram of Binary to gray code converter using 7486 Ic(Ex-Or Gate)

INPUTS OUTPUTS

Computer Organization & A r c h i t e c t u r e Lab (BCS-352) Manual (CS, III Page 20

SEM)
 Raj Kumar Goel Institute of Technology, Ghaziabad
Department of Computer Science & Engineering

A B C D G4 G3 G2 G1
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
Circuit Diagram of Binary to Gray Code 0 1 1 1 0 1 0 0
Converter 1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

Truth Table

b) To design and implement Binary to Gray Code conversions

Pin diagram of Gray to Binary code converter using 7486 Ic(Ex-Or Gate)

Computer Organization & Architecture Lab (BCS-352) Manual (CS, III SEM) Page 21
 Raj Kumar Goel Institute of Technology, Ghaziabad
Department of Computer Science & Engineering

INPUTS OUTPUTS

A B C D B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
Circuit Diagram for Gray to Binary Code 1 1 0 1 1 0 0 1
Converter 1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0T 0 0 1 1 1 1

Truth Table
Pre-Experiment Questions:
1. What is a code converter?
2. Differentiate between translator and code converter.
3. Explain the primary usage of grey code.
4. Illustrate the reasons for using grey code.

Procedure:
 Collect the components necessary to accomplish this experiment.
 Plug the IC chip into the breadboard.
 Connect the supply voltage and ground lines to the chips. PIN7 = Ground and PIN14
= +5V.
 Make connections as shown in the respective circuit diagram.
 Connect the inputs of the gate to the input switches of the LED.
 Connect the output of the gate to the output LEDs.
 Once all connections have been done, turn on the power switch of the breadboard

Computer Organization & Architecture Lab (BCS-352) Manual (CS, III SEM) Page 22
 Raj Kumar Goel Institute of Technology, Ghaziabad
Department of Computer Science & Engineering

 Operate the switches and fill in the truth table (Write "1" if LED is ON and "0" if L1
is OFF Apply the various combination of inputs according to the truth table and
observe the condition of Output LEDs.

Result & Conclusion: Binary to gray and gray to binary code converter has been designed
using EXOR gate and its truth table verified.

Post-Experiment Question:
1. What are the advantages of code converter?
2. What are the properties of gray code?
3. Describe a way by which we can convert BCD to binary using hardware approach.
4. List the process to generate n bit gray codes.

Computer Organization & Architecture Lab (BCS-352) Manual (CS, III SEM) Page 23
 Raj Kumar Goel Institute of Technology, Ghaziabad
Department of Computer Science & Engineering

EXPERIMENT 3

Aim: Design and implementation of 3-8 line DECODER.

Equipment’s & Components Required :

S.No. Equipment’s Specification Quantity

1 Digital IC Trainer kit - 1
2 Digital Multimeter 1

S.No. Components Specification Quantity

7400, 7402,
7404,
1 Digital ICs 1 each
7408, 7432,
7486.
2 Patch cords - 6

Theory:
a) 4 to 2 encoder using logic gates:

Truth Table Logic Diagram:

I3 I2 I1 I0 O1 O0

0 0 0 1 0 0

0 0 1 0 0 1

0 1 0 0 1 0

1 0 0 0 1 1

Computer Organization & Architecture Lab (BCS-352) Manual (CS, III SEM) Page 24
 Raj Kumar Goel Institute of Technology, Ghaziabad
Department of Computer Science & Engineering

b) 3 to 8 decoder using logic gates:

Symbol: Truth table:

Logic Diagram of 3 to 8 decoder

Pre-Experiment Questions:
1. Difference between Encoder and Decoder.
2. Explain the need of Decoder.
3. Which is the major functioning responsibility of the multiplexing combinational circuit?
4. How many NOT gates are required for the construction of a 4-to-1 multiplexer?
Procedure:
 Collect the components necessary to accomplish this experiment.
 Plug the IC chip into the breadboard.
 Connect the supply voltage and ground lines to the chips. PIN7 = Ground

 and PIN14 = +5V.

 Make connections as shown in the respective circuit diagram.
 Connect the inputs of the gate to the input switches of the LED.
 Connect the output of the gate to the output LEDs.

Computer Organization & Architecture Lab (BCS-352) Manual (CS, III SEM) Page 25
 Raj Kumar Goel Institute of Technology, Ghaziabad
 Once all connections have been done, turn on the power switch of the breadboard
 Operate the switches and fill in the truth table ( Write "1" if LED is ON and "0" if L1
is OFF Apply the various combination of inputs according to the truth table and observe
the condition of Output LEDs.

Result & Conclusion: 3-8 line decoders have been implemented & verified through truth table.

Post Experiment Questions:

1. Design a 5 to 32 decoder using one 2 to 4 and four 3 to 8 decoder IC’S.
2. Write a note on BCD to decimal decoder.

Computer Organization & Architecture Lab (BCS-352) Manual (CS, III SEM) Page 26
 Raj Kumar Goel Institute of Technology, Ghaziabad

EXPERIMENT 4

Aim: Implementing 4x1 MUX and 8x1 MULTIPLEXERS

Equipment’s & Components Required :

S.No. Equipment’s Specification Quantity

1 Digital IC Trainer kit - 1
2 Digital Multimeter 1

S.No. Components Specification Quantity

7400, 7402,
7404,
1 Digital ICs 1 each
7408, 7432,
7486.
2 Patch cords - 6

Theory:

a) 4 to 1 Multiplexer:
Symbol: Truth table:

Addressing Input
Selected
0 0 A
0 1 B
1 0 C
1 1 D

Computer Organization & Architecture Lab (BCS-352) Manual (CS, III SEM) Page 27
 Raj Kumar Goel Institute of Technology, Ghaziabad
Department of Computer Science & Engineering

Logic Diagram:

d) 8x1 Multiplexer

Pin diagram of 8:1 Mux using two 4:1 Mux

Computer Organization & A r c h i t e c t u r e Lab (BCS-352) Manual (CS, III SEM) Page 28
 Raj Kumar Goel Institute of Technology, Ghaziabad
Department of Computer Science & Engineering

Circuit of 8:1 Mux using dual 4:1 Mux

Truth Table of 8:1 Mux Using Dual 4:1 Mux

Select Lines Inputs Output

Ea S0 S1 Io I1 I2 I3 I4 I5 I6 I7 Za Zb Y

0 0 0 0 × × × × × × × 0 × 0
0 0 0 1 × × × × × × × 1 × 1
0 0 1 × 0 × × × × × × 0 × 0
0 0 1 × 1 × × × × × × 1 × 1
0 1 0 × × 0 × × × × × 0 × 0
0 1 0 × × 1 × × × × × 1 × 1
0 1 1 × × × 0 × × × × 0 × 0
0 1 1 × × × 1 × × × × 1 × 1
1 0 0 × × × 0 × × × × 0 0
1 0 0 × × × × 1 × × × × 1 1
1 0 1 × × × × × 0 × × × 0 0
1 0 1 × × × × × 1 × × × 1 1

Computer Organization & A r c h i t e c t u r e Lab (BCS-352) Manual (CS, III SEM) Page 29
 Raj Kumar Goel Institute of Technology, Ghaziabad
Department of Computer Science & Engineering

1 1 0 × × × × × × 0 × × 0 0
1 1 0 × × × × × × 1 × × 1 1
1 1 1 × × × × × × × 0 × 0 0
1 1 1 × × × × × × × 1 × 1 1

Pre-Experiment Questions:
1. Explain the need of multiplexer.
2. Which is the major functioning responsibility of the multiplexing combinational circuit?
3. How many NOT gates are required for the construction of a 4-to-1 multiplexer?

Procedure:
 Collect the components necessary to accomplish this experiment.
 Plug the IC chip into the breadboard.
 Connect the supply voltage and ground lines to the chips. PIN7 = Ground
and PIN14 = +5V.
 Make connections as shown in the respective circuit diagram.
 Connect the inputs of the gate to the input switches of the LED.
 Connect the output of the gate to the output LEDs.
 Once all connections have been done, turn on the power switch of the breadboard
 Operate the switches and fill in the truth table ( Write "1" if LED is ON and "0" if L1
is OFF Apply the various combination of inputs according to the truth table and
observe the condition of Output LEDs.

Result & Conclusion: 3-8 line decoder, 4x1 and 8x1 Mux have been implemented & verified
through truth table.

Post Experiment Questions:

1. In 1-to-4 de-multiplexer, how many select lines are required?

2. Which IC is used for the implementation of 1-to-16 DEMUX?

Computer Organization & A r c h i t e c t u r e Lab (BCS-352) Manual (CS, III SEM) Page 30
 Raj Kumar Goel Institute of Technology, Ghaziabad
Department of Computer Science & Engineering

EXPERIMENT 5

Aim: Verify the excitation table of various FLIP-FLOPS

Equipments & Components Required:

S.No. Equipments Specification Quantity

1 Digital IC Trainer kit - 1
2 Digital Multimeter 1
3. Components Required:
S.No. Components Specification Quantity
7400, 7402,
7404,
1 Digital ICs 1 each
7408, 7432,
7486.
2 Patch cords - 6

Theory:
Flip-flops are synchronous bi-stable devices. The term synchronous means the output changes
state only when the clock input is triggered. That is, changes in the output occur in
synchronization with the clock. A flip-flop circuit has two outputs, one for the normal value
and one for the complement value of the stored bit. Since memory elements in sequential
circuits are usually flip-flops, it is worth summarizing the behavior of various flip-flop types
before proceeding further. All flip -flops can be divided into four basic types: SR, JK, D and
T. They differ in the number of inputs and in the response invoked by different value of input
signals. The four types of flip -flops are defined in the Table below.

Computer Organization & A r c h i t e c t u r e Lab (BCS-352) Manual (CS, III SEM) Page 31
 Raj Kumar Goel Institute of Technology, Ghaziabad
Department of Computer Science & Engineering

Circuit Diagram

Computer Organization & A r c h i t e c t u r e Lab (BCS-352) Manual (CS, III SEM) Page 32
 Raj Kumar Goel Institute of Technology, Ghaziabad
Department of Computer Science & Engineering

Pre-Experiment Questions:
1. Difference between Latch and Flip Flop.
2. Differentiate between combinational and sequential circuits.
3. The truth table for an S-R flip-flop has how many VALID entries?
4. What is a trigger pulse?

Computer Organization & A r c h i t e c t u r e Lab (BCS-352) Manual (CS, III SEM) Page 33
 Raj Kumar Goel Institute of Technology, Ghaziabad
Department of Computer Science & Engineering

Procedure:
 Collect the components necessary to accomplish this experiment.
 Plug the IC chip into the breadboard.
 Connect the supply voltage and ground lines to the chips. PIN7 = Ground
 and PIN14 = +5V.
 Make connections as shown in the respective circuit diagram.
 Connect the inputs of the gate to the input switches of the LED.
 Connect the output of the gate to the output LEDs.
 Once all connections have been done, turn on the power switch of the breadboard
 Operate the switches and fill in the truth table ( Write "1" if LED is ON and "0" if L1
is OFF Apply the various combination of inputs according to the truth table and
observe the condition of Output LEDs.

Result & Conclusion: Verified excitation table of various flip flops.

Post Experiment Questions:

1. How is a JK Flip Flop made to toggle?
2. How many stable states do a Flip Flop has?
3. What is the significance of the J and K terminals on the J-K flip-flop?
4. Determine the output frequency for a frequency division circuit that contains 12 flip-
Flops with an input clock frequency of 20.48 MHz.

Computer Organization & A r c h i t e c t u r e Lab (BCS-352) Manual (CS, III SEM) Page 34
 Raj Kumar Goel Institute of Technology, Ghaziabad
Department of Computer Science & Engineering

EXPERIMENT 6

Aim: Design and implement 8-bit Input/Output System with four 8-bit internal registers

Equipment’s & Components Required:

S.No. Equipments Specification Quantity

1 Logic Simulator - 1

S.No. COMPONENT SPECIFICATION QTY.

1. D FLIP FLOP IC 7474 2
2. OR GATE IC 7432 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 15

Theory:
A register is capable of shifting its binary information in one or both directions is known as
shift register. The logical configuration of shift register consist of a D-Flip flop cascaded with
output of one flip flop connected to input of next flip flop. All flip flops receive common
clock pulses which causes the shift in the output of the flip-flop. The simplest possible shift
register is one that uses only flip flop. The output of a given flip flop is connected to the input
of next flip flop of the register. Each clock pulse shifts the content of register one bit position
to right.

Computer Organization & A r c h i t e c t u r e Lab (BCS-352) Manual (CS, III SEM) Page 35
 Raj Kumar Goel Institute of Technology, Ghaziabad
Department of Computer Science & Engineering

LOGIC DIAGRAM:
8-bit Input/Output System with four 8-bit internal register

Pre-Experiment Questions:
1. What are the functions of a bus?
2. State the features of multiplexers.
3. What is the difference between register and counter?
4. Explain serial shifting method.

Procedure:
 Connections are given as per circuit diagram.
 Logical inputs are given as per circuit diagram.
 Observe the output and verify the truth table.
Result & Conclusion: Verified 8-bit Input/Output System with four 8-bit internal registers
on simulator.

Post-Experiment Questions:
1. What are the advantages of using bus interface?

Computer Organization & A r c h i t e c t u r e Lab (BCS-352) Manual (CS, III SEM) Page 36
 Raj Kumar Goel Institute of Technology, Ghaziabad
Department of Computer Science & Engineering

2. Define an Internal register?

3. How many types of registers are there?
4. What is a binary register?

Computer Organization & A r c h i t e c t u r e Lab (BCS-352) Manual (CS, III SEM) Page 37
 Raj Kumar Goel Institute of Technology, Ghaziabad
Department of Computer Science & Engineering

EXPERIMENT 7

Aim: Design of an 8- bit ARITHMETIC LOGIC UNIT.

Equipment’s & Components Required :

S.No. Equipments Specification Quantity

1 Logic Simulator - 1

Theory:
ALU or Arithmetic Logical Unit is a digital circuit to do arithmetic operations like addition,
subtraction, division, multiplication and logical operations like AND, OR, XOR, NAND,
NOR etc. A simple block diagram of a 4 bit ALU for operations AND, OR, XOR and ADD is
shown in the Logic diagram.

LOGIC DIAGRAM:
Block diagram of a 4 bit ALU

Computer Organization & A r c h i t e c t u r e Lab (BCS-352) Manual (CS, III SEM) Page 38
 Raj Kumar Goel Institute of Technology, Ghaziabad
Department of Computer Science & Engineering

Design Issues :
The circuit functionality of a 1 bit ALU is shown here, depending upon the control signal S1
and S0 the circuit operates as follows:
for Control signal S1 = 0 , S0 = 0, the output is A And B,
for Control signal S1 = 0 , S0 = 1, the output is A Or B,
for Control signal S1 = 1 , S0 = 0, the output is A Xor B,
for Control signal S1 = 1 , S0 = 1, the output is A Add B.
The truth table for 16-bit ALU with capabilities similar to 74181 is shown here:
Required functionality of ALU (inputs and outputs are active high)
Mode Select Fn for active HIGH operands
Inputs Logic Arithmetic (note 2)
S3 S2 S1 S0 (M = H) (M = L) (Cn=L)
L L L L A' A
L L L H A'+B' A+B
L L H L A'B A+B'
L L H H Logic 0 minus 1
L H L L (AB)' A plus AB'
L H L H B' (A + B) plus AB'
L H H L A⊕B A minus B minus 1
L H H H AB' AB minus 1
H L L L A'+B A plus AB
H L L H (A ⊕ B)' A plus B
H L H L B (A + B') plus AB
H L H H AB AB minus 1
H H L L Logic 1 A plus A (Note 1)
H H L H A+B' (A + B) plus A
H H H L A+B (A + B') plus A
H H H H A A minus 1

The L denotes the logic low and H denotes logic high.

Pre-Experiment Questions:
1. What are the functions of a an ALU?
2. How does an ALU work?
3. Describe the components of ALU.
4. What are the basic operations of I/O unit?

Computer Organization & A r c h i t e c t u r e Lab (BCS-352) Manual (CS, III SEM) Page 39
 Raj Kumar Goel Institute of Technology, Ghaziabad
Department of Computer Science & Engineering

Procedure:
 Connections are given as per circuit diagram.
 Logical inputs are given as per circuit diagram.
 Observe the output and verify the truth table.

Result & Conclusion: Verified the design of an 8 bit ALU.

Post-Experiment Questions:
1) What are the functions of a CPU?
2) What are the components of CPU and how are they interconnected?
3) What are the basic operations of memory unit?
4) How many ALU’s a computer can have?

Computer Organization & A r c h i t e c t u r e Lab (BCS-352) Manual (CS, III SEM) Page 40
 Raj Kumar Goel Institute of Technology, Ghaziabad
Department of Computer Science & Engineering

EXPERIMENT 8

Aim: Design the data path of a computer from its register transfer language description

Theory:

The internal registers of a microprocessor characterize its architecture. For example, a 32‐bit
Microprocessor has (mostly) 32‐bit registers internally. Moving data among these registers is
the single most frequent operation that takes place in a computer. In this session, we will
construct a 4x4 "register file" comprising registers R0, R1, R2 and R3 (as shown in the figure of
Step 4) to demonstrate the concept of register transfer logic. We will also implement a simple
arithmetic and logic unit (ALU) and then combine the ALU and the register file to construct a
simple computer data path. Moving data from one register to another may be more accurately
described as a "copy" operation. The destination register takes on the value of the source
register which itself remains unchanged after the operation. The source and destination registers
may be the same register.
These register transfers are designated using register transfer notation. For example, copying the
contents of a register Rs into another register Rd would be written as:
Rd ← Rs
where Rs is the source register (and remains unchanged) and Rd is the destination register. A
register file comprises a decoder which chooses a destination register and a multiplexer to direct
the outputs of any register through to the data output lines. The decoder select lines may then be
viewed as the destination "address" and the multiplexer select lines as the source "address".

Procedure:

Step 1 Decoder
The register file requires a 2‐line to 4‐line decoder with HI‐true outputs and one HI‐true enable
input as shown in the circuit of Step 4. This is similar to the decoder you designed in a previous
lab.

Step 2 Quad 4:1 MUX

The register file also requires a Quad 4:1 multiplexer. A Quad 4:1 MUX has four 4‐bit data
inputs, a 4‐bit data output and two select lines as shown below. Study the VHDL source code
given at the end of this lab that implements a Quad 4:1 multiplexer. Be sure you understand the
logic of the VHDL code. Compile this program, implement and test using the MAX7000 device.
Generate a symbol for this MUX which you will use later.

Computer Organization & Architecture Lab (BCS-352) Manual (CS, III SEM) Page 41
 Raj Kumar Goel Institute of Technology, Ghaziabad
Department of Computer Science & Engineering

Step 3 Registers
The four registers R0, R1, R2 and R3 in the diagram below are to be implemented using the
VHDL code at the end of this lab (similar to Figure 7.46, p. 429 of the textbook). Each
registers Comprises 4 positive edge‐triggered D flip flops. Each register has a 4‐bit input
data and A 4‐bit Output data. The clock input to all flip flops in the register is defined as Clk.
Compile thiscode and make a symbol for the register

Step 4 Register File

Now we will design the register file using the graphic design editor by connecting the
multiplexer, decoder and four registers as shown below. Compile and test the register file
circuit in the MAX7000 chip to ensure that all four registers can be loaded using toggle
switches on the Data In lines, and read using LEDs connected at the Data Out lines. Be sure
that you understand the timing of the "load enable" input relative to all the other inputs and
outputs.Make a symbol for this circuit for use later.
Show this working circuit to a Lab Demonstrator before proceeding.

Destination register selection

Load Enable

Source register
selection

Computer Organization & Architecture Lab (BCS-352) Manual (CS, III SEM) Page 42
 Raj Kumar Goel Institute of Technology, Ghaziabad

Department of Computer Science & Engineering

Step 5 Data path

The register file forms the basis of a "data path" which is a fundamental building block of
acomputer. See the diagram below. Data is selected from any register then stored back into
any other register in the register file, all in a single clock cycle ( a lo‐ hi‐ lo pulse applied
to the load enable LE input). A Quad 2:1 MUX included as shown below allows external
data to be inserted into the data path. Data can thus be transferred between any two
registers of our register file or any register can be loaded with external data. This data path
can execute the following
operations:
(a) any register can be loaded with external data from switches Rd ← data (4‐ bits)
(where d=0,1,2 or 3)
(b) any register can be loaded with the data contained in any one of the other registers,
including itself (register‐ to‐ register transfer) Rd ← Rs (where d, s = 0, 1, 2 or 3)

The implementation is shown below. The inputs [ D1, D0, S1, S0, DS ] form a 5‐ bit
"control" word which specifies the source (S1, S0) and destination (D1, D0) registers of
the register file and an operation (DS) that is to take place. For DS=0, external data from
switches is loaded into the destination register; for DS=1, data is transferred from the
source register to the destination register. Once the control word and data input (if
appropriate) are set on the level switches, execution is achieved by applying a load enable
(LE) input to the register file. This LE input may be considered as the clock to the entire
system. You can view the results of each operation using four LEDs connected to the
output of the register file as shown.
Design this data path using the graphic design editor. VHDL code for the Quad 2:1 MUX
design is given at the end of this lab. Test the circuit for various combinations of the
register transfers summarized in the following table.

Computer Organization & Architecture Lab (BCS-352) Manual (CS, III SEM) Page 43
 Raj Kumar Goel Institute of Technology, Ghaziabad

Department of Computer Science & Engineering

Summary of register transfer operation

Data Register
Source Source Destination Register data input Transfer
DS Register D1 D0 Operation
S1 S0
0 X X 0 0 abcd R0 abcd
0 X X 0 1 abcd R1  abcd
0 X X 1 0 abcd R2  abcd
0 X X 1 1 abcd R3  abcd
1 0 0 0 0 XXXX R0  R0
1 0 0 0 1 XXXX R1  R0
1 0 0 1 0 XXXX R2  R0
1 0 0 1 1 XXXX R3  R0
1 0 1 0 0 XXXX R0  R1
1 0 1 0 1 XXXX R1  R1
1 0 1 1 0 XXXX R2  R1
1 0 1 1 1 XXXX R3  R1
1 1 0 0 0 XXXX R0  R2
1 1 0 0 1 XXXX R1  R2
1 1 0 1 0 XXXX R2  R2
1 1 0 1 1 XXXX R3  R2
1 1 1 0 0 XXXX R0  R3
1 1 1 0 1 XXXX R1  R3
1 1 1 1 0 XXXX R2  R3
1 1 1 1 1 XXXX R3  R3

Computer Organization & Architecture Lab (BCS-352) Manual (CS, III SEM) Page 44
 Raj Kumar Goel Institute of Technology, Ghaziabad

Department of Computer Science & Engineering

Step 6 ALU
An ALU is a combinational logic circuit that performs various arithmetic and logic
operations on n-bit data (operands). A simple 8-function ALU that operates on 4-bit inputs
A and B is specified in the following table. The block symbol for an ALU is also given
below. The number of bits on the "function select" input determines how many operations
may be performed on the operands (in this example there are 23 = 8 functions). Its
definition in VHDL code is given at the end of this lab (see Figure 6.48, p.360 of the
textbook).

Step 7 Modify the Register File

To be able to include an ALU in our data path, we must first modify our register file design

so that it has the capability to select two registers as outputs (Source Register A and Source
Register B).This will allow the contents of any two registers to be applied to the A and B
inputs of the ALU.This is easily achieved by adding a second Quad 4:1 MUX to the design
of

Computer Organization & Architecture Lab (BCS-352) Manual (CS, III SEM) Page 45
 Raj Kumar Goel Institute of Technology, Ghaziabad

Department of Computer Science & Engineering

Step8 Data path with ALU

Now, the data path design can be extended by including the ALU from Step 6 and the
register file from Step 7 as shown in the next figure
Using the graphic design editor, build this circuit using the previous components and compile,
implement and test.
This data path has much more capability than our first design in St ep 5: as before, any register can
be loaded with external data from switches:
Rd  data (4 bits) (where d = 0, 1,2 or 3) any register can be loaded with the result of
any of the eight functions supported by our ALU whose input is the data contained in anytwo
ofthe registers. For example:

Rd  RA + RB (where d, A, B = 0, 1, 2 or3)

Would allow us to load any register with the sum of any two registers.

The inputs [ D1, D0, SA1, SA0, SB1, SB0, s2, s1, s0, DS ] comprise a 10‐bit control word
which specifies a destination register (D1, D0) , the two source registers (SA1, SA0) and
(SB1, SB0), and the ALU function (s2, s1, s0) that operates on the source registers. The
DS input allows loading of the registers with external data via the Quad 2:1 MUX. For
DS=0, external data from switches is loaded into the destination register; for DS=1, data is
transferred from the ALU output to the destination register. As in Step 5, once the
control word and data input (inappropriate) are set on the level switches, execution is achieved
by applying a load enable (LE) input (pulse lo‐hi‐lo) to the register file. This LE input may
be considered as the clock to the entire system. You can view the results of each operation
using four LEDs connected to the output of the ALU as shown. The function that is
executed in response to a control word and a LE clock input is called a microoperation. A
series of microoperation applied to a data path is called a Microprogram. Try the following
examples of micro operations in your implementation:

Computer Organization & Architecture Lab (BCS-352) Manual (CS, III SEM) Page 46
 Raj Kumar Goel Institute of Technology, Ghaziabad
Department of Computer Science & Engineering

Destination Source Source ALU Data data

Register Register Register function select Sourc inpu Operation
D1 D0 A SA1 B SB1 s2 s1 s0 e DS t
SA0 SB0
0 X X XXX 0 abcd R0 abcd
0 X X
0 X X XXX 0 abcd R1  abcd
1 X X
1 X X XXX 0 abcd R2  abcd
0 X X
1 X X XXX 0 abcd R3  abcd
1 X X
0 0 0 011 1 XXXX R0  R0 + R1
0 0 1
0 0 1 010 1 XXXX R1  R0 ‐ R2
1 0 0
1 X X 000 1 XXXX R2  0
0 X X
1 X X 111 1 XXXX R3  ‐1
1 X X
0 1 1 110 1 XXXX R0  R2 AND
0 0 1 R3
0 0 1 101 1 XXXX R1  R1 OR R2
1 1 0
1 0 1 100 1 XXXX R2  R1 XOR
0 1 1 R3
1 1 1 100 1 XXXX R3  R3 XOR
1 1 1 R3

Result: The above Result: verified all the micro-operations.

Post Experiment Questions:

Q1.What microoperation is implemented with the control

word: 10010111?
Q2.What is the effect of the last microoperation in this table?

Computer Organization & Architecture Lab (BCS-352) Manual (CS, III SEM) Page 47
 Raj Kumar Goel Institute of Technology, Ghaziabad

Department of Computer Science & Engineering

EXPERIMENT 9

Aim: Implement a simple instruction set computer with a control unit and a data path.

Equipments and components required: Processor simulator

Theory
In Figure the typical organization of a modern von Neumann processor is illustrated. Note that
the CPU, memory subsystem, and I/O subsystem are connected by address, data, and control
buses. The fact that these are parallel buses is denoted by the slash through each line that
signifies a bus.

Schematic diagram of a modern von Neumann processor, where the CPU is denoted by a
shaded box
It is worthwhile to further discuss the following components in Figure:
 Processor (CPU) is the active part of the computer, which does all the work of data
manipulation and decision making.
 Data path is the hardware that performs all the required operations, for example,
ALU,registers, and internal buses.
 Control is the hardware that tells the data path what to do, in terms of switching,
operation selection, data movement between ALU components, etc.
The processor represented by the shaded block in Figure is organized as shown in Figure
below. Observe that the ALU performs I/O on data stored in the register file, while the Control
Unit sends (receives) control signals (resp. data) in conjunction with the register file.

Computer Organization & Architecture Lab (BCS-352) Manual (CS, III SEM) Page 48
 Raj Kumar Goel Institute of Technology, Ghaziabad

Department of Computer Science & Engineering

Schematic diagram of the processor in Figure 4.1, adapted from [Maf01].

In MIPS, the ISA determines many aspects of the processor implementation. For example,
implementation strategies and goals affect clock rate and CPI. These implementation constraints
cause parameters of the components in Figure to be modified throughout the design process.

Schematic diagram of MIPS architecture from an implementation perspective, adapted from

[Maf01].

Such implementation concerns are reflected in the use of logic elements and clocking strategies.
For example, with combinational elements such as adders, multiplexers, or shifters, outputs
depend only on current inputs. However, sequential elements such as memory and registers
contain state information, and their output thus depends on their inputs (data values and clock) as
well as on the stored state. The clock determines the order of events within a gate, and defines
when signals can be converted to data to be read or written to processor components (e.g.,
registers or memory). For purposes of review, the following diagram of clocking is presented:

Computer Organization & Architecture Lab (BCS-352) Manual (CS, III SEM) Page 49
 Raj Kumar Goel Institute of Technology, Ghaziabad

Department of Computer Science & Engineering

Here, a signal that is held at logic high value is said to be asserted. In Section 1, we discussed
how edge-triggered clocking can support a precise state transition on the active clock pulse
edge (either the rising or falling edge, depending on what the designer selects). We also
reviewed the SR Latch based on nor logic, and showed how this could be converted to a
clocked SR latch. From this, a clocked D Latch and the D flip-flop were derived. In particular,
the D flip-flop has a falling-edge trigger, and its output is initially disserted (i.e., the logic low
value is present).

4.1.2. Register File

The register file (RF) is a hardware device that has two read ports and one write port
(corresponding to the two inputs and one output of the ALU). The RF and the ALU together
comprise the two elements required to compute MIPS R-format ALU instructions. The RF is
comprised of a set of registers that can be read or written by supplying a register number to be
accessed, as well (in the case of write operations) as a write authorization bit. A block diagram
of the RF is shown in Figure 4.4a.

Computer Organization & Architecture Lab (BCS-352) Manual (CS, III SEM) Page 50
 Raj Kumar Goel Institute of Technology, Ghaziabad

Department of Computer Science & Engineering

(a)

(b)

Computer Organization & Architecture Lab (BCS-352) Manual (CS, III SEM) Page 51
 Raj Kumar Goel Institute of Technology, Ghaziabad

Department of Computer Science & Engineering

(c)

Register file (a) block diagram, (b) implementation of two read ports, and (c)
implementation of write port - adapted from [Maf01].
Since reading of a register-stored value does not change the state of the register, no "safety
mechanism" is needed to prevent inadvertent overwriting of stored data, and we need only
supply the register number to obtain the data stored in that register. (This data is available at
the Read Data output in Figure 4.4a.) However, when writing to a register, we need (1) a
register number, (2) an authorization bit, for safety (because the previous contents of the
register selected for writing are overwritten by the write operation), and (3) a clock pulse
that controls writing of data into the register.

Data path Design and Implementation

The data path is the "brawn" of a processor, since it implements the fetch-decode-execute
cycle. The general discipline for data path design is to (1) determine the instruction classes
and formats in the ISA, (2) design data path components and interconnections for each
instruction class or format, and (3) compose the data path segments designed in Step 2) to
yield a composite data path.
Simple data path components include memory (stores the current instruction), PC or
program counter (stores the address of current instruction), and ALU (executes current
instruction). The interconnection of these simple components to form a basic data path is
illustrated in

Computer Organization & Architecture Lab (BCS-352) Manual (CS, III SEM) Page 52
 Raj Kumar Goel Institute of Technology, Ghaziabad
Department of Computer Science & Engineering
Figure 4.5. Note that the register file is written to by the output of the ALU. As in Section
4.1, the register file shown in Figure 4.6 is clocked by the RegWrite signal.

Schematic high-level diagram of MIPS data path from an implementation perspective

Implementation of the data path for I- and J-format instructions requires two more components –

Schematic diagram of Data Memory and Sign Extender

a data memory and a sign extender, illustrated in Figure . The data memory stores ALU results and
operands, including instructions, and has two enabling inputs (MemWrite and MemRead) that
cannot both be active (have a logical high value) at the same time. The data memory accepts an
address and either accepts data (WriteData port if MemWrite is enabled) or outputs data (ReadData
port if MemRead is enabled), at the indicated address. The sign extender adds 16 leading digits to a
16-bit word with most significant bit b, to product a 32-bit word. In particular, the additional 16

Computer Organization & Architecture Lab (BCS-352) Manual (CS, III SEM) Page 53
 Raj Kumar Goel Institute of Technology, Ghaziabad
Department of Computer Science & Engineering
digits have the same value as b, thus implementing sign extension in twos complement
representation.

R-format Data path

Implementation of the data path for R-format instructions is fairly straightforward - the register file
and the ALU are all that is required. The ALU accepts its input from the DataRead ports of the
register file, and the register file is written to by the ALUresult output of the ALU, in combination
with the RegWrite signal.

Schematic diagram R-format instruction data path, adapted from [Maf01].

Load/Store Data path

The load/store data path uses instructions such as lw $t1, offset($t2), where offset denotes a
memory address offset applied to the base address in register $t2. The lw instruction reads
from memory and writes into register $t1. The sw instruction reads from register $t1 and writes
into memory. In order to compute the memory address, the MIPS ISA specification says that
we have to sign-extend the 16-bit offset to a 32-bit signed value. This is done using the sign
extender shown in Figure 4.6.

The load/store data path is illustrated in Figure 4.8, and performs the following actions in the
order given:
 Register Access takes input from the register file, to implement the instruction, data, or
address fetch step of the fetch-decode-execute cycle.
 Memory Address Calculation decodes the base address and offset, combining them to
produce the actual memory address. This step uses the sign extender and ALU.
 Read/Write from Memory takes data or instructions from the data memory, and
implements the first part of the execute step of the fetch/decode/execute cycle.

 Write into Register File puts data or instructions into the data memory, implementing
the second part of the execute step of the fetch/decode/execute cycle.
Computer Organization & Architecture Lab (BCS-352) Manual (CS, III SEM) Page 54
 Raj Kumar Goel Institute of Technology, Ghaziabad
Department of Computer Science & Engineering

Figure 4.8. Schematic diagram of the Load/Store instruction data path. Note that
the execute step also includes writing of data back to the register file, which is not shown in the
figure, for simplicity [MK98].

The load/store data path takes operand #1 (the base address) from the register file, and sign-
extends the offset, which is obtained from the instruction input to the register file. The sign-
extended offset and the base address are combined by the ALU to yield the memory address,
which is input to the Address port of the data memory. The MemRead signal is then activated,
and the output data obtained from the ReadData port of the data memory is then written back to
the Register File using its WriteData port, with RegWrite asserted.

Branch/Jump Data path

The branch data path (jump is an unconditional branch) uses instructions such as beq $t1,
$t2, offset, where offset is a 16-bit offset for computing the branch target address via PC relative
addressing. The beq instruction reads from registers $t1 and $t2, then compares the data obtained
from these registers to see if they are equal. If equal, the branch is taken. Otherwise, the branch is
not taken. By taking the branch, the ISA specification means that the ALU adds a sign-extended
offset to the program counter (PC). The offset is shifted left 2 bits to allow for word alignment
(since 22 = 4, and words are comprised of 4 bytes). Thus, to jump to the target address, the lower
26 bits of the PC are replaced with the lower 26 bits of the instruction shifted left 2 bits.
The branch instruction data path is illustrated in Figure 4.9, and performs the following
actionsin the order given:
1. Register Access takes input from the register file, to implement the instruction
fetch or data fetch step of the fetch-decode-execute cycle.
2. Calculate Branch Target - Concurrent with ALU #1's evaluation of the branch condition,
ALU #2 calculates the branch target address, to be ready for the branch if it is taken.
This completes the decode step of the fetch-decode-execute cycle.

Computer Organization & Architecture Lab (BCS-352) Manual (CS, III SEM) Page 55
 Raj Kumar Goel Institute of Technology, Ghaziabad
Department of Computer Science & Engineering

Schematic diagram of the Branch instruction data path.

Note that, unlike the Load/Store data path, the execute step does not include writing of results
back to the register file. The branch data path takes operand #1 (the offset) from the
instruction input to the register file, then sign-extends the offset. The sign-extended offset
and the program counter (incremented by 4 bytes to reference the next instruction after the
branch instruction) are combined by ALU #1 to yield the branch target address. The operands
for the branch condition to evaluate are concurrently obtained from the register file via the
ReadData ports, and are input to ALU #2, which outputs a one or zero value to the branch
control logic. MIPS has the special feature of a delayed branch, that is, instruction Ib which
follows the branch is always fetched, decoded, and prepared for execution. If the branch
condition is false, a normal branch occurs. If the branch condition is true, then Ib is executed.
One wonders why this extra work is performed - the answer is that delayed branch improves
the efficiency of pipeline execution, as we shall see in Section 5. Also, the use of branch-not-
taken (where Ib is executed) is sometimes the common case.

Single-Cycle and Multicycle Data paths

A single-cycle data path executes in one cycle all instructions that the data path is designed to
implement. This clearly impacts CPI in a beneficial way, namely, CPI = 1 cycle for all
instructions. In this section, we first examine the design discipline for implementing such a
data path using the hardware components and instruction-specific data paths developed in
Section 4.2. Then, we discover how the performance of a single-cycle data path can be
improved using a multi-cycle implementation.

Single Data paths

Let us begin by constructing a data path with control structures taken from the results of
Section 4.2. The simplest way to connect the data path components developed in Section 4.2
is to have them all execute an instruction concurrently, in one cycle. As a result, no data path
component can be used more than once per cycle, which implies duplication of components.
To make this type of design more efficient without sacrificing speed, we can share a data path
component by allowing the component to have multiple inputs and outputs selected by a
multiplexer.

Computer Organization & Architecture Lab (BCS-352) Manual (CS, III SEM) Page 56
 Raj Kumar Goel Institute of Technology, Ghaziabad
Department of Computer Science & Engineering
The key to efficient single-cycle data path design is to find commonalities among instruction
types. For example, the R-format MIPS instruction data path of Figure 4.7 and the load/store
data path of Figure 4.8 have similar register file and ALU connections. However, the
following differences can also be observed:
1. The second ALU input is a register (R-format instruction) or a signed-extended lower
16 bits of the instruction (e.g., a load/store offset).
2. The value written to the register file is obtained from the ALU (R-format instruction)
or memory (load/store instruction).

These two data path designs can be combined to include separate instruction and data
memory, as shown in Figure 4.10. The combination requires an adder and an ALU to
respectively increment the PC and execute the R-format instruction.

Computer Organization & Architecture Lab (BCS-352) Manual (CS, III SEM) Page 57
 Raj Kumar Goel Institute of Technology, Ghaziabad
Department of Computer Science & Engineering

Figure 4.10. Schematic diagram of a composite data path for R-format and load/store instructions
[MK98].
Adding the branch data path to the data path illustrated in Figure 4.9 produces the augmented data
path shown in Figure 4.11. The branch instruction uses the main ALU to compare its operands and
the adder computes the branch target address. Another multiplexer is required to select either the
next instruction address (PC + 4) or the branch target address to be the new value for the PC.

Computer Organization & Architecture Lab (BCS-352) Manual (CS, III SEM) Page 58
 Raj Kumar Goel Institute of Technology, Ghaziabad
Department of Computer Science & Engineering

Schematic diagram of a composite data path for R-format, load/store, and branch instructions
ALU Control. Given the simple data path shown in Figure we next add the control unit.
Control accepts inputs (called control signals) and generates (a) a write signal for each state
element, (b) the control signals for each multiplexer, and (c) the ALU control signal. The
ALU has three control signals, as shown in Table , below.
Table ALU control codes
ALU Control Input Function

000 and
001 or
010 add
110 sub
111 slt
The ALU is used for all instruction classes, and always performs one of the five functions in
the right-hand column of Table . For branch instructions, the ALU performs a subtraction,
whereas R-format instructions require one of the ALU functions. The ALU is controlled by
two inputs: (1) the opcode from a MIPS instruction (six most significant bits), and (2) a two-
bit control field (which Patterson and Hennesey call ALUop). The ALUop signal denotes
whether the operation should be one of the following:
ALUop Input Operation

00 load/store
01 beq
10 determined by opcode

Computer Organization & Architecture Lab (BCS-352) Manual (CS, III SEM) Page 59
 Raj Kumar Goel Institute of Technology, Ghaziabad
Department of Computer Science & Engineering
The output of the ALU control is one of the 3-bit control codes shown in the left-hand
column of Table 4.1. In Table 4.2, we show how to set the ALU output based on the
instruction opcode and the ALUop signals. Later, we will develop a circuit for generating
the ALUop bits. We call this approach multi-level decoding -- main control generates ALU
opbits, which are input to ALU control. The ALU control then generates the three-bit codes
shown in Table.
Table ALU control bits as a function of ALUop bits and opcode bits [MK98].

In this table, an "X" in the input column represents a "don't-care" value, which indicates that
the output does not depend on the input at the i-th bit position. The preceding truth table can
be optimized and implemented in terms of gates, as shown in Section C.2 of Appendix C of
the textbook.
4.3.1.2. Main Control Unit. The first step in designing the main control unit is to identify
the fields of each instruction and the required control lines to implement the data path shown
in Figure

Recalling the three MIPS instruction formats (R, I, and J), shown as follows:

Computer Organization & Architecture Lab (BCS-352) Manual (CS, III SEM) Page 60
 Raj Kumar Goel Institute of Technology, Ghaziabad
Department of Computer Science & Engineering

Observe that the following always apply:

 Bits 31-26: opcode - always at this location
 Bits 25-21 and 20-16: input register indices - always at this location
Additionally, we have the following instruction-specific codes due to the regularity of the MIPS
instruction format:

 Bits 25-21: base register for load/store instruction - always at this location
 Bits 15-0: 16-bit offset for branch instruction - always at this location
 Bits 15-11: destination register for R-format instruction - always at this location
 Bits 20-16: destination register for load/store instruction - always at this location
Note that the different positions for the two destination registers imply a selector (i.e., a mux)to
locate the appropriate field for each type of instruction. Given these constraints, we can add to
the simple data path thus far developed instruction labels and an extra multiplexer for the
WriteReg input of the register file, as shown in Figure 4.12.

Computer Organization & Architecture Lab (BCS-352) Manual (CS, III SEM) Page 61
 Raj Kumar Goel Institute of Technology, Ghaziabad

Department of Computer Science & Engineering

Schematic diagram of composite data path for R-format, load/store, and branch instructions
Here, we see the seven-bit control lines (six-bit opcode with one-bit WriteReg signal) together with
the two-bit ALUop control signal, whose actions when asserted or deserted are given as follows:

 RegDst
Deserted: Register destination number for the Write register is taken from bits 20-16 (rt
field) of the instruction

Asserted: Register destination number for the Write register is taken from bits 15-11 (rd
field) of the instruction

 RegWrite
Deserted: No action

Asserted: Register on the WriteRegister input is written with the value on the WriteData
input

 ALUSrc
Deasserted: The second ALU operand is taken from the second register file output (ReadData
2)
Asserted: the second alu operand is the sign-extended, lower 16 bits of the instruction

 PCSrc
Deasserted: PC is overwritten by the output of the adder (PC + 4)

Asserted: PC overwritten by the branch target addres

Computer Organization & Architecture Lab (BCS-352) Manual (CS, III SEM) Page 62
 Raj Kumar Goel Institute of Technology, Ghaziabad
Department of Computer Science & Engineering
 MemRead
Deasserted: No action
Asserted: Data memory contents designated by address input are present at the ReadData
output

 MemWrite
Deasserted: No action
Asserted: Data memory contents designated by address input are present at the WriteData
input

 RegWrite
Deasserted: The value present at the WriteData input is output from the ALU
Asserted: The value present at the register WriteData input is taken from data memory
Given only the opcode, the control unit can thus set all the control signals except PCSrc, which is
only set if the instruction is beq and the Zero output of the ALu used for comparison is true.
PCSrc is generated by and-ing a Branch signal from the control unit with the Zero signal from
the ALU. Thus, all control signals can be set based on the opcode bits. The resultant data path
andits signals are shown in detail in Figure 4.13.

Schematic diagram of composite data path for R-format, load/store, and branch instructions
withcontrol signals illustrated in detail

Computer Organization & Architecture Lab (BCS-352) Manual (CS, III SEM) Page 63
 Raj Kumar Goel Institute of Technology, Ghaziabad

Department of Computer Science & Engineering

We next examine functionality of the data path illustrated in 4.13, for the three major types of
instructions, then discuss how to augment the data path for a new type of instruction.

Data path Operation

Recall that there are three MIPS instruction formats -- R, I, and J. Each instruction causes
slightly different functionality to occur along the data path, as follows.

R-format Instruction
Execution of an R-format instruction (e.g., add $t1, $t0, $t1) using the data path developed in
Section 4.3.1 involves the following steps:
1. Fetch instruction from instruction memory and increment PC
2. Input registers (e.g., $t0 and $t1) are read from the register file
3. ALU operates on data from register file using the funct field of the MIPS instruction (Bits
5-0) to help select the ALU operation
4. Result from ALU written into register file using bits 15-11 of instruction to select the
destination register (e.g., $t1).

Note that this implementation sequence is actually combinational, because of the single-cycle
assumption. Since the data path operates within one clock cycle, the signals stabilize
approximately in the order shown in Steps 1-4, above.
Load/Store Instruction. Execution of a load/store instruction (e.g., lw $t1, offset($t2))
using the data path developed in Section 4.3.1 involves the following steps:

1. Fetch instruction from instruction memory and increment PC

2. Read register value (e.g., base address in $t2) from the register file
3. ALU adds the base address from register $t2 to the sign-extended lower 16 bits of the
instruction (i.e., offset)

4. Result from ALU is applied as an address to the data memory

5. Data retrieved from the memory unit is written into the register file, where the register
index is given by $t1 (Bits 20-16 of the instruction).

Computer Organization & Architecture Lab (BCS-352) Manual (CS, III SEM) Page 64
 Raj Kumar Goel Institute of Technology, Ghaziabad
Department of Computer Science & Engineering
Branch Instruction. Execution of a branch instruction (e.g., beq $t1, $t2, offset) using
the data path developed in Section 4.3.1 involves the following steps:
1. Fetch instruction from instruction memory and increment PC
2. Read registers (e.g., $t1 and $t2) from the register file. The adder sums PC + 4 plus sign-
extended lower 16 bits of offset shifted left by two bits, thereby producing the branch
target address (BTA).

Final Control Design. Now that we have determined the actions that the data path must
perform to compute the three types of MIPS instructions, we can use the information in Table 4.3
to describe the control logic in terms of a truth table. This truth table (Table 4.3) is to yield the
data path control circuitry.
Table ALU control bits as a function of ALUop bits and opcode bits

Extended Control for New Instructions

The jump instruction provides a useful example of how to extend the single-cycle data path
developed in Section, to support new instructions. Jump resembles branch (a conditional form of
the jump instruction), but computes the PC differently and is unconditional. Identical to the branch
target address, the lowest two bits of the jump target address (JTA) are always zero, to preserve
word alignment. The next 26 bits are taken from a 26-bit immediate field in the jump instruction
(the remaining six bits are reserved for the opcode). The upper four bits of the JTA are taken from
the upper four bits of the next instruction (PC + 4). Thus, the JTA computed by the jump
instruction is formatted as follows:

 Bits 31-28: Upper four bits of (PC + 4)

 Bits 27-02: Immediate field of jump instruction
 Bits 01-00: Zero (002)

Computer Organization & Architecture Lab (BCS-352) Manual (CS, III SEM) Page 65
 Raj Kumar Goel Institute of Technology, Ghaziabad
Department of Computer Science & Engineering

The jump is implemented in hardware by adding a control circuit to Figure 4.13, which is comprised
of:

 An additional multiplexer, to select the source for the new PC value. To cover all cases, this
source is PC+4, the conditional BTA, or the JTA.
 An additional control signal for the new multiplexer, asserted only for a jump instruction
(opcode = 2).
The resulting augmented data path is shown in Figure 4.14.

Schematic diagram of composite data path for R-format, load/store, branch, and jump instructions,
with control signals labeled
.

Computer Organization & Architecture Lab (BCS-352) Manual (CS, III SEM) Page 66
 Raj Kumar Goel Institute of Technology, Ghaziabad
Department of Computer Science & Engineering

Microinstruction Format
A microinstruction is an abstraction of low-level control that is used to program control logic
hardware. The microinstruction format should be simple, and should discourage or prohibit
inconsistency. (An inconsistent microinstruction requires a given control signal to be set to two
different values simultaneously, which is physically impossible.)

The implementation of each microinstruction should, therefore, make each field specify a set of
no overlapping values. Signals that are never asserted concurrently can thus share the same
field. Table 4.5 illustrates how this is realized in MIPS, using seven fields. The first six fields
control the data path, while the last field controls the microinstruction sequencing (deciding
which microinstruction will be executed next).
Table MIPS microinstruction format
Field Name Field Function

Specify the operation performed by the ALU during this clock

ALU control
cycle, the result written to ALUout.

SRC1 Source for the first ALU operand

SRC2 Source for the second ALU operand

Register Specify read or write for Register File, as well as the source of a
control value to be written to the register file if write is enabled.

Specify read or write, and the source for a write. For a read, specify
Memory
the destination register.

PCWrite
Specify how the PC is to be written (e.g., PC+4, BTA, or JTA)
control

Sequencing Specify how to choose the next microinstruction for execution

In hardware, microinstructions are usually stored in a ROM or PLA (per descriptions in

Appendices B and C of the textbook). The microinstructions are usually referenced by
sequential addresses to simplify sequencing. Branching, to the microinstruction that initiates
execution of the next MIPS instruction. This is implemented by the value Fetch in
the Sequencing field.

Computer Organization & Architecture Lab (BCS-352) Manual (CS, III SEM) Page 67
 Raj Kumar Goel Institute of Technology, Ghaziabad
Department of Computer Science & Engineering

Microprogramming the Data path Control

In this section, we use the fetch-decode-execute sequence that we developed for the multicycle
data path to design the microprogrammed control. First, we observe that sometimes an
instructionmight have a blank field. This is permitted when:

 A field that controls a functional unit (e.g., ALU, register file, memory) or causes state
information to be written (e.g., ALU dest field), when blank, implies that no control
signals should be asserted.

 A field that only specifies control of an input multiplexer for a functional unit, when left
blank, implies that the data path does not care about what value the output of the mux
has.
We can now create the Microprogram in stepwise fashion.

Instruction Fetch and Decode, Data Fetch. Each instruction execution first fetches
the instruction, decodes it, and computes both the sequential PC and branch target PC (if
applicable).The two microinstructions are given by:

Label ALU control SRC1 SRC2 Register control Memory PCWrite

Sequencing
----- ------------- ------ -------- ------------------- -------- --------- ------------
Fetch Add PC 4 --- Read PC ALU Seq
--- Add PC Extshft Read --- --- Dispatch 1
where "---" denotes a blank field. In the first microinstruction,
 ALU control, SRC1, and SRC2 are set to compute PC+4, which is written to ALUout. The
memory field reads the instruction at address equal to PC, and stores the instruction in the IR.
The PCWrite control causes the ALU output (PC + 4) to be written into the PC, while the
Sequencing field tells control to go to the next microinstruction.
 The label field (value = fetch) will be used to transfer control in the next Sequencing field
when execution of the next instruction begins.
In the second microinstruction, we have the following actions:
 ALU control, SRC1, and SRC2 are set to store the PC plus the sign-extended, shifted
IR[15:0] into ALUout. Register control causes data referenced by the rs and rt fields to be placed

Computer Organization & Architecture Lab (BCS-352) Manual (CS, III SEM) Page 68
 Raj Kumar Goel Institute of Technology, Ghaziabad
Department of Computer Science & Engineering

in ALU input registers A and B. output (PC + 4) to be written into the PC, while the Sequencing
field tells control to go to dispatch table 1 for the next microinstruction address.

Dispatch Tables. Patterson and Hennessey consider the dispatch table as a case statement that
uses the opcode field and dispatch table i to select one of Ni different labels. For in Dispatch Table
#1 (i = 1, Ni = 4) we have label Mem1 for memory reference instructions, Rformat1 for arithmetic
and logical instructions, Beq1 for conditional branches, and Jump1 for unconditional branches. Each
of these labels points to a different microinstruction sequence that can be thought of as a kind of
subprogram. Each microcode sequence can be thought of as comprising a small utility that
implements the desired capability of specifying hardware control signals.
Memory Reference Instructions. Three microinstructions suffice to implement memory access
in terms of a MIPS load instruction: (1) memory address computation, (2) memory read, and
(3) register file write, as follows:

Label ALU control SRC1 SRC2 Register control Memory PCWrite Sequencing
----- ------------- ------ -------- ------------------- -------- --------- ------------
Mem1 Add A Extend ---------------------------------- Dispatch 2
LW2 --- --- --- --- Read ALU --- Seq
--- --- --- --- Write MDR --- --- Fetch
The details of each microinstruction are given on pp. 405-406 of the textbook.
R-format Execution. R-format instruction execution requires two microinstructions: (1) ALU
operation, labelled Rformat1 for dispatching; and (2) write to register file, as follows:

Label ALU control SRC1 SRC2 Register control Memory PCWrite Sequencing
----- ------------- ------ -------- ------------------- -------- --------- ------------
Rformat1 Func code A B --- --- --- Seq
--- --- --- --- Write ALU --- --- Fetch
The details of each microinstruction are given on p. 406 of the textbook.
Branch and Jump Execution. Since we assume that the preceding microinstruction
computed the BTA, the Microprogram for a conditional branch requires only the following
microinstruction:

Label ALU control SRC1 SRC2 Register control Memory PCWrite Sequencing
----- ------------- ------ -------- ------------------- -------- --------- ------------
Beq1 Subt A B --- --- ALUout-cond Fetch

Computer Organization & Architecture Lab (BCS-352) Manual (CS, III SEM) Page 69
 Raj Kumar Goel Institute of Technology, Ghaziabad
Department of Computer Science & Engineering

Similarly, only one microinstruction is required to implement a Jump instruction:

Label ALU control SRC1 SRC2 Register control Memory PCWrite Sequencing
----- ------------- ------ -------- ------------------- -------- --------- ------------
Jump1 --- --- --- --- --- Jump address Fetch

Implementational details are given on p. 407 of the textbook.

The composite microprogram is therefore given by the following ten instructions:

Label ALU control SRC1 SRC2 Register control Memory PCWrite Sequencing
----- ------------- ------ -------- ------------------- -------- --------- ------------
Fetch Add PC 4 --- Read PC ALU Seq
--- Add PC Extshft Read ---------------------- Dispatch 1
Mem1 Add A Extend----------------------------------Dispatch 2
LW2 --- --- --- --- Read ALU --- Seq
--- --- --- --- Write MDR --- --- Fetch
SW2 --- --- --- --- Write ALU --- Fetch
Rformat1 Func code A B --- --- --- Seq
--- --- --- --- Write ALU --- --- Fetch
Beq1 Subt A B --- --- ALUout-cond Fetch
Jump1 --- --- --- --- --- Jump address Fetch
Here, we have added the SW2 microinstruction to illustrate the final step of the store instruction.
Observe that these ten instructions correspond directly to the ten states of the finite-state control
developed in Section 4.4. In more complex machines, Microprogram control can comprise tens or
Hundreds of thousands of microinstructions, with special-purpose registers used to store
intermediate data.

Result: implementation is verified

Post Experiment Question:

Q1. What is micro instruction format?

Q2. What is FSM?

Computer Organization & Architecture Lab (BCS-352) Manual (CS, III SEM) Page 70
R Raj Kumar Goel Institute of Technology, Ghaziabad

Department of Computer Science & Engineering

EXPERIMENT 10

Aim: Design and implementation of HALF SUBTRACTOR, FULL SUBTRACTOR

using basic logic gates

Equipment & Components Required:

S.No. Equipments Specification Quantity

1 Digital IC Trainer kit - 1
2 Digital Multimeter 1

S.No. Components Specification Quantity

7400, 7402,
7404,
1 each
1 Digital ICs 7408, 7432,
7486.
- 6
2 Patch cords

Theory:

a) To design and implement half Subtractor using logic gates

HALF SUBTRACTOR

OUTPUTS
INPUT X INPUT Y
D B

0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

CIRCUIT DIAGRAM

Computer Organization & Architecture Lab (BCS-352) Manual (CS, III SEM) Page 71
R Raj Kumar Goel Institute of Technology, Ghaziabad

Department of Computer Science & Engineering

b) To design and implement full subtractor using logic gates

INPUTS OUTPUTS
A B BIN D BOUT
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

CIRCUIT DIAGRAM TRUTH TABLE

.
Pre-Experiment Questions:
1. Explain the truth table of half subtractor.
2. How many Ex-or and or or gate can be used to make a half subtractor?
3. Why XOR gate is called an inverter?
4. How many outputs are required for the implementation of a subtractor?

Procedure:
 Identify the pins.
 Connect the circuit as per circuit diagram.
 Obtain outputs with various input combinations.
 Verify it with the Boolean function using truth table

Result & Conclusion: All logical circuits have been implemented & verified through truth
table.

Computer Organization & Architecture Lab (BCS-352) Manual (CS, III SEM) Page 72
R Raj Kumar Goel Institute of Technology, Ghaziabad

Department of Computer Science & Engineering

Post-Experiment Question:
1. What are the applications of half subtractor?
2. What are the applications of full subtractor?
3. What does minuend and subtrahend denotes in a subtractor?
4. How can a full subtractor be implemented?

Computer Organization & Architecture Lab (BCS-352) Manual (CS, III SEM) Page 73
R Raj Kumar Goel Institute of Technology, Ghaziabad

Department of Computer Science & Engineering

APPENDIX

AKTU SYLLABUS

KCS 352: COMPUTER ORGANIZATION LAB

1. Implementing HALF ADDER, FULL ADDER using basic logic gates

2. Implementing Binary -to -Gray, Gray -to -Binary code conversions.

3. Implementing 3-8 line DECODER.

4. Implementing 4x1 and 8x1 MULTIPLEXERS.

5. Verify the excitation tables of various FLIP-FLOPS.

6. Design of an 8-bit Input/ Output system with four 8-bit Internal Registers.

7. Design of an 8-bit ARITHMETIC LOGIC UNIT

8. Design the data path of a computer from its register transfer language description.

9. Design the control unit of a computer using either hardwiring or microprogramming based
on its register transfer language description.

10. Implement a simple instruction set computer with a control unit and a data path.

Computer Organization & Architecture Lab (BCS-352) Manual (CS, III SEM) Page 74