Sequential Circuits: Latches and Flip-Flop

6.1.1 Introduction to Sequential Circuits

In digital electronics, a combinational circuit is one of the essential types of circuits which is made up
of basic gates. In the combinational circuit, the output at any instant of time depends only on the
inputs at that time. Such circuits are called circuits with no memory because the output does not
depend on the previous state of the circuit.
One more very important logical circuit is known as a sequential circuit, in which the present output
depends not only on the present inputs but also on the previous output. When the output is
generated, that output is stored in a storage unit known as a memory element. This stored output is
fed back to the combinational circuit along with other inputs. The storage element, that is, memory, is
capable of storing binary information in the form of 0 and 1.
There are two types of storage elements: latches and flip-flops. Both these storage elements are
bi-stable devices. Bi means two. So, they have two stable states and can store either logic 0 or 1.
Hence, these two storage elements are also known as 1-bit storage elements. The major difference
between a latch and a flip-flop is how they are triggered. The latch or flip-flop’s state can be changed
via a momentary change in its input signal, and this momentary change is called a trigger. This
trigger is provided by means of a clock pulse. When a trigger pulse is applied to the input, the output
changes, and the storage device is said to be triggered. There are two ways of triggering: level
triggering and edge triggering.
There are two types of level triggering:
1. High-level sensitive triggering
2. Low-level sensitive triggering
There are two ways to edge triggering:
1. Positive edge triggering
2. Negative edge triggering
Latches are level sensitive, that is, the output changes only during the high voltage period or low
voltage period. On the other hand, flip-flops are edge-triggered. In positive edge triggering, the
output changes at the positive edge of the clock, whereas in negative edge triggering, the output
changes at the negative edge of the clock.
Sequential circuits are used in many applications. It is used in the implementation of registers.
Registers are used in microprocessors and microcontrollers to store temporary data. It is used in the
implementation of memory. Memory elements are typically implemented using flip-flops. Sequential
circuits are also used in the implementation of analog-to-digital and digital-to-analog converters,
counters, etc.
6.1.2 Storage Elements: RS Latch
The latch is a basic storage element that is capable of storing 0 or 1 by either setting or resetting. RS
latch is also known as the reset-set latch. This latch has two inputs, R and S, and two outputs, Q and
Q′. R is reset, S is set. Reset means storing 0 into the latch and set means storing 1 into the latch.
This latch can be implemented either using NOR gates or NAND gates. In NOR gate implementation
of the RS latch, it uses two 2-input NOR gates, G1 and G2. NOR gate truth table is shown in Figure
1.
Figure 1: NOR gate implementation
R input is connected to one of the inputs of G1, and the other input to G1 comes from the Q′ output.
Similarly, the S input is connected to one of the inputs of G2, and the other input comes from the Q
output.
To demonstrate the functioning of the RS latch, consider the following four cases.
Case 1: R = 1 and S = 0
When one or both inputs of NOR gate is 1, the output will be 0. Hence, the output Q will be at 0. This
Q output is fed as an input to G2. Since both the inputs to G2 are 0, the output will equal 1. Hence,
for R = 1, and S = 0, Q = 0 and Q′ = 1. Latch is said to be reset to 0.
Case II: R = 0 and S = 1
Since one of the inputs to G2 is 1, the output will equal 0. Hence, Q′ = 0. Now G1 has both its inputs
0, so the output will be equal to 1. So, for R = 0, and S = 1, Q is equal to 1, and Q′ is equal to 0.
Hence, the latch is set to 1.
Case III: R = 0 and S = 0
Assume Q = 0. Since Q = 0, Q′ will be equal to 1. Since the second input of G1 is 1, output Q = 0,
and since both the inputs of G2 are zero, the output Q′ will be 1. Hence, the output is the same as its
previous state. For the same third case, let us assume Q is equal to 1 and Q′ is equal to 0. Since
both the inputs of G1 are 0, output Q is 1, and since one of the inputs of G2 is one, the output Q′ will
be 0.
Case IV: R = 1 and S = 1
Both the NOR gate have one of their inputs at logic 1. So, both the NOR gates yield logic 0, that is,
Q equals 0 and Q′ equals 0. Having both Q and Q′ at the same level is not correct. Hence, setting R
= 1 and S = 1 is forbidden. The NOR gate RS latch truth table is shown in Figure 2.

Figure 2: Truth table for NOR gate RS Latch implementation.

When R = 0 and S = 0, the latch is said to be in the previous state. This state of latch is known as
the memory state. When R = 0 and S = 1, latch is set to 1. When R = 1 and S = 0, latch is reset to 0.
When R = 1 and S = 1, latch will be in a forbidden state or invalid state where both Q and Q’ will be
holding the same state.
Figure 3 shows the NAND gate implementation of the RS latch and the corresponding truth table.
Figure 3: NAND gate RS Latch implementation
When R = 0 and S = 0, latch will be in an invalid state. When R = 0 and S = 1, the latch is set to 0.
When R = 1 and S = 0, the latch is reset to 1. When R = 1 and S = 1, the latch is said to be in the
previous state.
6.1.3 Storage Elements: RS Flip-Flops
The RS flip-flop is one of the most basic sequential logic circuits. The RS stands for SET RESET.
Similar to RS latch, the RS flip-flop is a one-bit memory and is a bi-stable device. Flip-flop word
means that it can be “FLIPPED” into one logic state or “FLOPPED” back into another. RS flip flop
has three inputs. The first input is called “RESET,” which will reset the flip-flop to 0 and is labeled as
R. The second input is known as “SET,” which will set the flip-flop to 1 and is labeled as S. The third
input is a clock. Clocking causes the flip-flop either to change or to retain its output signal based on
the values of the input signals at the transition. The main difference between RS Latch and the RS
flip-flop is how the device is triggered. RS latch is level triggered, whereas RS flip-flop is edge
triggered. It can be triggered at the positive edge of the clock or at the negative edge of the clock.
Figure 4 shows the clocked RS flip-flop, which consists of a basic NOR RS latch and two AND
gates.
Figure 4: Clocked RS flip-flop
R and S inputs are applied to one of the inputs of these two AND gates, and another input of these
gates is connected to the clock. The outputs of the two AND gates remain at 0 if the clock pulse is
zero, irrespective of R and S input values.
When the clock input is 1, the input R and S values are applied to the basic RS latch. The flip-flop is
set to 1 when R = 0, S = 1, and clock = 1. The flip-flop is reset to 0 when R = 1, S = 0, and Clock = 1.
When R = 0, S = 0, and Clock = 1, the flip-flop is said to be in the previous state. In this state, the
outputs of the flip-flop, Q and Q′ will be at the previous logic level. When S = 1, R = 1, and Clock = 1,
the flip-flop is indeterminate, or the flip-flop is said to be in the forbidden or invalid state. The truth
table of the RS flip-flop is shown in Figure 5.

Figure 5: Clocked RS flip-flop

6.1.4 Storage Element: JK Flip-Flops
The R-S flip-flop has the disadvantage of meta-stability; that is, if both inputs go high, the resulting
state is unpredictable. To overcome this problem, a JK flip-flop is used. JK flip-flop is the most widely
used of all the flip-flop designs and is a universal flip-flop circuit. This flip-flop was developed by Jack
Kilby. The role of inputs J and K are the same as that of R and S inputs. Logic 1 on J input sets the
flip-flop, and logic 1 on K input resets or clears the flip-flop. A clocked J K flip-flop is as shown in
Figure 6. This flip-flop uses a basic SR flip-flop and additional AND gates. Q′ output is ANDed with J
and clock inputs. To set a flip-flop, inputs J, Q′ should be 1, along with an active clock pulse.
Similarly, Q input is ANDed with K and Clock inputs so that the flip-flop is cleared during a clock
pulse only if Q was previously 1. The structure and truth tables are given in Figures 6 and 7,
respectively.

Figure 6: Structure of JK flip-flop

Figure 7: Truth table of JK flip-flop

J and K are the two data inputs to the JK flip-flop. Outputs Qn and Qn′ represent the present output.
S and R are the two inputs to the RS flip-flop. Qn+1 represents the next output. Let us assume that
the clock is high when inputs to the flip-flop are to be applied.
Consider four cases of inputs J and K.
Case I: J = 0 and k = 0.
There are two possibilities for present outputs Qn and Qn′. Irrespective of these two possible values
for present outputs, since both J and K are zero, the output of both the AND gates will be 0. So, S
and R will be zero. Therefore, Qn+1 will be in the previous state. That is, when Qn is equal to 0, Qn+1
will be zero, and when Qn is 1, Qn+1 will be 1; hence, when J = 0, K = 0, the flip-flop will be in the
previous state.
Case II: J = 0 and K = 1
Assume Qn is 0 and Qn′ is 1. Since J is 0, the output of AND gate G1 is zero. Similarly, since Qn is 0,
AND gate G2 output is zero. Therefore, S and R are applied with 0, which makes the flip-flop remain
in the previous state. Since the previous state of the flip-flop is 0, the next state Qn+1 is 0.
Now assume Qn is 1 and Qn′ is 0. Since Qn′ is 0, the output of AND gate G1 is zero. So, S will be 0.
Since all the inputs to G2 are 1, the output will be 1. Hence, R will be equal to 1. For S = 0 and R =
1, the output of the flip-flop will be reset to 0. So. Qn+1 is equal to 0. Therefore, for J = 0 and K = 1,
the flip-flop is said to be cleared or reset.
Case III: J = 1 and K = 0
Assuming Qn equals 0 and Qn′ equals 1, S and R become 1 and 0, respectively. This, in turn, sets
the flip-flop to 1, which is 1. Assuming Qn equals 1 and Qn′ equals 0, S and R become 0. When both
S and R inputs are 0, a flip-flop will be in the previous state. In this case, the previous state of the
flip-flop is 1. Hence, Qn+1 is set to 1.
Case IV: J = 1 and K = 1
Assuming Qn equals 0 and Qn′ equals 1, S and R become 1 and 0, respectively. This, in turn, sets
the flip-flop to 1, that is, Qn+1 is 1. Assuming Qn equals 1 and Qn′ equals 0, S and R become 0 and
1, respectively.
When S = 0 and R = 1, the flip-flop will be reset to 0. As you can see, when J = 1, K =1 flip-flop
changes its state from 1 to 0 and 0 to 1. And the flip-flop is said to be in a toggle state.
6.1.5 Demerits of JK Flip-Flops
The invalid state of the RS flip-flop is eliminated by the JK flip-flop by using a feedback connection
from output to input. In the JK flip-flop, when J = 1 and K = 1, the flip-flop is said to be in a toggle
state. J K flip-flop also possesses a problem. This problem is known as a race-around condition.
Consider the last row of the truth table given in Figure 7, where both J and K are equal to one. The
output Qn+1 of the flip-flop depends on the status of previous outputs Qn and Qn′. Qn+1 will be 1
when Qn is 0, and Qn+1 will be 0 when Qn is 1. Let both J and K be equal to 1, and Qn is zero, and
clock pulse. Let tp be the pulse width from the leading edge of the clock to the falling edge. ∆t be the
propagation time of a flip-flop. Propagation delay, in general, is defined as the length of time starting
from when the input to a device is applied to the time that the output of the device is available. Since
the previous output Qn is zero, the present output toggles to 1. At the end of ∆t, flip-flop finds the
clock is high, the previous output is 1, and toggles to 0. This toggling back and forth between 0 and 1
continues during the entire clock period tp. At the end of the clock pulse, the value of Qn+1 is
uncertain. This condition is referred to as the “race-around condition.” The solution to solve the
problem is to keep tp less than ∆t. This solution is difficult to implement practically because ICs
usually have very small propagation delays. A more feasible solution is to use a modified version of
the JK flip-flop known as a master-slave flip-flop.
6.1.6 Storage Element: JK Master-Slave Flip-Flops
JK master-slave flip-flop is made up of two JK flip-flops. The first flip-flop is known as a master
flip-flop which is positive edge triggered, whereas the second one is known as a slave which is
negative edge triggered. These two flip-flops are called master and slave because the master
responds to its J and K inputs before the slave flip-flop. Figure 8 shows the master-slave JK flip-flop.
Figure 8: Truth table of master-slave JK flip-flop
Figure 9 is the truth table of the master-slave JK flip-flop.

Figure 9: Truth table of Master-Slave JK flip-flop.

When both the inputs of the master are zero, the flip-flop is disabled, and the output of the master
and slave remains unchanged. The flip-flop will be said to be in the previous state. If J = 0 and K = I,
the master resets on the positive edge of the clock. That is, Q output of the master will be 0. During
the negative edge of the clock, the slave resets to 0. The slave copies the master again. The flip-flop
is said to be in the reset state. If J = 1 and K = 0, the output of the master is set to 1 on the positive
clock transition. The high Q output of the master drives the J input of the slave, so on the negative
clock transition, the slave is set to 1. So, the slave copies the action of the master. When both J and
k inputs of the master are high, the output toggles on the positive edge of the clock, and the slave
sets or resets on the negative edge of the clock based on the master’s output. When the master
toggles during the positive edge of the clock and at the end of the clock, let us assume its output is
0. Now for the slave, J input of 0, and K input is 1, which makes the flip-flop reset on the negative
edge of the clock. If the master output is 1 after toggling, the slave output will be set. So, slave will
have stable output. This is how race condition is eliminated in JK master-slave flip-flop.
6.1.7 Storage Element: D Flip-Flops
The main drawback of RS flip is the “invalid state”; that is, the output becomes forbidden when S and
R inputs are set to 1. Similarly, in the case of the JK flip-flop, setting J = 1 and K = 1 leads to a race
condition. The main purpose of these two flip-flops is to set or reset the flip-flop. In the case of the
RS flip-flop, when S = 1 and R = 0, the flip-flop will be set to 1, and when S = 0 and R = 1, the
flip-flop will be reset to 0. For these two cases, S is the complement of R. Similarly, in the case of the
JK flip-flop, when J = 1 and K = 0, the flip-flop will be set to 1, and when J = 0 and K = 1, the flip-flop
will be reset to 0. Similar to the RS flip-flop, here also, J is the complement of K. Therefore, instead
of having two inputs, the flip-flop can have only one input, and the other input can be generated by
complementing it.
D flip-flop is a combinational electronic circuit that has only two inputs, D and clock. The D input is
also known as data input. It is a clocked flip-flop. D flip-flop implementation using RS and JK flip-flop
is shown in Figure 10.

Figure 10: D flip-flop block diagram

In the case of D flip-flop implementation using Rs flip-flop, the D input is connected to the S input
and its complement to R input. Similarly, in the case of implementation using J K flip-flop, the D input
is connected to J input and complement of D to K input. When the clock input is low, the output
retains the original value stored in the flip-flop. When the D flip-flop is clocked, output Q follows the
input D. The state of its output signal Q is delayed until the next rising edge of a clock occurs.
Hence, this flip-flop is also known as a delay flip-flop. A truth table for the two implementations is
shown in Figure 11.

Figure 11: D flip-flop block diagram

The D flip-flop symbol is shown in Figure 12.
Figure 12: D flip-flop symbol
The main applications include the implementation of time delay circuits and counters. They are also
used in shift registers for data transfer applications.
6.1.8 Storage Elements: T Flip-Flops
In JK flip-flop, when both J and K are equal to 1 flip-flop, it will be in a toggle state. That is, output
changes from 0 to 1 and 1 to 0. In counter applications, J and K inputs are always at logic 1. This
can be achieved by modifying the J K flip-flop. In T flip-flop, “T” denotes “Toggle.” This flip-flop works
as a toggle switch. That is, the next state of the flip-flop will be the complement of the present state.
T Flip-flop has two inputs, “T” and clock. Two outputs, Q and Q′. For constructing a T flip-flop from
JK flip, we need to tie inputs J and K together. Due to this T flip-flop is also known as single input JK
flip-flop. There are two variants of T flip-flops based on the triggering applied at the clock input. In a
positive edge-triggered flip-flop, output toggles at the positive edge of the clock pulse. In a negative
edge-triggered flip-flop, output changes at the negative edge of the clock pulse. Figure 13 shows the
logic circuit and truth table of the T flip-flop.
Figure 13: T flip-flop and its truth table
T can have a value of either 0 or 1. When T = 0, the flip-flop will be in the previous state. When T =
1, output toggles from 0 to 1 and 1 to 0. One of the popular applications of T flip-flops is in the
implementation of frequency divider circuits.

Figure 14: Frequency divider circuit

Figure 14 shows the frequency divider circuit, which uses two JK flip-flops. The inputs of both the
flip-flops are supplied with logic High input. Both the flip-flops are negative edge triggered. So, the
output changes during the negative edge of the clock. The clock input to the second JK flop–flop
comes from the Q output of the first flip-flop. The output Q0 changes its output at the negative edge
of the input clock pulse. Whereas the output of the second flip-flop changes its output at the negative
edge of the Q0 output. So, if clock frequency is f, then output Q0’s frequency is 0.5f and Q1’s
frequency is 0.25f.
Registers
6.2.1 Introduction to Registers
Flip-flop is a sequential circuit that can store 1 bit of digital information. This flip-flop is considered as
an essential element of a sequential logic system. Any sequential circuit can be designed using
flip-flops and combinational circuits. The register contains an array of flip-flops that can store a word
of information. The number of flip-flops in a register depends on the number of bits in a word.
Registers find their application in various digital systems, including microprocessors and
microcontrollers. For example, the LC3 processor has a set of registers used to store temporary data
required during the processing of an instruction. These sets of registers are known as register set or
register file. Data can be entered into the register in serial form or in parallel form. In serial form, the
data is entered one bit at a time, whereas in parallel form, all bits of the data are entered
simultaneously. Data in serial form is also referred to as a temporal code, and in parallel form is
called spatial code. For example, consider binary data D3 D2 D1 D0 equal to 0 1 0 1, where D3 is
MSB and D0 is LSB. This data in serial form and parallel form is shown in Figure 15.

Figure 15: Data in serial and parallel forms

One data line is required for serial data transfer, whereas for parallel data transfer, multiple lines are
required. Based on how data is entered and retrieved, registers are classified into four categories.
1. Serial in, Serial Out (SISO)
2. Serial in, Parallel Out (SIPO)
3. Parallel in, Serial Out (PISO)
4. Parallel in, Parallel Out (PIPO)
The register in which data are entered and taken out in serial or parallel form is known as a shift
register. It is possible to design a register whose contents can be shifted toward the right or left.
Such registers are called right-shift registers and left-shift registers. In a bi-directional shift register,
data can be shifted from left to right as well as in reverse direction. A register that can implement all
four types of register that is SISO, SIPO, PISO, and PIPO, is known as a universal register.
6.2.2 Types of Registers
Shift registers are one of the most commonly used registers in which data is entered and taken out
in a serial or parallel form.

Figure 16: Block diagram of 5-bit shift register

Figure 16 shows the 5-bit register implemented using five master slave JK flip-flops. In such a
register, flip-flops are cascaded where the output of one flip-flop is connected to the input of the next.
Figure 17: Waveform of the 5-bit shift register
To shift a 0 into the flip-flop, J is set to 0, and K is set to 1. To shift a 1 into the flip-flop, J is set to
one, and K is set to zero. Initially, flip-flops are set to 0 by using Clear input. All the flip-flops are tied
to a common clock, and flip-flops are activated at the negative edge of the clock pulse. Clock pulses
are numbered T1, T2, T3, etc. Data to be shifted is loaded into the serial input line. The process of
entering the data input starts with the data input corresponding to the least significant bit. Since
initially, all the flip-flops are cleared, the outputs of Q0 to Q4 will be zero during T1. At the falling
edge of the T1 clock pulse, the output of flip-flop 4 will be 0 since the data input is 0, and the outputs
of all other flip-flops are 0 since their inputs are 0. At the falling edge of T2, input corresponding to
the next bit one is applied, the flip-flop outputs will be Q4 equals 1, Q3, Q2, Q1, and Q0 equals 0. At
the falling edge of T3, the next input 1 is applied. The flip-flop outputs will be Q4, Q3 equals 1, Q2,
Q1, Q0 equals 0. At the falling edge of T4, the next input zero is applied. The flip-flop outputs will be
Q4 equals 0, Q3, Q2 equals 1, Q1, Q0 equals 0. At the falling edge of T5, the next input 1 is applied.
The flip-flop outputs will be Q4 equals 1, Q3 equals 0, Q2, Q1 equals 1, and Q0 equals 0. At the end
of the fifth clock pulse, the outputs of flip-flops are Q4 equals 1, Q3 equals 0, Q2 equals 1, Q1
equals 1, and Q0 equals 0, which is the same as the number which was entered. Observe that the
number of clock pulses required for entering the data is the same as the number of data bits. Data is
entered into the register serially. Data can also be entered in parallel by using a parallel input line
and preset enable.
Note: The process of entering the data is referred to as writing into the register. The process of
retrieving the data is referred to as reading.
6.2.3 Applications of Registers
In general, registers are used for storing temporary data during the execution of instructions in a
processor. A register may hold an instruction, the address of a storage unit, or any kind of data, such
as a bit sequence or characters. Figure 18 shows the block diagram of a general-purpose processor.

Figure 18: Block diagram of a processor

All processors have a register known as a program counter, also known as an instruction pointer. A
program counter is used to store the address of the instruction that is to be executed next. The
Instruction register is used to store the instruction fetched from memory. MDR (memory data register
and MAR (memory address register) act as a buffer between the memory and the processor. MDR
holds the data, whereas MAR holds the address. Apart from these registers, there are registers that
will aid during arithmetic and logical operations and address computation. These sets of registers
are known as register files.
Figure 19: LC-3 Processor architecture
In the LC-3 computer of Figure 19, there is a register file containing several registers. Another
application of the register is storing the status of the processor. The status information stored in the
register is known as the processor status word (PSW). The purpose of using register storage is to
improve the execution speed of a program since accessing the register is faster than the main
memory.
While switching from one function to another, it is required to store the context of the calling function.
Processors are usually connected to external devices either for data acquisition or data transfer. In
such cases, it is essential to know the status of the device connected. For example, how does a
computer know the ink cartridge is empty, or printer is not on, or there is no paper? This information
is captured as a status in a register. Bits in the status register are examined for further action.
Another application of the register is to introduce a time delay in digital signals. A Serial Input, Serial
Output register, may be used to introduce a delay. In data communication, parallel data transmission
is used for shorter distances, providing greater speed. The best example is communication between
the computer and a printer. On the other hand, serial data communication is suitable for transmitting
data over longer distances. Computers generate parallel data that needs to be converted to serial
data before it is transmitted. Similarly, at the receiving end, received serial data needs to be
converted back to parallel data. For this purpose, parallel to serial converter and serial to parallel
converter is needed. Parallel data can be converted to serial form using parallel in serial out shift
register. In contrast, serial data can be converted to parallel data using serial in, parallel out shift
register.
A special type of sequential circuit used to count the pulse is known as a counter. They are used to
count specific events happening in the circuit. These counters are implemented using registers.
Registers are also used to generate a prescribed sequence of bits. Such sequence generators find
their application in counters, random bit generators, and code generators.
Memory
6.3.1 Concept of Memory: Address Space and Addressability
A flip-flop is one-bit memory capable of storing logical 1 and 0. The memory unit stores information
that usually consists of program instructions which are coded in binary form, data to be processed
and intermediate and final results. The basic element of memory is a flip-flop. Memories are usually
made up of a large number of locations where data word is stored. Each location is identified by a
unique identifier known as a memory address. The number of bits of information stored in each
location is known as addressability. The total number of uniquely identifiable locations is known as
address space. For example, 2 KB memory. K stands for a kilo. K stands for 1024.
Most memories are byte-addressable, where each location is capable of storing 8 bits of information.
The modern computer, which is to perform large scientific calculations, has higher addressability. For
example, 64-bit addressable memory.

Figure 20: Block diagram of 8 × 2-bit memory

The simple memory organization of 8 × 2-bit memory is shown in Figure 20. The address space of
this memory is 8, which means there are eight memory locations in the memory. These memory
locations are uniquely addressed. The starting address of the memory is 0, and the last memory
location is 7. The binary equivalent of these addresses is, as shown. Addressability is 2 bits; that is,
in each memory location, 2-bit information can be stored. There is a relationship between the
number of memory locations and a number of bits needed to represent an address.
2N=M
2
N
=M
where N is the number of address bits, and M is the total number of memory locations.
6.3.2 Types of Memory: Random-Access, Sequential-Access, Volatile, and Non-Volatile
Memory is an integral part of a computer that is required to store data, programs, and results. The
memory of a computer is categorized into two types: primary memory and secondary memory.
Primary memory is the computer’s main memory, where programs and data are stored temporarily.
Program and data stored in this main memory are directly accessed by the CPU during program
execution. On the other hand, secondary memory is used to store large volumes of data
permanently on a secondary storage device. The secondary storage memory is permanent memory.
Depending on the type of material used, there are two most common types of memory
semiconductor memory and magnetic memory. Semiconductor memory is a faster, lightweight,
compact, but expensive memory, whereas magnetic memory is slower and cheaper.
Information stored in memory can be accessed either sequentially or randomly. In sequential access
memory, information is read or written sequentially. Access time is the amount of time it takes to read
or write information. In the case of random-access memory, access time is independent of where
information is stored.
Semiconductor memories are categorized into two types: RAM—random access memory and
ROM—read only memory. Originally RAM was known as read-write memory. RAM is volatile
memory, that is, contents will be erased in case of no power. Therefore, it is used as temporary
storage. RAM is usually packaged as a chip and may require two more chips to make a memory of
the required size. For example, there is a RAM chip called SN74LS207, which is 1024 × 1-bit
memory. To make it 1024 × 8 bits, we need eight such chips. RAM comes in two categories: dynamic
RAM, in short, known as D-RAM, and static RAM, in short, known as SRAM.
Figure 21: DRAM structure
Figure 21 shows the structure of D-RAM. It has a very simple construction. Each memory cell
consists of a transistor and a capacitor. Here, the data is stored in the form of a charge on a
capacitor. A charge cannot be held for a longer time. Charges tend to leak. Hence, there is a need
for a refreshing circuit even when the circuit is powered. This is an extra overhead. DRAMS are
smaller in size and less expensive but slower. DRAMS are extensively used in the implementation of
main memory and frame buffers.
Figure 22: SRAM structure
The structure of SRAM is shown in Figure 22. Since there are no capacitors involved, no charges to
leak. Hence, no refreshing circuit is needed. The structure of SRAM is complex compared to DRAM.
Hence, it requires a larger space per bit. Also, it is more expensive than DRAM. Since it is faster
compared to DRAM, it is used in the implementation of cache memory. Cache memory is a
high-speed memory that acts as a bridge between the main memory and the CPU. There is a
comparison table that compares SRAM and DRAM with reference to transistor per bit, access time,
the requirement of refreshing circuit, cost, and applications.
Read only memory is also random-access memory. This permanent and non-volatile memory has a
few variants. In ROM, memory contents are written during production, and there is no option for the
user to program it. Note that the process of programming a ROM is sometimes called burning the
ROM. Programmable ROM, PROM is a second variant where the user can program data only once.
The difference between a PROM and a ROM is that a PROM is manufactured as blank memory,
whereas a ROM is programmed during the manufacturing process. To write data onto a PROM chip,
a special device called a PROM programmer or PROM burner is needed. The third variant is
erasable PROM, EPROM. It is a special type of PROM that can be erased by exposing it to
ultraviolet light or X-ray. Once it is erased, it can be reprogrammed. The fourth variant is electrically
erasable PROM, EEPROM. This has an electronic erase capability. The last variant in the list is flash
memory. It is similar to that of EEPROM. The main difference between EEPROM and flash memory
is that in the case of EEPROM, the entire memory is erased before being written, whereas in the
case of flash memory, it may be erased, written, and read in blocks or bytes.
Some of the applications are as follows:
● Storing fonts for a printer
● Storing sound data in musical instruments
● Video game consoles
● Implantable medical devices
● High-definition multimedia interfaces (HDMI)
● BIOS chip in the computer
● Program storage chips in modems, video cards, and many electronic gadgets, controllers for
disks, network cards, etc.

Secondary storage is a memory that is stored external to the computer. It is mainly used for the
permanent and long-term storage of programs and data. Secondary memories are classified into two
types. Disk drives and tape drives. Examples include floppy disks, hard disks, SD cards, pen/flash
drives, SSD, and others; optical memories include CDs, DVDs, and others. Hard disk stores and
retrieves data using magnetic storage. Uses multiple magnetic disks coated with magnetizable
material such as iron oxide. Redundant arrays of independent disks (RAID) is another type of
memory that consists of multiple disks. This technology is used to increase the performance of data
storage through parallel I/O access. It provides reliable data storage. And this reliability is achieved
through redundancy. SSD or solid-state disks are an alternative to magnetic disks. It is a faster
memory compared to magnetic memories. Most people prefer SSD not just because it is a faster
memory but it is also a green device. SSD is a green device because SSD has no moving parts and
hence its energy consumption is much lower compared to the magnetic disk. SD card is a tiny flash
memory card. SD cards are typically used in digital cameras and other portable devices. USB flash
drive is also popularly known as pen drive. It is a plug-and-play portable storage device that uses
flash memory. Optical Devices include Compact disks such as CD, CD read-write, DVD, and so on.
6.3.3 Example of Memory Unit: 4×3-bit Memory
Figure 23: SRAM structure
Memory is capable of storing many 1s and 0s. Figure 23 shows the M by K read-write memory
whose address space is M and addressability is K. The memory is capable of being written into and
read from. Whenever the processor wants to perform reading and writing operations, it sends signals
on read and write lines, respectively. To perform a read or write operation, the processor has to send
an N-bit address on the address lines. The relationship between the number of address bits and the
address space is given by 2N = M. Data to be written into is sent on the K data input lines, and data
to be read from is sent on K data output lines.
Figure 24: 4×2 memory structure
Figure 24 shows the 4×2-bit memory. There are four memory locations; in each location, 2 bits of
information can be stored. Thus, a total of 8 bits of information can be stored in this memory. To
store these 8 bits, for each location, two flip-flops are needed. Two address lines, A1 and A0,
address four memory locations. To provide the addressability of two, there are two data input lines
and two data output lines. Data inputs are fed to the D input of the flip-flop. Data input gets latched
into the flip-flop when the clock signal is enabled. Data inputs are written to which location is decided
by the binary signal on address lines A1 and A0 and write enable WE line. The two address lines are
connected to the 2:4 decoder circuit.
Consider an example that illustrates memory write operation. Assume that the data to be written is 1
0, and the address of the memory location is 0. So, A1, A0 is set to 00, and D1 D0 is set to 10.
To write data into the memory, write enable WE signal is set to 1. This enables the first output of the
decoder, which in turn is connected to the clock inputs of the first two flip-flops, FF01 and FF00. By
enabling the clock inputs, both flip-flops store data available at D1 and D0 inputs. In this case, it is 1,
0. In the case of a memory read operation, data is obtained from the OR gate output lines. This OR
gate is driven by the AND gates. One of the inputs for these AND gates comes from the output of the
flip-flop, and the decoder output drives the other input.