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Digital Circuits
Assignment- Week 7
TYPE OF QUESTION: MCQ
Number of questions: 15 Total mark: 15 X 1 = 15
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QUESTION 1:

Modulus (MOD) value of the 5-bit ring counter is ________.

A) 10

B) 50

C) 5

D) 6

Correct Answer: c

Detailed Solution:

The Modulus of a counter is the number of unique states that the counter will sequence
through. In, ring counter the number of unique states is equal to number of FFs.
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QUESTION 2:
The contents of the following registers (Q4Q3Q2Q1Q0) after two clock transitions are.
(Assume initial values of all flip-flops are logic 1).

A) 1 1 1 1 0

B) 1 1 0 0 1

C) 1 1 0 1 0

D) 1 1 1 0 0

Correct Answer: D

Detailed Solution:

Q4 Q3 Q2 Q1 Q0

Initial state 1 1 1 1 1

Clk 1 1 1 1 0

Clk 1 1 1 0 0

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QUESTION 3:
The minimum number of flip-flops required to design a mod-150 counter?
A) 8
B) 7
C) 6
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D) 15

Correct Answer: A

Detailed Solution:
In a n-bit counter, the total number of states = 2^n.
Therefore, in a 8-bit counter, the total number of states = 2^8 = 256 states. So, to design 150
MOD counter we need at least 8 FFs.

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QUESTION 4:
A MOD-2 and MOD-5 up counter when cascaded together results in a MOD __________
counter . ( In integer)

a) 7

b) 2

c) 10

d) 5

Correct Answer: C

Detailed Solution:

Whenever 2 counters having MOD A and MOD B respectively are connected in cascade,
then the overall counter is formed with MOD (A x B)

MOD (overall counter)

MOD A1 x MOD A2 x MOD A3 …….

The overall configuration is MOD ( 2x 5) = 10

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QUESTION 5:
What is the output (QAQBQCQD) sequence of the following circuit after 5 clock transitions?
(Assume initial output state of the all FFs are logic ‘0’.
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A) 0 0 0 1

B) 1 0 0 0

C) 1 1 1 0

D) 0 1 1 0

Correct Answer: A

Detailed Solution:

clk QA QB QC QD

0 0 0 0

1 0 0 0

0 1 0 0

1 1 1 0

0 0 0 1

0 0 0 1

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QUESTION 6:
Which of the state diagram represents the following circuit?
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A) C)

B) D)

Correct Answer: D

Detailed Solution:

QUESTION 7:
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A finite state machine (FSM) is implemented using the D flip-flops A and B, and logic gates, as
shown in the figure below.

Assume that XIN is held at logic ‘1’ throughout the operation of the FSM. When the FSM
initialized to the state QAQB=00 and clocked, after two clock cycles, what will the output?

A) 00

B) 11

C) 10

D) 01

Correct Answer: B

Detailed Solution:

clk QA QB

NA 0 0

0 1

1 1

QUESTION 8:
The following circuits acts as
____________________.

a) Ring counter
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b) Johnson ring counter

c) Circular shift register

d) Mod-3 counter.

Correct Answer: B

Detailed Solution: Follow lecture materials

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QUESTION 9:
What is the modulus value of 5-bit Johnson counter?
A) 4
B) 6
C) 8
D) 10
Correct Answer: D

Detailed Solution:

The modulus value of Johnson counter is twice the number of FFs

QUESTION 10:
Initially, outputs of all the flip-flops are reset to logic 0. What is the output (AB) after 3 clock
transitions?

a) 00

b) 01

c) 10

d) 11
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Correct Answer: a

Detailed Solution:

clk Present state TA = A+B TB = A’ + B Next state

1 00 0 1 01

2 01 1 1 10

3 10 0 1 00

After 3 clock cycles applied the output AB = 00

QUESTION 11:
Which of the following sequence(Q1Q0) produced by the below circuit?

A) 00,01,10,11,00
B) 00,01,10,00,01
C) 00,01,11,00,01
D) 00,10,11,00,10
Correct Answer: B

Detailed Solution:

clk Q1 Q0
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NA 0 0

0 1

1 0

0 0

QUESTION 12:
The current state of QA QB of a two JK flip-flop system is 00. Identify the sequence produced by
QA QB.

A) 00, 01, 10, 11, 00, 01

B) 00, 11, 10, 01, 00, 11
C) 00, 11, 01, 10, 00, 11
D) 00, 01, 11, 10, 00, 11
Correct Answer: C

Detailed Solution:

clk QA QB
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NA 0 0

1 1

0 1

1 0

0 0

QUESTION 13:
Which of the following is not an application of a shift register circuit?
A) Serial to parallel converter
B) Sequence generator
C) Look ahead carry adder
D) Delay unit
Correct Answer: C

Detailed Solution:

We can design shift register and sequence detector using shift registers.

QUESTION 14:
A counter is constructed with three D flip-flops. The input-output pairs are named (D0, Q0), (D1,
Q1), (D2, Q2), where the subscripts 0 denotes the least significant bit. The output sequence is
desired to be the grey code sequence 000, 001, 011, 010, 110, 111, 101, and 100 repeating
periodically. Note that the bits are listed in the Q2Q1Q0 format. The combinational logic
expression for D1 is,

a)
b)
c)
d) +
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Correct Answer: D

Detailed Solution:

Given

000 → 001 → 011 → 010 → 110 →111 → 101 → 100 → 000 → ……….

Table for given condition

Present State Next state

Q2 Q1 Q0 Q2+ Q1+ Q0+ D2 D1 D0

0 0 0 0 0 1 0 0 1

0 0 1 0 1 1 0 1 1

0 1 1 0 1 0 0 1 0

0 1 0 1 1 0 1 1 0

1 1 0 1 1 1 1 1 1

1 1 1 1 0 1 1 0 1

1 0 1 1 0 0 1 0 0

1 0 0 0 0 0 0 0 0

D1 will have high logic at (1, 3 , 2 , 6) → D1 = 𝛴 m(1, 3, 2, 6)

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QUESTION 15:
Which of the following sequence generated at the output by the below circuit. Assume initial
state (Q3 Q2 Q1 Q0) of the circuit is 0001.

a) 0,1,1,1,1,0,…..

b) 0,0,1,1,1,1,…..

c) 0,0,0,1,1,1,……

d) 1,0,0,0, 1,0, …...

Correct Answer: d

Detailed Solution: D3 = Q1 XOR Q0, D2 = Q3, D1 = Q2 , D0 = Q1

Q3 Q2 Q1 Q0
0 0 0 1
1 0 0 0
0 1 0 0
0 0 1 0 1, 0, 0 , 0 , 1 , 0, …….
1 0 0 1
1 1 0 0
0 1 1 0
1 0 1 1
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