Raghavendra B S

28 July 2024 11:29

System verilog Interfaces:

Interface(Static and Synthesizable) allows us to encapsulate a multiple signals/ports together and are accessed by interface instance handle (usefull in complex designs).

1. It is easier to add new signals along with the existing connections in the interface(reusability).
2. signals within an Interface can be easily shared across the components by passing its handle.
3. It provides directional information (modports) and timing information (clocking blocks).
4. Interfaces can contain parameters, variables, functional coverage, assertions, tasks and functions.
5. Interfaces can contain procedural initial and always blocks and continuous assign statements.

Note: A module cannot be instantiated in an interface, But vice-versa is possible. Interfaces supports parameterization like modules.

➢ What are the advantages?

It also becomes easier to connect to designs regardless of the number of ports since it is encapsulated in an interface.

Example-1:

//Interface definition //Using Interface

//Main Design
module TB;
module RAM(Bus i1); interface Bus; Bus i2( ); //instantiate the interface
reg [7:0]mem[0:255]; logic [7:0]Addr,Data; logic [7:0]mem[0:255];
logic RWn; RAM r1(.i1(i2)); //connect it
always @(*) begin endinterface
if(i1.RWn) //Reading from memory condition initial begin //Drive and monitor
i1.Data=mem[i1.Addr]; i2.RWn=0;
else mem[i1.Addr]=i1.Data; //writing into memory i2.Addr=0;
end for(int i=0; i<7; i++) i2.Addr=i2.Addr+1;

endmodule i2.RWn=1;
i2.Data=mem[0];
end
endmodule

Example-2: (connecting multiplier with its testbench through interface driven by clock)

Multiplier Module interface mult_if (input logic clk, Testbench

reset); module Top;
logic [7:0] a, b; bit clk1, reset1;
module multiplier(mult_if inf2); logic [15:0] out; always #2 clk1 = ~clk1;
logic en,ack;
always@(posedge inf2.clk or posedge inf2.reset) begin endinterface mult_if inf1(.clk(clk1),.reset(reset1));
multiplier DUT(.inf2(inf1));
if(inf2.reset) {inf2.out,inf2.ack} <= 0;
else if(inf2.en) {inf2.out,inf2.ack} <= {{inf2.a * initial begin
inf2.b},{1'b1}}; {clk1,reset1} = 2'b01;
#2 {clk1,reset1} = 2'b01;
else inf2.ack <= 0; end
end
endmodule initial begin
// Drive stimulus through signals (if1.a, if1.b, if1.en, if1.ack)
#20 $finish;
end

initial begin
$dumpfile("dump.vcd"); $dumpvars;
end
endmodule

Example-3: (Using Modport)

Design Example: Two modules master and slave connected through bus structure through which address and data is communicated between master and slave using
interface.

//Master Design // Defining Interface // Defining Testbench

module mas(ms_if.master mif); interface ms_if(input clk); module tb();
logic sready,rstn; reg clk;
// accessible signals: mif.addr, mif.data, logic [1:0]addr; always #10 clk=~clk;
mif.sready, mif.rstn logic [7:0]data;
ms_if if0(.clk(clk));
endmodule modport slave(input addr,data,rstn,clk, output sready); top d0(.tif(if0));
modport master(input sready, clk, rstn output addr,data );
//slave Design // accessible signals: clk, if0.rstn……
endinterface
module sla(ms_if.slave sif); interface mult_if (input logic clk, reset); endmodule
// reg signals for storage purpose logic [7:0] a, b;
logic [15:0] out;
// accessible signals: sif.addr, sif.data, logic en,ack;
sif.sready, sif.rstn modport TB (output a,b, en, input out, ack);
modport RTL (input clk, reset, a,b, en, output out,
endmodule

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 modport RTL (input clk, reset, a,b, en, output out,
endmodule ack);
endinterface
//connecting master and slave together
via Interface with modport
module top(ms_if tif);

//passing modports to master and slave

mas m0(tif.master);
sla s0(tif.slave);
endmodule

Example: Multiplier
// Design code // Defining Interface // Defining Testbench
module multiplier(mult_if inf); interface mult_if (input logic clk, reset); module tb_top;
logic [7:0] a, b; bit clk;
always@(posedge inf.clk or posedge logic [15:0] out; bit reset;
inf.reset) begin logic en,ack;
if(inf.reset) begin modport TB (output a,b, en, input out, ack); always #2 clk = ~clk;
inf.out <= 0; modport RTL (input clk, reset, a,b, en, output out, ack);
inf.ack <= 0; endinterface initial begin
end clk = 0;
else if(inf.en) begin reset = 1;
inf.out <= inf.a * inf.b; #2;
inf.ack <= 1; reset = 0;
end end
else inf.ack <= 0;
end mult_if inf(clk, reset);
endmodule multiplier DUT(inf);

initial begin
// accessible signals: inf.TB.en , inf.TB.a ….

end
initial begin
$dumpfile("dump.vcd"); $dumpvars;
end
endmodule

Example-4(Parameterized Interface)

module Top; interface Channel #(parameter N=0)(input bit Clock, bit Ack, bit Sig); module TX(Channel Ch);
bit Clock, Ack, Sig; bit Buff[N-1:0];
initial for(int i=0; i<N; i++) Buff[i]=0;
//Instantiate the interface //accessible signals Ch.Clock, Ch.Ack, Ch.Sig….
Channel #(.N(7)) TheCh(.*); always @(posedge Clock)
if(Ack) Sig=Buff[N-1];
TX DUT(.Ch(TheCh)); else Sig=0; endmodule
…..
endmodule endinterface

Note: (.*) This is shorthand for

connecting the instance's ports to
signals with the same name in the
scope where it is used.

➢ What are clocking blocks within interface?

Signals that are specified inside a clocking block will be driven with that clock. There may be multiple clocking blocks within the interface.
• modports and interfaces by default cant specify timing requirements or synchronization schemes between signals. A clocking block defined between clocking and
endclocking helps to maintain some synchronization relation among signals.
• Only one clocking block per clock is supported in SV
• Clocking blocks allows inputs to be sampled and output to be driven at the specified clock event.

In the below example we have specified that by default, input must be sampled 1 time unit before(Input Skew) and output should be driven 2 time unit(output skew) after
posedge clk.
module multiplier(mult_if.RTL inf); interface mult_if (input logic clk, reset);
logic [7:0] a, b; module tb_top;
always@(posedge inf.clk or posedge inf.reset) begin logic [15:0] out; bit clk,reset;
//accessible signals inf.out, inf.ack, inf.en, inf.a, inf.b logic en,ack; always #2 clk = ~clk;

end initial begin

endmodule clocking cb @(posedge clk); clk = 0; reset = 1;
default input #1 output #2; #2;
input out, ack; reset = 0;
output a,b, en; end
endclocking
mult_if inf(clk, reset);
modport TB (clocking cb, input clk, reset); multiplier DUT(.inf (inf));
modport RTL (input clk, reset, a,b, en, output out,
ack);
initial begin
endinterface //accessible signals inf.out, inf.a, inf.b

end
Note: endmodule
• If we specify (default input #1ps output
@negedge )within clocking block means that
input is sampled at exactly 1ps, and outputs are
driven at negetive edge of clock instead of default
posedge.
• If default values not specified then input sampling

5.Interafces Page 2
 • If default values not specified then input sampling
and output driving takesplace exactly at clocking
event.

Example: Consider a design with inputs clk, req drives an output signal gnt. grant is provided as soon as request is received. Interface is created to for port signals. Next
we drive inputs to the design so that it gives back the grant signal. It can be simulated in output window that req is driven #5ns after the clock edge.

➢ What is a virtual Interface?

Virtual Interface: Acts as a handle or pointer to an interface instance, It allows different components of a testbench to refer to the same interface without being directly
connected. Virtual interface allows dynamic access to an Interface makes testbench components to interact with each other without direct instantiation(Flexibility,
Reusability and Modularity).
• Dynamic Binding: Virtual interfaces decouple/couple the testbench from specific instances of interfaces, enabling more modular and reusable testbench components.
• Modular Testbenches: Virtual interfaces allow for dynamic assignment of interfaces in UVM where testbench components (e.g., drivers, monitors) may be reused
across multiple DUTs without any hardwired mechanism.
module dut (bus_if bus1); // The DUT takes the interface bus_if(input logic clk); module tb;
interface as a port logic [7:0] data; logic clk;
logic valid; bus_if bus2(clk); // Instantiate the interface
virtual bus_if vif; // Declare a virtual interface with instance "vif"
always_ff @(posedge bus1.clk) begin // Interface tasks or functions can be added here
if (bus1.valid) task send_data(input logic [7:0] data_in); // Clock generation
$display("Received data: %0d", bus1.data); data,valid = {data_in,1'b1}; initial begin
end #1 valid = 0; clk = 0;
endmodule endtask forever #5 clk = ~clk;
end
endinterface
initial begin
// Assign the virtual interface to the actual interface instance
vif = bus2;
// Testbench drives signals through the virtual interface
vif.send_data(8'hAA); // Send some data
#10 vif.send_data(8'hBB); // Send some more data
end
// Instantiate DUT and connect it to the actual interface instance
dut dut_inst(bus2);

endmodule

Interface Bundles:
Interface bundles is a collection of related signals, variables or other interfaces grouped together under a single interface name. It allows for modular design by
encapsulating related functionality or communication protocols.
Interface bundles are commonly used to represent the communication between different modules or blocks within the design, providing the standardized interface for
interactions.

Example: In the below example, the design refrences the actual interface name for access to its signals. The example below shows myDesign and yourDesign declares a
port in the portlist called if0 of type myInterface to access signals.

5.Interafces Page 3
Extra Concepts(Not Important)
➢ What are input and output skews in a clocking blocks?
For input skew in a clocking block all input signals within that block will be sampled at skew time units before the clock event, and all output signals in that block will be
driven skew times after the corresponding clock event.
Skew is specified as a constant expression or as a parameter. In the example shown below, we declared the clocking block to describe the signals belonging to this block has
be be sampled. signal req is specified to have a skew of 1ps and will be sampled 1ps before the clock edge clk, The output signal gnt has an output skew of 2 time units,
hence will be driven 2ns after the clock edge, the last signal sig is of inout type and will be sampled 1ns before the clockedge and driven 3ns after clockedge.

An input skew of 1step indicates that the signal should be sampled at immediately before the positive clockedge.

Output skew: In SV output skew refers to maximum allowable difference in arrival times of signals on different output ports of a module. It represents the time delay
variation between when different output signals transition from one state to another. Minimizing output skew ensures the proper operation of synchronous high speed
design.
• In the testbench we use for loop to iterate through each stimulus and use different clocking block for each iteration.

Input skew: In system verilog input skew refers to the maximum allowable difference in arrival times of signal on different input ports of a module. It represents the
time delay variation between when different input signals are sampled or recognized by the module.
• The interface declaration shown below has different clocking blocks before each with a different input skew.
• In the testbench, we'll fork 4 different threads at a time 0ns where each thread waits for the positive edge of clock and samples the output from DUT.

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