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Electrical and Computer Engineering Department

ECE-238L COMPUTER LOGIC DESIGN

Lab Report: LAB 1 Comparator and 7-Segment display

Course Title: ECE-238 Computer Logic Design

Lab Number: Lab 1:

Section Name: 007 Thursday : 3:30 to 6:15 p.m

Name: - Ghazi Alazmi

Teammate: Abdullah Alazmi

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Contents
Introduction:................................................................................................................. 3
Lab 1A: Comparator Design ........................................................................................... 4
Screenshots for Lab 1A .............................................................................................. 4
VHDL Design Source File ........................................................................................ 4
Design Schematic .................................................................................................. 4
Truth Table ............................................................................................................. 5
Simulation Source File ............................................................................................ 6
Simulation Waveform ............................................................................................. 7
Constraints File ...................................................................................................... 8
Summary: ................................................................................................................. 8
Challenges: ............................................................................................................... 8
Improvements: .......................................................................................................... 9
Lab 1B: 7 Segment Display .......................................................................................... 10
Screenshots for Lab 1B ............................................................................................ 10
VHDL Design Source File ...................................................................................... 10
Design Schematic ................................................................................................ 12
Simulation Source File .......................................................................................... 13
Simulation Waveform ........................................................................................... 13
Constraints File .................................................................................................... 14
Summary: ............................................................................................................... 14
Challenges: ............................................................................................................. 15
Improvements: ........................................................................................................ 15
Discussion and Conclusion: ........................................................................................ 15
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Introduction:
The purpose of this lab is to develop and test digital logic designs using VHDL and FPGA
hardware. LAB1A focuses on implementing basic comparators using VHDL to compare two
single-bit inputs and generate output signals indicating equality, greater than, or less than
conditions. LAB1B extends this concept by using a 7-segment display to visually represent
the results of the comparison. This exercise helps to understand fundamental digital
design principles and the application of VHDL for creating practical digital circuits.

The General Block Diagram of Comparator is given below as,

And the 7-segment display is shown below as,

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Lab 1A: Comparator Design

Screenshots for Lab 1A

VHDL Design Source File

Design Schematic
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Truth Table
Inputs Outputs
A B F_E F_G F_L
0 0 1 0 0
0 1 0 1 0
1 0 0 0 1
1 1 1 0 0
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Simulation Source File

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Simulation Waveform
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Constraints File

Summary:
We focused on designing basic Boolean logic gates using VHDL. The primary task involved
creating a VHDL module to implement AND, OR, and NOT gates, followed by rigorous
simulation to verify their functionality. The accuracy of the logic gates was confirmed by
comparing the simulation results with theoretical truth tables. This part of the lab provided
a solid foundation in understanding and verifying fundamental logic operations.

Challenges:
One notable challenge was ensuring that the VHDL code accurately represented the
intended Boolean functions. We encountered difficulties with interpreting simulation
results, which required iterative debugging to align the outputs with the expected behavior.
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Additionally, configuring the FPGA constraints file correctly was crucial to achieving
successful hardware implementation.

Improvements:
Future labs could benefit from more detailed guidance on debugging VHDL code and
interpreting simulation results. Providing additional resources or examples for common
issues encountered during simulation and hardware testing could enhance the learning
experience and streamline the development process.
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Lab 1B: 7 Segment Display

Screenshots for Lab 1B
VHDL Design Source File
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Design Schematic
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Simulation Source File

Simulation Waveform
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Constraints File

Summary:
Lab 1B extended our understanding of VHDL by involving the design of a module to drive a
seven-segment display. We developed a VHDL design to display characters such as 'E' and
'L' based on input signals. This lab required an understanding of both combinational logic
and the specific segment encoding needed to represent different characters on the display.
The accuracy of the seven-segment display outputs was validated through comprehensive
simulation and hardware testing.
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Challenges:
A key challenge was mapping the correct segments to display the required characters
accurately. Ensuring that the display showed the correct character required a precise
understanding of the segment encoding and careful verification through simulation.
Configuring the FPGA to display the correct segments based on different input conditions
also required careful attention to detail.

Improvements:
Providing more extensive examples and guidelines on segment encoding for seven-
segment displays could be beneficial. Additionally, clearer instructions on debugging and
verifying display outputs could improve the ease of achieving correct results in future lab
sessions.

Discussion and Conclusion:

In LAB1A we implemented a simple comparator using Boolean logic to compare two inputs
and generate signals indicating equality, greater than, or less than. This exercise helped us
understand how to build basic combinational logic circuits and test them through
simulation.

In LAB1B we extended the comparator design by adding a 7-segment display output. The
display showed characters based on the comparison results, allowing us to visualize the
output. Mapping the correct segment patterns to display characters in an active-low
configuration required careful attention to detail. Overall, the lab reinforced our
understanding of combinational logic and 7-segment display control in digital circuits. For
future labs, visual aids for 7-segment display configurations could simplify the design
process.