Introduction to FPGA Technology

FPGAs are Field Programmable Gate Arrays

• Largest players in the FPGA market are Xilinx (acquired by AMD
in 2022) and Intel (formerly Altera, which Intel acquired in
2015)
• FPGAs first on the market in the mid-1980’s
• As review, we know that Central Processing Units (CPUs) are
microprocessors that execute software which is typically
accessed through off-chip memory (RAM).

Picture: PIC microcontroller from: https://en.wikipedia.org/wiki/Microcontroller#/media/File:PIC12C508-HD.jpg

• Microcontrollers integrate a CPU, RAM, Flash (or other

non-volatile storage), and often other useful peripherals
such as:
• Serial interfaces (e.g. UART, SPI, I2C, CAN)
• Analog-to-Digital Converters (ADCs)
• Digital-to-Analog Converters (DACs)
• Pulse-Width-Modulation (PWM) generators
 Introduction to FPGA Technology (Intel)
• FPGAs are composed of Configurable Logic Blocks (CLBs),
also known as Logic Elements (LEs).
• The MAX 10 has 16 LEs in each Logic Array Block (LAB).
• The MAX 10 FPGA on the DE10-Lite board has 50,000 LEs
(maximum of the MAX 10 family).
• The Intel Stratix FPGA can have up to 10.2 million LEs.

Picture: https://www.intel.cn/content/dam/altera-www/global/zh_CN/pdfs/literature/hb/max-10/m10_handbook.pdf
Introduction to FPGA Technology (Intel)

• Internal Flash
• UFM: User Flash Memory
• CFM: Configuration Flash Memory
• PLL: Phase Locked Loop – used to modify the external clock frequency
entering the FPGA
• ADC: Analog-to-Digital Converter

• Aside: I/O Blocks and internal logic can have different voltages
Picture: https://www.intel.cn/content/dam/altera-www/global/zh_CN/pdfs/literature/hb/max-10/m10_handbook.pdf
Introduction to FPGA Technology (Intel)
• FPGAs are composed of Configurable Logic
Blocks (CLBs), also known as Logic
Elements (LEs).
• The MAX 10 has 16 LEs in each Logic Array
Block (LAB).
• The MAX 10 FPGA on the DE10-Lite board
has 50,000 LEs

Pictures: https://www.intel.cn/content/dam/altera-
www/global/zh_CN/pdfs/literature/hb/max-10/m10_handbook.pdf
Introduction to FPGA Technology
• FPGAs are composed of Configurable Logic
Blocks (CLBs), also known as Logic
Elements (LEs).
• The MAX 10 has 16 LEs in each Logic Array
Block (LAB).
• The MAX 10 FPGA on the DE10-Lite board
has 50,000 LEs

Pictures: https://www.intel.cn/content/dam/altera-
www/global/zh_CN/pdfs/literature/hb/max-10/m10_handbook.pdf

x16

Logic Element (LE)

 Introduction to FPGA Technology (Intel)
Logic Element (LE)

Picture: https://www.intel.cn/content/dam/altera- Example: 4-input AND

www/global/zh_CN/pdfs/literature/hb/max-10/m10_handbook.pdf
IN_0 IN_1 IN_2 IN_3 OUT
• The 4-input Look Up Table (LUT) 0 0 0 0 0
acts like a ROM and can implement 0 0 0 1 0
any 4-input combinational logic 0 0 1 0 0
function. 0 0 1 1 0
4-input LUT 0 1 0 0 0
0 1 0 1 0

IN_0 0 1 1 0 0
0 1 1 1 0

IN_1 1 0 0 0 0
1 0 0 1 0
OUT
IN_2 1 0 1 0 0
1 0 1 1 0
IN_3 1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 1
 Introduction to FPGA Technology (Xilinx)

Picture: https://docs.xilinx.com/v/u/en-US/ug474_7Series_CLB
 Introduction to FPGA Technology (Xilinx)

Picture: https://docs.xilinx.com/v/u/en-US/ug474_7Series_CLB
 Introduction to FPGA Technology (Xilinx)

Artix-7 Xilinx part number: XC7A35T- 1CPG236C

Picture: https://digilent.com/reference/programmable-logic/basys-3/reference-manual
 Introduction to FPGA Technology
Application Specific Integrated Circuits (ASICs)
• A circuit specially design for a specific use
• Very expensive for initial design costs (up to millions of
dollars), known as Non-Recurring Engineering (NRE)
• Very expensive software tools
• Very expensive manufacturing costs – optical masks for
photolithography, very expensive fabrication plants (fabs)
• Very time consuming to go from concept to production
• For large volumes, e.g. >100,000 units/year, then per unit costs
are low

Gate Arrays
• In-between ASICs and FPGAs
• Mostly like an ASIC with regular circuit patterns, but metal
layers can be customized to create customized circuits
(actually semi-custom)
• Mask programmable gate arrays cannot be reprogrammed (i.e.
not “field-programmable”) after they have been manufactured
• FPGAs can be fairly competitive on cost, and have the
advantage of being reprogrammable.
 Introduction to FPGA Technology
Advantages of FPGAs
• Can implement any digital circuit, including CPUs (called “softcores”)
– NIOS for Intel, MicroBlaze for Xilinx (or other CPUs like ARM or
custom). NIOS-V is the latest for Intel (RISC-V implementation)
• Circuits can work in parallel to greatly speed up computations, so can
be much faster than CPUs
• Timing can be very deterministic, compared to a CPU
• Massive number of I/Os
• Can be lower power than CPUs, depending on the application
• Lower initial costs than ASICs and at low volumes
• Can be reprogrammed if there are bugs or additional functionality is
required in the future
 Introduction to FPGA Technology
Disadvantages of FPGAs
• Expensive – more expensive than microprocessors and more
expensive than ASICs at higher volumes.
• Difficult to design FPGA applications, more difficult than for CPUs
• Can be power hungry
• Some applications cannot be effectively parallelized, see Amdahl’s
Law

Amdahl's Law, formulated by Gene

Amdahl in 1967, is a key principle in
parallel computing that explains the
limits of system performance
enhancements. It highlights how the
non-parallelizable portion of a task
constrains overall speedup, showing
that even with infinite processors, the
improvement is limited by the
sequential part of the task.

𝟏 Graph from: https://en.wikipedia.org/wiki/Amdahl%27s_law

𝑺=
𝑷
𝟏 −𝑷 +𝑵 𝟏 𝟏
lim 𝑺 = 𝑷 =
Where: 𝑁→∞ 𝟏−𝑷 +𝑵 𝟏−𝑷
• S is the overall Speedup
• P is the proportion of the task that can be The equation is simplified when the number of
parallelized parallel processors becomes large, and you can see
• 1 – P is the proportion of the task that is this result in the graph above, the plots for 50% to
inherently sequential (cannot be parallelized) 𝟏
• N is the number of parallel processors 95% converge asymptotically to
𝟏−𝑷

Dr. Mike Smith – What is the first rule of assembly language

programming?
Dr. Denis Onen – What the first rule of designing with FPGAs?
 Introduction to FPGA Technology
Applications Areas of FPGA Technology
• Data Centers (e.g. Amazon EC2 F1 Instances for cloud computing)
• Consumer Electronics
• High Performance Computing
• Medical
• Communications
• Automotive
• Aerospace
• Test and Measurement
• Industrial
• Internet of Things (IoT)

Some applications
- Data analytics
- Video, image, and signal processing (e.g. Subaru EyeSight system)
- Machine learning (very strong as inference engine)
- NoLoad Storage & Compute Workload Acceleration (Eideticom)
- Security
- Real-time analytics (e.g. face/motion detection)
- Codecs
- Motor control
- Power supply control
 Continuum of Configurable Computing
The “continuum of configurable computing” is a concept that relates
flexibility (able to do a variety of tasks, development time) versus
performance (execution speed, power consumption) in computing
platforms. On one end, general purpose processors are very flexible, but
can be limited in performance. On the other end, ASICs have high
performance but limited flexibility.

E.g. ASICs GPUs are somewhere here

E.g. FPGAs E.g. customizable processors like ARM

Cortex with custom instructions or
NIOS or MicroBlaze softcore
processors
E.g. DSP processors like
TI MSP 430, TI TMS320,
AD SHARC

CPUs like Intel i7,

ARM

Picture: N. Dutt and Kiyoung Choi, "Configurable processors for embedded computing," in Computer, vol. 36, no. 1, pp. 120-123, Jan. 2003,
doi: 10.1109/MC.2003.1160063.
 Continuum of Configurable Computing
Example showing different paradigms for computation (hardware vs
software)

Horner’s Rule: an efficient algorithm used to evaluate polynomials numerically by using nested
operations to reduce the number of additions and multiplications. Popularized by George
Horner in the early 1800’s, but the method was known for centuries in China and Persia.

y = A*x2 + B*x + C y = A*x2 + B*x + C

t1 = x*x t1 = A*x
t2 = A*t1 t2 = t1 + B
t3 = B*x t3 = t2*x
t4 = t2 + t3 y = t3 + C
y = C + t4
Reduced to 4 additions/multiplications
5 additions/multiplications by using by nesting the operations as:
the standard polynomial form directly y = (A*x + B)*x + C

The nesting is accomplished by factoring

out the variable term, x.

Picture: A. DeHon and J. Wawrzynek, "Reconfigurable Computing: What, Why, and Implications for Design Automation," DAC 99, New
Orleans, Louisiana: 1999 ACM 1-58113-109-7/99/06.