Introduction to Hardware

Description Languages (HDLs)

There are several HDLs, the development of which was to replace
schematic diagrams as the means to design digital hardware.
There were tremendous productivity gains for designers using
HDLs, for designing, modifying, and simulating digital circuits.

Schematic

SystemVerilog

VHDL

Code and Circuits from: Digital Design

and Computer Architecture, 2nd Ed, by
Harris and Harris
 Introduction to Hardware
Description Languages (HDLs)
There are several HDLs, the development of which was to replace
schematic diagrams as the means to design digital hardware. There
were tremendous productivity gains for designers using HDLs, for
designing, modifying, and simulating digital circuits.
Verilog
• Developed in 1984 by Gateway Automation
• Originally a proprietary language, then made open standard in 1990
• Became IEEE Standards 1364-1995, 1364-2001, 1364-2005
• Similar in appearance to C programming
SystemVerilog
• Extension of Verilog to more strongly support verification, using
Java-like code to support object-oriented programming (to promote
code reuse and scalability for UVM (Universal Verification
Methodology))
• Released in 2002, became IEEE Standards 1800-2005, 1800-2009,
1800-2017
• Verilog is a subset of SystemVerilog
VHDL
• VHSIC-HDL (VHDL), where VHSIC-HDL fully stands for Very High
Speed Integrated Circuit Hardware Description Language
• Developed by committee in 1981, became IEEE Standards 1067-
1987, 1067-1993, 1067-2002, 1067-2008, 1067-2011, 1067-2019
• Based Ada programming language
• VHDL is a verbose and strongly-typed language
Which language should you use?
 Introduction to Hardware
Description Languages (HDLs)
Some other languages that can be used for designing digital
hardware
• AHDL (Altera Hardware Description Language)
• OpenCL
• C-like and supports parallelism
• Chisel
• Based on Scala, HDL from UC Berkeley, gets converted to
Verilog for RTL code. The open-source RISC-V is described
using Chisel.
• Python (MyHDL)
• High-Level Synthesis (HLS)
• Converts high-level programming languages
(C/C++/SystemC) to HDL (e.g. VHDL, Verilog)
 Introduction to Hardware
Description Languages (HDLs)
Thinking about Hardware Description vs Software Programming
Introduction to Hardware Description Languages (HDLs)
Synthesizable vs Non-synthesizable code

Synthesizable:
Can infer digital
hardware
i.e. can generate
hardware

Non-synthesizable:
Cannot infer digital
hardware
i.e. suitable for
testbenches

A couple major hints for

non-synthesizable code is
time delays and
sometimes for loops
 Introduction to Hardware
Description Languages (HDLs)
Behavioral code vs RTL code vs Structural code More
abstract
Behavioral Code
• Describes the “behavior” of a system at a high level, showing the
relationships between inputs and outputs.
• Can be synthesizable (can become hardware).
• Can be non-synthesizable (useful for testbenches, i.e. simulation).

Register Transfer Level (RTL) Code

• Describes hardware in terms of the logic and logic between registers
(i.e. Flip Flops, regisers, multiplexers, combinational logic).
• Is always synthesizable (can become hardware), by definition (if
designed correctly).
• If we have synthesizable code that describes operations relative to
clock cycles, even though it may be written at a high level of
abstraction (i.e. it’s not clear exactly what hardware would be
generated), we would still consider it to be RTL code.

Structural Code
• Describes the connections between modules, think of computer
motherboard as the connection for a number of integrated circuits –
the integrated circuits are the modules and the motherboard is the
structural code to connect the modules together. In this case,
structural code is synthesizable.
• The “top_level” in RTL code should be structural code, for moderately
complex designs or complex designs.
• Lower level modules in RTL code can also use structural code to
instantiate lower level modules, for hierarchical design.
• Testbenches feature structural code when the Unit Under Test (UUT)
or Device Under Test (DUT) is instantiated within the testbench.
Less
abstract
Behavioral code vs RTL code vs Structural code
Behavioral Code

RTL Code

Structural Code (see next slide for circuit diagram)

Structural code
 Introduction to Hardware Description Languages (HDLs)
FPGA Design Flow

1. Design Entry (writing VHDL/Verilog RTL code)

2. Logic Verification (simulating design with testbenches)

Beginners should do
frequent synthesis checks

3. Synthesis (checking if design can be made to hardware)

4. Mapping (converts synthesis results to FPGA (or ASIC) technology)

5. Place and Route (places mapping results to specific locations on chip)

6. Timing Analysis (checks if design will be as fast as is required)

7. Configure FPGA (programs the FPGA according to the design)

8. Test FPGA (test in real hardware)

 Introduction to Hardware Description Languages (HDLs)
FPGA Design Flow (for experienced designers)

1. Design Entry (writing VHDL/Verilog RTL code)

 Introduction to Hardware Description Languages (HDLs)
FPGA Design Flow

1. Design Entry (writing VHDL/Verilog RTL code)

2. Logic Verification (simulating design with testbenches)

Can you spot a discrepancy?

 Introduction to Hardware Description Languages (HDLs)
FPGA Design Flow (for experienced designers)

1. Design Entry (writing VHDL/Verilog RTL code)

2. Logic Verification (simulating design with testbenches)

3. Synthesis (checking if design can be made to hardware)

 Introduction to Hardware Description Languages (HDLs)
FPGA Design Flow (for experienced designers)

1. Design Entry (writing VHDL/Verilog RTL code)

2. Logic Verification (simulating design with testbenches)

3. Synthesis (checking if design can be made to hardware)

4. Mapping (converts synthesis results to FPGA (or ASIC) technology)

Logic Element (LE)

Picture: https://www.intel.cn/content/dam/altera-www/global/zh_CN/pdfs/literature/hb/max-10/m10_handbook.pdf
 Introduction to Hardware Description Languages (HDLs)
FPGA Design Flow (for experienced designers)

1. Design Entry (writing VHDL/Verilog RTL code)

2. Logic Verification (simulating design with testbenches)

3. Synthesis (checking if design can be made to hardware)

4. Mapping (converts synthesis results to FPGA (or ASIC) technology)

5. Place and Route (places mapping results to specific locations on chip)

Pictures: https://www.intel.cn/content/dam/altera-
www/global/zh_CN/pdfs/literature/hb/max-
10/m10_handbook.pdf
 Introduction to Hardware Description Languages (HDLs)
FPGA Design Flow (for experienced designers)

1. Design Entry (writing VHDL/Verilog RTL code)

2. Logic Verification (simulating design with testbenches)

3. Synthesis (checking if design can be made to hardware)

4. Mapping (converts synthesis results to FPGA (or ASIC) technology)

5. Place and Route (places mapping results to specific locations on chip)

6. Timing Analysis (checks if design will be as fast as is required)

7. Configure FPGA (programs the FPGA according to the design)

8. Test FPGA (test in real hardware)

 Introduction to Hardware Description Languages (HDLs)
I/O Pin Mapping Constraints (and Timing Constraints, shown on next page)
• Provided in Xilinx Vivado by .xdc file
• Specifies which physical FPGA pins are assigned to the design’s inputs
and outputs
• Vital for the Place and Route step (Step 5 in FPGA Design Flow)

Notice the name gets edited in

2 places for each signal.

The signal names must match

the inputs and outputs in the
top_level code of your design.
 Introduction to Hardware Description Languages (HDLs)
Timing Constraints (same file as previous slide)
• Provided in Xilinx Vivado by .xdc file
• Specifies the minimum clock frequency required by the design
• Vital for the Timing Analysis step (Step 6 in FPGA Design Flow)
• If fails, then Vivado repeats the synthesis steps to improve the design to
meet timing requirements
• If still fails, then it’s up to the designer to take different approach

Specify this for

50% duty cycle
(i.e. 10/2 = 5)
set_property PACKAGE_PIN W5 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
Desired clock period (ns), specified by
designer so 10.00 means 10.00 ns.
1/(10.00 ns) = 100 MHz desired clock
Timing Summary Report from Vivado

How to compute the maximum FPGA clock frequency:

1 1
𝑀𝑎𝑥_𝑓𝑟𝑒𝑞 = = = 796 𝑀𝐻𝑧
𝑑𝑒𝑠𝑖𝑟𝑒𝑑_𝑐𝑙𝑜𝑐𝑘_𝑝𝑒𝑟𝑖𝑜𝑑 − 𝑊𝑁𝑆 10.00 𝑛𝑠 − 8.744 𝑛𝑠