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L4a Intro To SystemVerilog

Chapter 4 of 'Digital Design & Computer Architecture' focuses on Hardware Description Languages (HDLs), specifically SystemVerilog and VHDL, which are essential for specifying logic functions in digital design. The chapter covers key topics such as combinational and sequential logic, module declarations, and the synthesis process from HDL code to hardware gates. It emphasizes the importance of understanding hardware implications while coding in HDLs to avoid common pitfalls.

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6 views15 pages

L4a Intro To SystemVerilog

Chapter 4 of 'Digital Design & Computer Architecture' focuses on Hardware Description Languages (HDLs), specifically SystemVerilog and VHDL, which are essential for specifying logic functions in digital design. The chapter covers key topics such as combinational and sequential logic, module declarations, and the synthesis process from HDL code to hardware gates. It emphasizes the importance of understanding hardware implications while coding in HDLs to avoid common pitfalls.

Uploaded by

ibraestheticss
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Digital Design &

Computer Architecture
Sarah Harris & David Harris

Chapter 4:
Hardware Description
Languages
These lecture slides are based on the above textbook, with modifications by the instructor
Chapter 4 :: Topics
• Introduction
• Combinational Logic
• Delays
• Sequential Logic
• Combinational Logic w/ Always
• Blocking & Nonblocking Assignments
• Finite State Machines
• Parameterized Modules
• Testbenches

Digital Design & Computer Architecture Hardware Description Languages 2


Chapter 4: Hardware Description
Languages

Introduction

Based on textbook section 4.1

Textbook video lecture: https://www.youtube.com/watch?v=sVy31HJj4lA


Introduction
• Hardware description language (HDL):
– Specifies logic function only
– Computer-aided design (CAD) tool produces or synthesizes
the optimized gates
• Most commercial designs built using HDLs
• Two leading HDLs:
– SystemVerilog
• Developed in 1984 by Gateway Design Automation (as Verilog)
• IEEE standard (1364) in 1995 (still Verilog)
• Extended in 2005 (IEEE STD 1800-2009) (now formally SystemVerilog)
– VHDL 2008
• Developed in 1981 by the Department of Defense
• IEEE standard (1076) in 1987
• Updated in 2008 (IEEE STD 1076-2008)
Digital Design & Computer Architecture Hardware Description Languages 4
HDL to Gates
• Simulation
– Inputs applied to circuit (manually or “test vectors”)
– Outputs checked for correctness (visually by inspection of
waveforms or by “self-checking” testbenches that report results
of testing)
– Millions of dollars saved by debugging in simulation instead of
hardware (i.e. by finding faults earlier in the design cycle)
• Synthesis
– Transforms HDL code into a netlist describing the hardware (i.e.,
a list of gates and the wires connecting them), uses optimization
(fyi, the concept of netlist is also used in PCB design)

Digital Design & Computer Architecture Hardware Description Languages 5


HDL: Hardware Description Language

IMPORTANT:
When using an HDL, think of the hardware
the HDL should produce, then write the
appropriate idiom (e.g. a coding pattern)
that implies that hardware.

Beware of treating HDL like software and


coding without thinking of the hardware.

Digital Design & Computer Architecture Hardware Description Languages 6


SystemVerilog Modules

a
SystemVerilog
Verilog
b y
Module
Module
c

Two types of Modules*:


– Behavioral: describe what a module does
– Structural: describe how it is built from simpler
modules (useful for hierarchical design)

*according to the textbook, there others like RTL and gate-level


Digital Design & Computer Architecture Hardware Description Languages 7
Module Declaration
module example(input logic a, b, c,
output logic y);
// module body goes here, giving the module’s functionality
endmodule

• module/endmodule: required to begin/end module


• example: name of the module
• port list: inputs and outputs of the module
• logic data type: 4 values (0, 1, z, x) Recall:
z is floating (high impedance)
x is don’t care
a
SystemVerilog
Verilog
b y
Module
Module
c

Digital Design & Computer Architecture Hardware Description Languages 8


Behavioral SystemVerilog
module example(input logic a, b, c,
output logic y);
assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & c;
endmodule
• module/endmodule: required to begin/end module
• example: name of the module
• port list: inputs and outputs of the module
• logic data type: 4 values (0, 1, z, x)
• assign: statement that describes combinational logic
• Operators:
~: NOT
&: AND
|: OR
^: XOR
SystemVerilog files have the .sv file extension.
Module and signal names may not begin with a digit.
Digital Design & Computer Architecture Hardware Description Languages 9
HDL Simulation
module example(input logic a, b, c,
output logic y);
assign y = ~a & ~b & ~c | // note the statement is spanning
a & ~b & ~c | // multiple lines (// is a comment)
a & ~b & c;
endmodule
Is the assign statement more clear
here or in the previous slide?

is y correct?
Digital Design & Computer Architecture Hardware Description Languages 10
HDL Synthesis
module example(input logic a, b, c,
output logic y);
assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & c;
endmodule

Compare synthesis result to the explicit


Synthesis: logic described above, why the difference?
b
c y

un5_y
y

un8_y

Recall “sillyfunction” from previous lecture (same code)

Digital Design & Computer Architecture Hardware Description Languages 11


SystemVerilog Syntax
• Case sensitive
– Example: reset and Reset are not the same signal.
– This will cause tricky errors when coding!!
• No names that start with numbers
– Example: 2mux is an invalid name
• Whitespace is ignored
• Comments:
– // single line comment
– /* multiline
comment */
– Some designers write their comments before coding
• Statement termination:
– Semi-colon (;)

Digital Design & Computer Architecture Hardware Description Languages 12


Structural SystemVerilog
module and3(input logic a, b, c,
output logic y);
assign y = a & b & c;
endmodule

module inv(input logic a,


output logic y);
assign y = ~a;
endmodule

// 3 input NAND in structural coding with positional connections


module nand3(input logic a, b, c
output logic y);
logic n1; // internal signal (acts like an
// internal connecting wire)

and3 andgate(a, b, c, n1); // instance of and3 (andgate is label)


inv inverter(n1, y); // instance of inv (inverter is
endmodule // instance label)

Digital Design & Computer Architecture Hardware Description Languages 13


Structural SystemVerilog
Repeat previous example but with
module and3(input logic a, b, c, explicit connections (not positional).
output logic y); Use this style and save yourself
assign y = a & b & c; grief!!
endmodule

module inv(input logic a,


output logic y);
assign y = ~a;
endmodule

// 3 input NAND in structural coding with explicit connections


module nand3(input logic a, b, c
output logic y);
logic n1; // internal signal (acts like an
// internal connecting wire)

and3 andgate(.a(a), .b(b), .c(c), .y(n1)); //explicit connections


inv inverter(.a(n1), .y(y)); //explicit connections
endmodule

Digital Design & Computer Architecture Hardware Description Languages 14


HDL Example 4.1 COMBINATIONAL LOGIC

Digital Design & Computer Architecture Hardware Description Languages 15

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